CN1521644A - Digital signal processor with a restructurable system hardware stack - Google Patents
Digital signal processor with a restructurable system hardware stack Download PDFInfo
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- CN1521644A CN1521644A CNA031153755A CN03115375A CN1521644A CN 1521644 A CN1521644 A CN 1521644A CN A031153755 A CNA031153755 A CN A031153755A CN 03115375 A CN03115375 A CN 03115375A CN 1521644 A CN1521644 A CN 1521644A
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Abstract
A digital signal processor with reconfiguration system hardware depot relating to the signal processing technology field of digit signal processor, wherein the operation register of the system hardware depot includes a system hardware depot index finger register connected to the system hardware depot through the address bus, by arranging the port value, the digital signal processor according to the invention enables the program operate under the dissimilar system hardware depot environment of 16 items, 32 items, 48 items or 64 items. The invention can facilitate the user to estimate the program execution efficiency, consider the cost for each system hardware depot, and find the optimum performance-cost ratio.
Description
Technical field
What the present invention relates to is a kind of digital signal processor, and particularly a kind of digital signal processor that has the reconfigurable system hardware stack belongs to digital signal processing technique field.
Background technology
" digital signal processor integrated circ (the DSP Integrated Circuits) " that publish of U.S. academic press (Academic Press) in 1999 (author: Lars Wanhammar) disclose a kind of stack operation method of digital signal processor of prior art.In existing digital signal processing calculating process, for cycling, subroutine and interrupt service routine, the operation that all needs to carry out pop down He move back stack.In order to improve the operational efficiency of program, different with general CPU, existing digital signal processor (DSP) generally adopts the hardware loop of zero-overhead, the sub-routine operation of zero-overhead and interrupt service routine operation.So-called zero-overhead is meant not to be needed with extra instruction the chip status value of carrying out needing to preserve before above-mentioned cycling, subroutine and the interrupt service routine to be pressed into storehouse, perhaps when finishing aforesaid operations, state value is taken out from storehouse for the state that recovers chip.For instance, before the general cycling, need be circulation start address and cycle index pop down at that time, in addition at that time instruction counter value and status register value is pressed into storehouse, like this can be in multinest circulation, cycling that can the correct execution last layer after subcycle finishes.For the hardware loop of zero-overhead, do not need extra four instructions to carry out push operation in the program, but chip carry out these operations automatically.Yet must in chip, dispose the hardware loop that system hardware stack at a high speed could be realized above-mentioned zero-overhead, the sub-routine operation of zero-overhead and interrupt service routine operation.Need the number of times of pop down many more, the system hardware stack is big more, and chip area is big more like that, and cost is high more.Size according to the characteristics configure system hardware stack of program just can reach best cost performance.The size of original common design system hardware stack is fixed, and is unfavorable for like this adjusting optimum cost performance according to the application program of reality.
Summary of the invention
The objective of the invention is to overcome deficiency of the prior art, a kind of digital signal processor that has the reconfigurable system hardware stack is provided, the size that is provided with the system hardware stack by port signal is reconstructed operation, to be used for evaluating system hardware stack efficient and utilization factor in actual applications.So that use only system hardware stack size during volume production, reach best price/performance ratio.
The present invention is achieved by the following technical solutions, the present invention mainly comprises: the address generator unit, instruction decoding unit, digital data processing unit, digital data memory, procedure control unit, instruction decoding unit is connected to procedure control unit, procedure control unit is connected to the address generating unit, instruction decoding unit and digital data processing unit, the two-way digital data memory that is connected to of digital data processing unit, the address generator unit is connected to digital data memory by address bus, digital data memory is connected to the address generator unit by data bus simultaneously, instruction decoding unit and digital data processing unit, digital data bus links to each other with digital data memory, the digital data memory storage provides will be by the numerical data of described digital signal processor operation, instruction decoding unit is the instruction that described digital signal processor extracts configuration program, and instruction translation become control signal and data-signal, digital data processing unit carries out digital operation or logical operation according to control signal to the data of input, the address generator unit generates the address of access digital data storer, and procedure control unit generates the operation command signal of other unit of the described digital signal processor of control according to described instruction.
Comprise the system hardware stack in the procedure control unit and to the operation control register of system hardware stack.The operation note of system hardware stack comprises the system hardware stack pointer register, and the system hardware stack pointer register is connected on the system hardware stack by address bus.64 clauses and subclauses of the physically maximum placement of system hardware stack, each clauses and subclauses is 24.One two port is arranged on the chip periphery pin, by this two bit port is carried out 00,01,10,11 these four kinds of different settings, this port signal line is connected on the selector switch in the procedure control unit, and stack pointer register also is connected on the selector switch, and upwards spill over is drawn from selector switch, the address bus of drawing from selector switch is connected on the system hardware stack, can be configured to 16 clauses and subclauses to the system hardware stack like this, 32 clauses and subclauses, four kinds of different sizes of 48 clauses and subclauses and 64 clauses and subclauses.
The principle of work of digital signal processor of the present invention is as follows: digital signal processor is placed with 64 clauses and subclauses of system hardware stack when design, but in use, the user can be by being provided with the signal value of peripheral port, and the visible system hardware stack of program is set to 16,32,48 or 64 clauses and subclauses.The size of stack pointer register is 6 position digital signals, but is provided with at each clauses and subclauses, and the available size of stack pointer register can be adjusted automatically.Such as when the system hardware stack is set to 16, the size of stack pointer register can only be 0～15, if surpass dividing value up and down, numerical value can be got back in the boundary by automatic delivery.Simultaneously, the upwards overflow position of the system hardware stack in the status register of chip is with overflow position also can be according to different port arrangement demonstration error messages downwards, when being configured to have 16 hardware stacks when chip, pop down is gone into 17 24 data will produce the error message of upwards overflowing, although the actual system hardware stack that has 64 clauses and subclauses in the chip.After the digital signal processor design is finished,
The present invention has substantive distinguishing features and marked improvement, whole design is imported in the programmable logic array (FPGA), then by port value is set, program may operate under the environment of the different system hardware stack of 16 clauses and subclauses, 32 clauses and subclauses, 48 clauses and subclauses or 64 clauses and subclauses, the user can begin to attempt working procedure from the system hardware stack size of minimum, from small to large, the execution efficient of evaluate application on the basis of different system hardware stack sizes, consider the cost of each system hardware stack then, find optimum cost performance.Just can use such system hardware stack size during later on real chip volume production.For saving cost very big benefit is arranged like this.
Description of drawings
The structured flowchart of Fig. 1 digital signal processor of the present invention
The structured flowchart of system hardware stack in Fig. 2 digital signal processor of the present invention
Embodiment
As shown in Figure 1, digital signal processor cores get 5 has procedure control unit 1, address generator unit 2, instruction decoding unit 3 and digital data processing unit 4, and digital data memory 6 links to each other with digital signal processor cores get 5.Instruction decoding unit 3 is translated into order code the control signal of the representative instruction meaning of digital signal processor cores get 5 inside, these described control signals are connected to procedure control unit 1, and procedure control unit 1 sends the required control signal of these module work of control to address generating unit 2, instruction decoding unit 3 and digital data processing unit 4.Digital data processing unit is accepted the data from digital data memory 6, and it is carried out computing.Address generator unit 2 carries out address arithmetic, and the result of address arithmetic is connected on the digital data memory 6 by address bus.Digital data memory 6 is put into the corresponding digital data on the data bus according to the address that address generator unit 2 produces, and described data bus is connected to instruction decoding unit 3 and data processing unit 4, for they provide instruction and operand.
As shown in Figure 2, the system hardware stack is the part in the program controling module, and the total system hardware stack is divided into 4 data blocks: data block 11, data block 12, data block 13 and data block 14.The size of each data block is 16 24 clauses and subclauses.Data in the stack pointer register 16 are carried out behind certain modulo operation address as the access system hardware stack by selector switch 15.Size_sel[1:0] be the input signal of chip, it is the selection control signal in the selector switch 15.
In selector switch 15, upwards the generation of spill over (overflow) is according to selecting control signal size_sel[1:0] difference and different.Upwards spill over is transferred in the status register of chip, and the user can know in view of the above for the operation of stack overflows.Size_sel[1:0] equal 00 expression the stack of 16 clauses and subclauses, size_sel[1:0 are arranged] equal the stack that 01 expression has 32 clauses and subclauses, size_sel[1:0] equal the stack that 10 expressions have 48 clauses and subclauses, size_sel[1:0] equal the stack that 11 expressions have 64 clauses and subclauses.For instance, as size_sel[1:0] when equaling 10, if the value in the stack pointer register 16 surpassed for 47 (the expression pop down surpasses 48 clauses and subclauses), upwards spill over is put a high position, expression is upwards overflowed.Equally, the address as the access system hardware stack is carried out behind the different modulo operations in the data based different setting in the stack pointer register 16.Such as size_sel[1:0] equal at 01 o'clock, it is 32 modulo operation that the numerical value in the stack pointer register 16 is carried out modulus, then the address of result as the access system hardware stack.
Claims (5)
1. digital signal processor that has the reconfigurable system hardware stack, mainly comprise: address generator unit (2), instruction decoding unit (3), digital data processing unit (4), digital data memory (6), it is characterized in that also comprising: procedure control unit (1), hardware stack pointer register (16), instruction decoding unit (3) is connected to procedure control unit (1), procedure control unit (1) is connected to the address generating unit, instruction decoding unit (3) and digital data processing unit (4), the two-way digital data memory (6) that is connected to of digital data processing unit (4), address generator unit (2) is connected to digital data memory (6) by address bus, digital data memory (6) is connected to address generator unit (2) by data bus simultaneously, instruction decoding unit (3) and digital data processing unit (4), digital data bus links to each other with digital data memory (6), digital data memory (6) storage provides will be by the numerical data of described digital signal processor operation, procedure control unit (1) generates the operation command signal of other unit of the described digital signal processor of control according to described instruction, comprise the system hardware stack in the procedure control unit (1) and to the operation control register of system hardware stack, the operation note of system hardware stack comprises system hardware stack pointer register (16), and system hardware stack pointer register (16) is connected on the system hardware stack by address bus.
2. the digital signal processor that has the reconfigurable system hardware stack according to claim 1, it is characterized in that, instruction decoding unit (3) is the instruction that described digital signal processor extracts configuration program, and instruction translation become control signal and data-signal, digital data processing unit (4) carries out digital operation or logical operation according to control signal to the data of input.
3. the digital signal processor that has the reconfigurable system hardware stack according to claim 1 is characterized in that, address generator unit (2) generate the address of access digital data storer (6).
4. the digital signal processor that has the reconfigurable system hardware stack according to claim 1 is characterized in that, 64 clauses and subclauses of the physically maximum placement of system hardware stack, and each clauses and subclauses is 24.
5. the digital signal processor that has the reconfigurable system hardware stack according to claim 1, it is characterized in that, one two port is arranged on the chip periphery pin, by this two bit port is carried out 00,01,10,11 these four kinds of different settings, this port signal line is connected on the middle selector switch (15) of procedure control unit (1), stack pointer register (16) also is connected on the selector switch (15), upwards spill over is drawn from selector switch (15), and the address bus of drawing from selector switch (15) is connected on the system hardware stack.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 03115375 CN1255740C (en) | 2003-02-13 | 2003-02-13 | Digital signal processor with a restructurable system hardware stack |
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| CN 03115375 CN1255740C (en) | 2003-02-13 | 2003-02-13 | Digital signal processor with a restructurable system hardware stack |
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| CN1521644A true CN1521644A (en) | 2004-08-18 |
| CN1255740C CN1255740C (en) | 2006-05-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104793920A (en) * | 2014-01-17 | 2015-07-22 | 想象力科技有限公司 | Stack pointer value prediction |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104793920A (en) * | 2014-01-17 | 2015-07-22 | 想象力科技有限公司 | Stack pointer value prediction |
| CN104793920B (en) * | 2014-01-17 | 2019-03-08 | 美普思技术有限责任公司 | Method and apparatus for stack pointer value prediction |
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| CN1255740C (en) | 2006-05-10 |
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