CN1521593B

CN1521593B - Programmed frequency divider

Info

Publication number: CN1521593B
Application number: CN 03103433
Authority: CN
Inventors: 王荣志; 胡肇佑
Original assignee: Elan Microelectronics Corp
Current assignee: Elan Microelectronics Corp
Priority date: 2003-01-30
Filing date: 2003-01-30
Publication date: 2010-05-26
Anticipated expiration: 2023-01-30
Also published as: CN1521593A

Abstract

The invention provides a programmed frequency divider, comprising an n-bit adder and an n-bit D-type flip-flop, which is used for converting an input clock into a target clock, and the frequency of the input clock is 2 of the frequency of the target clock^mMultiple, where m is a positive integer greater than 0. The adder generates a first output signal by adding a feedback signal and an adjustment parameter, wherein the adjustment parameter comprises n bits, n is a positive integer greater than 0, and m is less than or equal to n, and the adjustment parameter can be controlled by a program instruction. The D-type flip-flop is connected with the adder to form a loop circuit, and is used for receiving the first output signal and the input clock and generating a second output signal. Wherein the second output signal is divided into a feedback signal and a target signal, the target signal being composed of a Most Significant Bit (MSB) of the second output signal, and the feedback signal being composed of all bits of the second output signal; the D-type trigger feeds the feedback signal back to the adder to be added with the adjusting parameter, and outputs the target clock according to the target signal.

Description

The sequencing frequency divider

Technical field

The present invention is about a kind of frequency divider, especially about a kind of sequencing frequency divider that utilizes computer program instructions control.

Background technology

In synchronous digital display circuit, clock signal is played the part of a very important role, and is except the usefulness of decision systems, more closely bound up with the power consumption of circuit.Especially Xian Dai running gear is luxuriant is agitation, many central processing unit (CPU)s (CPU), digital signal processor (DSP) and microcontroller are in order to reduce the consumption of power as best one can, to reach purpose of power saving, therefore when processor is idle, system is switched to lower frequency of operation.

General traditional frequency divider, please refer to Figure 1A, normally form by the D flip-flop (DFlip Flop) and an incrementer (incrementer) of a n position, resulting different frequency signals behind its frequency division, import respectively at several D flip-flops, therefore also need utilize a multiplexer to utilize a control signal FREQ_SEL to come the select target frequency signal, export this target frequency signal again.During practical layout (layout), because the position difference of each D flip-flop, so its exit point is to tending to produce different delays between the multiplexer.Simultaneously, the control signal FREQ_SEL that selects frequency also might arrive simultaneously because of control signal is non-, and cause the temporary non-target frequency that switches to when switching frequency, though still switch to target frequency at last, can cause very big influence in some cases.For instance, please refer to the clock timing diagram of Figure 1B, control signal FREQ_SEL is when about 215ns, switch to 3 " 011 " by 3 " 000 ", because the delay of each and inequality in the FREQ_SEL signal, so FREQ_SEL becomes " 010 " by " 000 " earlier, after the about 0.2ns of process, just stable become " 011 " therefore makes CLKOUT produce pulse (pulse) signal of a minimal width, just vibration (glitch) signal; The action that therefore system might make the mistake.

Another kind of traditional frequency divider, please refer to counter (binary upcounter) on the scale-of-two of Fig. 2 A, though can specify the periodicity of counting arbitrarily at input end COUNT_TO, and utilize its count to flag (blip counting) (TERCNT), when counting down to the COUNT value of appointment, produce pulse (pulse) signal in a CLKIN cycle.Shown in Fig. 2 B, if when this pulse signal is used for clock (CLOCK), may produce duty factor (duty cycle) is not the shortcoming of 50%-50%, and may tremble the phenomenon of (glitch) yet.

Summary of the invention

Fundamental purpose of the present invention provides a kind of frequency divider of sequencing, can utilize the control (directly utilizing programmed instruction to instruct switching frequency) of programmed instruction, to reach the purpose of frequency division, further, sequencing frequency divider provided by the present invention, the sub-frequency clock signal of the different multiples of its output connects by the output of same output point, need not be by the selection signal of multiplexer eliminating the problem of clock jitter, and then reach stable electricity-saving function.

Another object of the present invention provides a kind of sequencing frequency divider, and its frequency-dividing clock that obtains can not produce vibration (glitch) phenomenon.

A further object of the present invention provides a kind of frequency divider of sequencing, to obtain the frequency-dividing clock of 50%-50% duty factor (duty cycle).

A kind of sequencing frequency divider comprises a n position totalizer and a n position D flip-flop, and in order to an input clock is converted to a target clock, and the frequency of this input clock is 2 of a target clock frequency ^mDoubly, wherein m is the positive integer greater than 0.This totalizer regulates parameter according to one and a feedback signal addition produces one first output signal, and wherein this adjusting parameter comprises n position, and n is the positive integer greater than 0, and m≤n, and can utilize programmed instruction to control this adjusting parameter.This D flip-flop and this totalizer are connected to form loop checking installation, in order to receiving this first output signal and this input clock, and produce one second output signal.Wherein this second output signal is distinguished into feedback signal and echo signal, and this echo signal is made of the most significant digit (MSB) of this second output signal, and this feedback signal is made of all positions of this second output signal.This D flip-flop also this feedback signal is presented back this totalizer and this adjusting parameter is carried out additive operation, and exports this target clock according to its echo signal.

" sequencing frequency dividing circuit " proposed by the invention can utilize the control input to regulate the mode of parameter, obtains removing 2 ^mThe clock of frequency (m is the positive integer since 0), and can not produce the problem of clock jitter (glitch), to provide processor lower work clock.

Description of drawings

Figure 1A and Fig. 2 A are traditional frequency divider;

Figure 1B and Fig. 2 B are respectively the clock timing diagram of the frequency divider of Figure 1A and Fig. 2 A;

Fig. 3 A is the frequency divider figure of one embodiment of the invention;

Fig. 3 B～Fig. 3 D is that the various multiple frequency-dividing clocks of exporting according to the frequency divider of Fig. 3 A are graphic;

Fig. 4 A is the frequency divider figure of another embodiment of the present invention; And

Fig. 4 B～Fig. 4 F is the various multiple frequency-dividing clock sequential charts of exporting according to the frequency divider of Fig. 4 A.

Explanation of tables

Table one is the relation that INCR of the present invention regulates parameter and frequency f; And

Table two is that seven INCR of another embodiment of the present invention regulate parameter and frequency division multiple relation.

The primary clustering symbol description

Rejection gate (NOR)-----------41

Totalizer----------------31,42

D flip-flop-----------32,43,45,47

Clock-----------------300,400,400a

Regulate parameter------------301,401,403,409

Feedback signal------------302,405

Logic output signal-------402

First output signal-------303,406

Second output signal-------304,407

The 4th output signal-------410

The 5th output signal------412 first signal--------------404

Secondary signal------------408 the 3rd signal-------------411

The 4th signal------------413

Sheffer stroke gate (NAND)----44 with the door (AND)---------46

First input end--------4,401 second input end---------4402

The 3rd input end--------4601 four-input terminal---------4602

Not gate------------4001 XOR gate (XOR)----48

Echo signal-----------399,499

Embodiment

Relevant the present invention is the above-mentioned purpose of realization, the technology that is adopted, means and specific structural features, and now for a preferable feasible embodiment, and utilization illustrates and it is clear further to disclose, and is detailed in following.

The invention provides a kind of sequencing frequency divider, in order to an input clock (can utilize an oscillator to produce this input clock) is converted to a target clock, the frequency of this input clock is 2 of a target clock frequency ^mDoubly, wherein m is the positive integer greater than 0, please refer to Fig. 3 A, and this device comprises: a n position totalizer 31 and a n position D flip-flop 32.One regulates parameter 301 and a feedback signal 302 input summers 31, this totalizer 31 will be regulated parameter 301 and be produced one first output signal 303 mutually with feedback signal 302, and export this signal 303, wherein this adjusting parameter comprises n position, n is the positive integer greater than 0, and (for example, when the adjusting parameter was the n position, maximum frequency division multiple was 2 to m≤n ⁿ), and can utilize program to control this adjusting parameter 301 by the mode of instruction.D flip-flop 32 is connected to form loop checking installation with this totalizer 31, in order to receiving this first output signal 303 and input clock 300, and produces one second output signal 304; Wherein this second output signal 304 is further divided into feedback signal 302 and echo signal 399, and echo signal 399 is by most significant digit (MSB) formation of this second output signal 304, and this feedback signal 302 by this second output signal 304 all the position constitute, and this feedback signal 302 is presented back this totalizer 31 along loop checking installation carry out additive operation with this adjusting parameter 301, again according to these echo signal 399 export target clocks.In preferred embodiment, D flip-flop provided by the present invention is one just along one of them of a triggered flip-flop or a negative edge triggered flip-flop; Furthermore, this D flip-flop or this totalizer are made up of at least one and door (AND), at least one or door (OR) and at least one not gate (NOT).It should be noted that in this embodiment D flip-flop is taken as data buffer storage unit and uses.When being triggered by clock CLKIN, the data of its output are updated according to data buffer unit provided by the invention.Other can carry out the data buffer storage unit of identical function, for example by trigger, and latch circuit, the circuit that buffer constitutes similarly goes for the present invention.

Therefore, the invention provides a kind of frequency divider of sequencing, can utilize the control (directly utilizing programmed instruction to come switching frequency) of programmed instruction, to reach the purpose of frequency division, further, sequencing frequency divider provided by the present invention, the sub-frequency clock signal of the different multiples of its output connect by same output point output, need not be with the selection signal of multiplexer eliminating the problem of clock jitter, and then reach stable electricity-saving function.

For instance, please refer to Fig. 3 A and Fig. 3 B, when INCR regulates parameter 301 (n position, just from the 0th～n-1 position) most significant digit (MSB) be " 1 ", and CLKCNT[n-1 at the beginning suppose when be " 0 " in remaining position] echo signal 399 is " 0 ", after the addition of passing through ADD1 totalizer 31 is calculated, because INCR regulates parameter 301 and removes all remaining positions of most significant digit and be all " 0 ", so the CLKCNT_IN[n-1 of ADD1 totalizer 31 outputs] first output signal 303 is " 1 "; This is first cycle (cycle 1).Again through the next cycle clock just after trigger, CLKCNT[n-1] echo signal 399 is updated to 1 (this is second period; Cycle 2), its CLKCNT[n-1:0] feedback signal 302 regulates parameter 301 through after 31 additions of ADD1 totalizers, because the relation of carry obtains CLKCNT_IN[n-1 with INCR] first output signal 303 is " 0 ".When the 3rd cycle (cycle 3), CLKCNT[n-1] echo signal 399 is updated to " 0 ", gets back to original state again.When therefore if the input of INCR adjusting parameter 301 is constant, CLKCNT[n-1] echo signal 399 will do " 0 " in each in cycle and arrive " 1 " or " 1 " and arrive variation between " 0 ", therefore can be from CLKCNT[n-1] echo signal 399 can obtain an output clock that removes 2 overtones bands, and the output of its target clock is graphic shown in Fig. 3 B.

In addition, please refer to the clock timing diagram of Fig. 3 A and Fig. 3 C, regulate parameter 301 (n position when changing INCR, just from the 0th～n-1 position) input, making INCR[n-2] this parameter 301 time high-order be " 1 ", and all the other positions are when being all " 0 ", operation via frequency dividing circuit of the present invention, because INCR regulates the position that " 1 " of parameter 301 is positioned at n-2 position (an inferior high position), therefore must and CLKCNT feedback signal 302 secondary that adds up just can make CLKCNT[n-1] " 0 " take place once and arrive " 1 " or " 1 " and arrive variation between " 0 " in echo signal 399, we can be by CLKCNT[n-1 at this moment] echo signal 399 obtains one except that 2 ²The clock of overtones band is shown in Fig. 3 C.

Further, please refer to Fig. 3 A and Fig. 3 D if change INCR[n-3] regulate n-3 (inferior two high positions of parameter 301; Come the 3rd position from the most significant digit number) be " 1 ", and all the other positions are when being all " 0 ", because " 1 " that INCR regulates in the parameter 301 is positioned at n-3 bit position, therefore must and CLKCNT feedback signal 302 add up just can make CLKCNT[n-1 four times] " 0 " take place once and arrive " 1 " or " 1 " and arrive variation between " 0 " in echo signal 399, at this moment can be by CLKCNT[n-1] output of echo signal 399 obtains one except that 2 ³The clock of overtones band is shown in Fig. 3 D.

Therefore, through suitably controlling the input value that INCR regulates parameter 301, can make INCR[n-m] place value of the n-m position of this parameter 301 is " 1 " (m=1 wherein, 2,3 ... .n), and all the other positions of INCR parameter 301 are all " 0 ", can be by CLKCNT[n-1] echo signal 399 obtains removing the clock of 2m overtones band.The relation of its adjusting parameter I NCR and frequency f as shown in Table 1.

Please refer to another preferred embodiment of Fig. 4 A, the invention provides a kind of sequencing frequency divider, in order to an input clock (can utilize an oscillator to produce this input clock) is converted to a target clock, the frequency of this input clock is 2 of a target clock frequency ^mDoubly, wherein m is the positive integer since 0, to reach the purpose of frequency division.The inventive system comprises: a rejection gate (NOR) 41, a n position totalizer 42, a n position first D flip-flop (D Flip-Flop) 43, one Sheffer stroke gate (NAND) 44, one second D flip-flop 45, one and door (AND) 46, one the 3rd trigger 47 and an XOR gate 48.The input end of rejection gate (NOR) 41 is regulated parameter by one and is removed that remaining all of most significant digit 401 constitute, and after the logical operation of rejection gate 41, export a logic output signal 402, wherein this adjusting parameter comprises n position, n is the positive integer greater than 0, and m≤n (for example, when the adjusting parameter was the n position, maximum frequency division multiple was 2 ⁿ), and this adjusting parameter can utilize programmed instruction to control.Totalizer 42 produces one first output signal 406 according to one first signal 404 and a feedback signal 405 additions, this first signal 404 is removed by the logic output signal 402 of this rejection gate (NOR) 41 and this adjusting parameter that remaining all of most significant digit 403 constitute, and this logic output signal 402 most significant digit (MSB) that is this first signal 404.First D flip-flop 43 is connected to form loop checking installation with this totalizer 42, in order to receiving first output signal 406 that input clock 400 and this totalizer 42 are exported, and produces one second output signal 407; This second output signal 407 further is distinguished into a secondary signal 408 and feedback signal 405, this secondary signal 408 is made of the most significant digit (MSB) of this second output signal 407, and this feedback signal 405 is made of all positions of this second output signal 407, and this feedback signal 405 is fed back this totalizer 42 and this first signal 404 carries out additive operation along loop checking installation.Sheffer stroke gate (NAND) 44 is exported one the 4th output signal 410 according to the signal of a first input end 4401 and one second input end 4402, wherein this first input end 4401 is in order to receive this logic output signal 402, and this second input end 4402 is an inverting input, in order to the most significant digit (MSB) 409 that receives this adjusting parameter, the most significant digit 409 that just will regulate parameter is earlier done after the anti-phase computing input nand gate 44 again.Second D flip-flop 45 is in order to receiving the 4th output signal 410 and input clock 400, and produces one the 3rd signal 411.Export one the 5th output signal 412 with door (AND) 46 according to the signal of one the 3rd input end 4601 and a four-input terminal 4602, the 3rd input end 4601 is in order to receive this secondary signal 408, and four-input terminal 4602 is an inverting input, in order to receive the 3rd signal 411, just earlier the 3rd signal 411 is done after the anti-phase computing input again should and door 46.The 3rd trigger 47 is in order to receive the 5th output signal 412 and anti-phase input clock 400a, and produce one the 4th signal 413, wherein this anti-phase input clock 400a imports this trigger 47 after utilizing a not gate (NOT) 4001 that input clock 400 is done anti-phase computing.XOR gate 48 is exported an echo signal 499 according to this secondary signal 408 and the 4th signal 413, and according to these echo signal 499 export target clocks.In preferred embodiment, D flip-flop provided by the present invention is one just along one of them of a triggered flip-flop or a negative edge triggered flip-flop; Furthermore, this D flip-flop or this totalizer are made up of at least one and door (AND), at least one or door (OR) and at least one not gate (NOT).In addition, D flip-flop of the present invention can utilize the kenel of a data buffer storage unit to handle.Therefore, the invention provides a kind of frequency divider of sequencing, can utilize the control (directly utilizing programmed instruction to come switching frequency) of programmed instruction, to reach the purpose of frequency division, further, sequencing frequency divider provided by the present invention, the sub-frequency clock signal of the different multiples of its output connect by same output point output, need not be with the selection signal of multiplexer eliminating the problem of clock jitter, and then reach stable electricity-saving function.

For instance, one seven adjusting parameter can remove 2 ⁰～2 ⁷Frequency doubly.For example, desire removes 2 ⁰Frequency doubly (that is the output clock frequency equals input clock), please refer to Fig. 4 A and Fig. 4 B, input INCR adjusting parameter is seven " 0000000 ", when first cycle (cycle 1), by INCR[5:0] regulate parameter and remove all remaining positions 401 of most significant digit and after 41 computings of NOR1 rejection gate, produce INCR_N logic output signal 402 and be " 1 ", if CLKCNT[6 at the beginning] secondary signal 408 is " 0 ", this totalizer 42 output CLKCNT_IN[6 then] first output signal 406 be " 1 ", can not produce carry at this moment.And next CLKIN input clock 400 just when triggering, CLKCNT[6] secondary signal 408 is updated to " 1 ", enter second period (cycle 2) again, this moment CLKCNT[6] secondary signal 408 is " 1 ", and after feedback signal 405 and 404 additions of first signal, CLKCNT_IN[6] first output signal 406 will produce carry and become " 0 ".And next CLKIN input clock 400 just when triggering, CLKCNT[6] secondary signal 408 is updated to " 0 ", therefore get back to original state again, the rest may be inferred, if regulate parameter constant, CLKCNT[6] switching of " 0 " and " 1 " will take place in each cycle (cycle) in secondary signal 408, the clock that to be equivalent to a frequency be f/2.If INCR[6:0] all positions of regulating parameter remain " 0000000 ", then INCR_N logic output signal 402 is " 1 ", INCR[6] most significant digit 409 of regulating parameter is " 0 ", after the computing through NAND1 Sheffer stroke gate 44, EN_DIVIDE_IN the 4th output signal 410 will be " 0 ", therefore DFF3 second trigger 45 is after the just edge triggering of input clock 400, its output EN_DIVIDE the 3rd signal 411 will remain on " 0 " always, and this moment, ORGCLK_IN the 5th output signal 412 just was equivalent to CLKCNT[6] secondary signal 408 (because of another input end 4602 with door 46 is " 1 ").DFF2 the 3rd trigger 47 utilizes CLKIN input clock 400 to make negative edge and triggers, and therefore for two input ends of XOR1 XOR gate 48, ORGCLK the 4th signal 413 is for postponing the CLKCNT[6 of half period CLKIN input clock 400] secondary signal 408.Do after the XOR through XOR1 XOR gate 48, can obtain the target clock that frequency is f by export target signal 499.The variation of its clock signal can be with reference to figure 4B.Since two input ends of XOR1 XOR gate 48, its transformation period phase difference of half cycle (CLKIN cycle), so the signal of its output terminal can not produce the situation of vibration (glitch); More can obtain the frequency-dividing clock of 50%-50% duty factor (duty cucle).

If desire removes 2 ¹Frequency doubly, please refer to Fig. 4 A and Fig. 4 C, removing under the pattern of 2 overtones bands, input INCR adjusting parameter is seven " 1000000 ", when first cycle (cycle 1), INCR[5:0] regulate parameter and remove remaining all of most significant digit 401 after the computing of NOR1 rejection gate 41, producing INCR_N logic output signal 402 is " 1 ", if CLKCNT[6 at the beginning] secondary signal 408 is " 0 ", then can get CLKCNT_IN[6 after feedback signal 405 and 404 additions of first signal] first output signal 406 is " 1 ", can not produce carry this moment.And next CLKIN input clock 400 just when triggering, CLKCNT[6] secondary signal 408 is updated to " 1 ", then enter second period (cycle 2), this moment CLKCNT[6] secondary signal 408 is " 1 ", after the computing of totalizer 42, CLKCNT_IN[6] first output signal 406 will produce carry and become " 0 ".Next CLKIN input clock 400 just when triggering, CLKCNT[6] secondary signal 408 is updated to " 0 ", therefore gets back to original state again, this moment is identical with a last example (that is the output clock frequency equals input clock).The rest may be inferred, if regulate parameter constant, CLKCNT[6] switching of " 0 " and " 1 " will take place in each cycle (cycle) in secondary signal 408, be equivalent to produce a frequency clock that is f/2.If INCR[6:0] regulate parameter and remain " 1000000 " always, then INCR_N logic output signal 402 is " 1 ", INCR[6] most significant digit 409 of regulating parameter is " 1 ", after the computing through NAND1 Sheffer stroke gate 44, EN_DIVIDE_IN the 4th output signal 410 will be " 1 " always, therefore after the just edge triggering of DFF3 second trigger 45 via input clock 400, its output EN_DIVIDE the 3rd signal 411 will remain on " 1 " always, after the inverting input 4602 through being input to AND1 and door 46, will make ORGCLK_IN the 5th output signal 412 remain on " 0 " always.At this moment, output ORGCLK the 4th signal 413 of DFF2 the 3rd trigger will remain on " 0 " always, therefore through after the logical operation of XOR gate 48, CLK echo signal 499 equals to allow CLKCNT[6] secondary signal 408 is directly by XOR1 XOR gate 48, therefore can obtain the target clock that frequency is f/2 by CLK echo signal 499.Please refer to the clock timing diagram of Fig. 4 C.

Further, if desire removes 2 ²～2 ⁷Frequency doubly please refer to Fig. 4 A, Fig. 4 D, Fig. 4 E and Fig. 4 F.Under other pattern, seven INCR regulate the relation of parameter and frequency division multiple can reference table two, INCR_N logic output signal 402 is " 0 " at this moment, EN_DIVIDE_IN the 4th output signal 410 is " 1 ", make that EN_DIVIDE the 3rd signal 411 also is updated to " 1 " after the second period, this moment is CLKCNT[6 no matter] how secondary signal 408 to change, ORGCLK_IN the 5th output signal 412 will be " 0 ", again after half period (cycle), ORGCLK the 4th signal 413 also will remain " 0 " always, so CLK echo signal 499 is incited somebody to action fully by CLKCNT[6] secondary signal 408 decisions.The loop checking installation that constitutes of DFF1 first trigger 43 and ADD1 totalizer 42 again is when removing 2 ²During overtones band, can get INCR[6:0 by table two] regulate parameter and be " 0100000 ", ADD1 totalizer 42 its input end (INCR_N, INCR[5:0]) first signal 404 equals INCR[6:0] regulate all positions of parameter, this moment circuit the every cycle (cycle) that is operating as through a CLKIN input clock 400, CLKCNT feedback signal 405 INCR[6:0 that just adds up a time] regulate all value of parameter, therefore CLKCNT[6:5] the highest and time high-order value of second output signal 407 can be according to two " 00 ", " 01 ", " 10 ", the sequential loop of " 11 " is done variation, this moment CLKCNT[6] cycle (CLKIN cycle) of secondary signal 408 per two input clocks 400 can be by " 0 " to " 1 ", or once by " 1 " to " 0 " variation, so cycle (CLKIN cycle) of per four input clocks 400, end in XOR gate 48 produces a complete clock signal, and its frequency is f/4.Inference above comprehensive again, this moment, 499 outputs of CLK echo signal were fully by CLKCNT[6] secondary signal 408 decisions, therefore can obtain the target clock of f/4 by CLK echo signal 499, shown in Fig. 4 D.In like manner can get, at INCR[6:0] to regulate parameter be " 0010000 ", CLKCNT[6] secondary signal 408 per four input clock cycles (CLKIN cycle) can be by " 0 " to " 1 ", or once by " 1 " to " 0 " variation, so per eight input clock cycles (CLKINcycle), end in XOR gate 48 will produce a complete clock signal, and its frequency is f/8, shown in Fig. 4 E.Remaining pattern also can be derived out by same mode, and the result is shown in Fig. 4 F.

Therefore the present invention can and produce according to the continuous extension of the demand of system and remove 2 ⁿSignal doubly, and the signal of different frequency all can be by most significant digit (MSB) output of trigger (Flip-Flop), so during switching frequency, the clock signal of output can not given birth to vibration (glitch).This circuit of the present invention can be finished by the digital circuit of logic lock stratum fully, also is highly suitable for doing with HDL the High-LevelDesign Flow of design.In addition,, therefore be fit to very much be applied in the processor, directly utilize program indicator code to switch the operating frequency of digital display circuit because the present invention can utilize programmed instruction to change the characteristic of parameter.So in the design of digital display circuit, what its available scope will be very is wide.In sum, the present invention's " sequencing frequency divider " can be finished and then be reached the function of frequency division fully by the digital circuit of logic lock stratum, breaks through the known technology stereotype, is not the simple application that easy full of beard reaches.

Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can change and revise, thus protection scope of the present invention from proposed claim institute restricted portion be as the criterion.

Table one INCR regulates the relation of parameter and frequency f

Table two INCR regulates parameter and frequency division multiple relation

Regulate parameter (INCR)	The frequency division multiple
Regulate parameter (INCR)	The frequency division multiple	0000000	1
1000000	2	0000000	1
1000000	2	0100000	4
0010000	8	0100000	4
0010000	8	0001000	16
0000100	32	0001000	16
0000100	32	0000010	64
0000001	128	0000010	64

Claims

1. A programmable frequency division device, in order to convert an input clock into a target clock, the frequency of the input clock is 2 ^m times of the target clock frequency, wherein m is a positive integer greater than 0, and its features include:

An n-bit adder generates a first output signal by adding an adjustment parameter to a feedback signal, wherein the adjustment parameter includes n bits, n is a positive integer greater than 0, and m≤n, and the program instruction can be used controlling the tuning parameter; and

An n-bit D-type flip-flop is connected with the adder to form a circular loop for receiving the first output signal and the input clock, and generating a second output signal;

Wherein the second output signal is further divided into the feedback signal and a target signal, the target signal is composed of the most significant bit MSB of the second output signal, the feedback signal is composed of all bits of the second output signal, and the feedback The signal is fed back to the adder for addition operation with the adjustment parameter, and then the target clock is output according to the target signal.

2 . The frequency division device according to claim 1 , wherein the D-type flip-flop is one of a positive-edge-triggered flip-flop or a negative-edge-triggered flip-flop.

3. The frequency division device according to claim 1, wherein the D-type flip-flop is composed of at least one AND gate, at least one OR gate, and at least one NOT gate.

4. The frequency division device according to claim 1, wherein the adder is composed of at least one AND gate, at least one OR gate, and at least one NOT gate.

5. The frequency division device according to claim 1, wherein the input clock is generated by an oscillator.

6. A programmable frequency division device, in order to convert an input clock into a target clock, the frequency of the input clock is 2 ^m times of the target clock frequency, wherein m is a positive integer greater than 0, and its features include:

A NOR gate NOR, whose input terminal is composed of all the remaining bits of an adjustment parameter except the highest bit, and outputs a logic output signal, wherein the adjustment parameter includes n bits, n is a positive integer greater than 0, and m ≤n, and the adjustment parameter can be controlled by program instructions;

An n-bit adder generates a first output signal based on the addition of a first signal and a feedback signal, and the first signal is obtained by removing the highest bit from the logic output signal of the NOR gate and the adjustment parameter formed, and the logic output signal is the most significant bit MSB of the first signal;

An n-bit first D-type flip-flop is connected with the adder to form a circular loop to receive the first output signal and the input clock, and generate a second output signal, wherein the second output signal is further divided into a first Two signals and the feedback signal, the second signal is composed of the most significant bit MSB of the second output signal, and the feedback signal is composed of all bits of the second output signal, and the feedback signal is fed back to the adder and the performing an addition operation on the first signal;

A NAND gate NAND outputs a fourth output signal according to the signals of a first input terminal and a second input terminal, wherein the first input terminal is used to receive the logic output signal, and the second input terminal is an inverting input Terminal, used to receive the highest MSB of the adjustment parameter;

a second D-type flip-flop, used to receive the fourth output signal and the input clock, and generate a third signal;

An AND gate AND outputs a fifth output signal according to the signals of a third input terminal and a fourth input terminal, the third input terminal is used to receive the second signal, and the fourth input terminal is an inverting input terminal for to receive the third signal;

A third flip-flop is used to receive the fifth output signal and an inverted input clock, and generate a fourth signal, wherein the inverted input clock uses a NOT gate to make an inverted output of the input clock; and

An exclusive OR gate outputs a target signal according to the second signal and the fourth signal, and outputs the target clock according to the target signal.

7. The frequency division device according to claim 6, wherein the D-type flip-flops are a positive-edge triggered flip-flop or a negative-edge triggered flip-flop.

8. The frequency division device according to claim 6, wherein the D-type flip-flops are composed of at least one AND gate, at least one OR gate, and at least one NOT gate.

9. The frequency dividing device according to claim 6, wherein the adder is composed of at least one AND gate, at least one OR gate, and at least one NOT gate.

10. The frequency division device according to claim 6, wherein the input clock is generated by an oscillator.

11. A programmable frequency dividing device, in order to convert an input clock into a target clock, the frequency of the input clock is 2 ^m times of the target clock frequency, wherein m is a positive integer greater than 0, and its features include:

An n-bit adder n-bit ADD generates a first output signal by adding an adjustment parameter to a feedback signal, wherein the adjustment parameter includes n bits, n is a positive integer greater than 0, and m≤n, and The tuning parameter may be controlled by program instructions; and

An n-bit data buffer unit, connected to the adder to form a loop, is used to receive the first output signal and the input clock, and generate a second output signal;

12 . The frequency dividing device according to claim 11 , wherein the data buffer unit is one of a positive edge trigger type flip-flop or a negative edge trigger type flip-flop. 13 .

13. The frequency division device according to claim 11, wherein the data buffer unit is composed of at least one AND gate, at least one OR gate, and at least one NOT gate.

14. The frequency division device according to claim 11, wherein the adder is composed of at least one AND gate, at least one OR gate, and at least one NOT gate.

15. The frequency division device according to claim 11, wherein the input clock is generated by an oscillator.

16. A programmable frequency division device for converting an input clock into a target clock, the frequency of the input clock is 2 ^m times the frequency of the target clock, wherein m is an integer ≥ 0 , and its features include:

A NOR gate NOR, the input terminal of which is composed of all the remaining bits of an adjustment parameter except the highest bit, and outputs a logic output signal, wherein the adjustment parameter includes n bits, n is a positive integer greater than 0, and m ≤n, and the adjustment parameter can be controlled by program instructions;

An n-bit first data buffer unit is connected with the adder to form a circular loop for receiving the first output signal and the input clock, and generating a second output signal, wherein the second output signal is further divided into a second signal and the feedback signal, the second signal is composed of the most significant bit MSB of the second output signal, and the feedback signal is composed of all bits of the second output signal, and the feedback signal is fed back to the adder and the first A signal is added;

a second data buffer unit, configured to receive the fourth output signal and the input clock, and generate a third signal;

17. The frequency division device according to claim 16, wherein the data buffer units are a positive-edge-triggered flip-flop or a negative-edge-triggered flip-flop.

18. The frequency division device according to claim 16, wherein the data buffer units are composed of at least one AND gate, at least one OR gate, and at least one NOT gate.

19. The frequency division device according to claim 16, wherein the adder is composed of at least one AND gate, at least one OR gate, and at least one NOT gate.

20. The frequency division device according to claim 16, wherein the input clock is generated by an oscillator.