CN1519729A - Storage device having debugging mode, electronic equipment possessing the storage device, and debugging method - Google Patents
Storage device having debugging mode, electronic equipment possessing the storage device, and debugging method Download PDFInfo
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- CN1519729A CN1519729A CNA031008402A CN03100840A CN1519729A CN 1519729 A CN1519729 A CN 1519729A CN A031008402 A CNA031008402 A CN A031008402A CN 03100840 A CN03100840 A CN 03100840A CN 1519729 A CN1519729 A CN 1519729A
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Abstract
The storage device includes: a storage unit utilized to access a corresponding data based on a address signal and a instruction signal; a first to third buffers coupled to the said storage device; a controller in debugging mode utilized to enable the said first to third buffers based on a external signal as well as detect whether the said address signal, instruction signal, and corresponding data are changed or not; if yes, making the first to third buffers store the said address signal, instruction signal, and corresponding data.
Description
Technical field
The invention relates to a kind of memory storage, particularly about a kind of memory storage with debug mode.
Background technology
In other electronic installations such as mobile phone, individual digital secretary PDA, regular meeting uses storage to deposit program or data as 1T-SRAM or LPDRAM.Yet in the program development process, mobile phone or PDA usually can cause and work as machine because program error or hardware are unstable.Be to test traditionally to producing wrong program or data by logic analyser (logicanalyzier), and generation oscillogram, in order to analyze and debug, but logic analyser cost an arm and a leg and efficient not good, to make cost of development increase, and can't shorten the time of product development.
Therefore if can provide a storage with debug mode to be arranged at helps debug in the electronic installation, and the microprocessor in electronic installation performs an analysis and debug, will help Products Development.
Summary of the invention
In view of this, primary and foremost purpose of the present invention is to provide a kind of memory storage with debug mode to come auxiliary electronic device to analyze and debug, to reduce cost of development and to promote product development speed.
In addition, another object of the present invention is to provide a kind of debug method of memory storage.
The invention provides a kind of memory storage, comprise a storage unit with debug mode, in order to according to an address signal and a command signal, access one corresponding data; The one first to the 3rd buffer couples said memory cells; An and debug mode controller, in order to according to an external signal, above-mentioned first to the 3rd buffer of activation, and detect above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data and whether change, and when above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data change, and cause above-mentioned first to the 3rd buffer to store above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data.
The present invention also provides a kind of debug method of electronic installation, comprise a memory storage with debug mode is provided that be arranged in the above-mentioned electronic installation, wherein above-mentioned memory storage comprises a storage unit, in order to according to an address signal and a command signal, access one corresponding data; The one first to the 3rd buffer couples said memory cells; And a debug mode controller, store above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data in order to control above-mentioned first to the 3rd buffer.Then, detect above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data and whether change, and when above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data change, cause above-mentioned three buffers, store above-mentioned address signal, command signal respectively, and above-mentioned corresponding data.Then, read above-mentioned address signal, command signal stored in above-mentioned three buffers, and above-mentioned corresponding data.At last, carry out the debug analysis according to the above-mentioned address signal that reads, command signal and above-mentioned corresponding data.
The present invention more provides a kind of electronic installation with storage of debug mode, comprise an electronics, has plural blas, and comprise a microprocessing unit at least, in order to carrying out above-mentioned plural blas and to carry out the debug analysis, and above-mentioned microprocessing unit is exported an activation signal to enter a debug mode; And the memory storage with debug mode, be arranged in the above-mentioned electronic installation, comprise a storage unit, when above-mentioned microprocessing unit was carried out above-mentioned blas, said memory cells was in order to according to an address signal and a command signal, access one corresponding data; The one first to the 3rd buffer couples said memory cells; An and debug mode controller, in order to according to above-mentioned enable signal, above-mentioned first to the 3rd buffer of activation, and detect above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data and whether change, and when above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data change, and cause above-mentioned first to the 3rd buffer to store above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data; Wherein above-mentioned microprocessing unit is according to above-mentioned first to the 3rd buffer stored above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data, carries out the debug analysis.
Description of drawings
Fig. 1 is the synoptic diagram of the embodiment of the invention;
Fig. 2 is another synoptic diagram of the embodiment of the invention;
Fig. 3 is the process flow diagram of debug method of the present invention.
The figure number explanation:
10: memory storage with debug mode;
12: storage unit; 14: Address Register;
16: Instruction Register; 18: data buffer;
20: the debug mode controller; 150: electronics;
151: microprocessing unit.
Embodiment
As shown in fig. 1, be the electronic installation 200 with storage of debug mode of the present invention, comprise that an electronics 150 and has the storage 10 of debug mode.
Wherein, electronics 150, mobile phone, individual digital secretary PDA for instance, or the out of Memory household electrical appliances or the like, common above-mentioned electronics all 150 includes at least that a microprocessing unit 151 and other are peripheral to be equipped with, for example LCD screen, button, battery or the like (not being shown among the figure), and have plural blas.Microprocessing unit 151 is programs of carrying out a correspondence according to command signal, for instance microprocessing unit 151 can be an analog processor (Incircuit Emulation, ICE).With mobile phone, similarly be provided with a microprocessing unit and carry out relevant program, for example according to the data in the inquiry telephone directory that the user imported, or the telephone crosstalk number that the user imported dials or the like.
For the user can take a no problem product, in the development process of various electronic products, test and debug are unavoidable.Therefore, the microprocessing unit 151 in the electronics 150 of the present invention is more exported a debug enable signal to enter a debug mode.
As shown in Figure 2, the memory storage 10 with debug mode of the present invention is arranged in the electronic installation 200 among Fig. 1.Above-mentioned memory storage 10 comprises a storage unit 12, an Address Register 14, an Instruction Register 16, a data buffer 18 and a debug mode controller 20.
Wherein storage unit 12, are coupled to microprocessing unit 151, when microprocessing unit 151 is carried out some blas, and in order to according to an address signal Add and a command signal com, access one corresponding data D.In general, storage unit 12 can include a command signal decoder, in order to above-mentioned command signal is deciphered, an address signal code translator, in order to above-mentioned address signal is deciphered, and a storage array, in order to store above-mentioned corresponding data or the like.
In addition, Address Register 14, Instruction Register 16 and data buffer 18 are to couple storage unit 12.For instance, Address Register 14, Instruction Register 16, data buffer 18 are respectively to be a bit shift register, and can be made of bolt-lock or flip-flop, and each bit shift register is in order to storing at least one data, for example 32,64 or more than.
Afterwards, when the electronic installation with storage of debug mode of the present invention desires to carry out the debug analysis, can see through microprocessing unit 151 and be according to Address Register 14, Instruction Register 16, data buffer 18 stored address signal Add, command signal com and corresponding data D, carry out the debug analysis.
Fig. 3 is the process flow diagram of debug method of the present invention.The debug method of electronic installation of the present invention, step 21 at first, provide a memory storage with debug mode as shown in Figure 2, be arranged in the electronics 200, wherein electronics 200 has plural blas, and comprise a microprocessing unit 151 at least, in order to carry out above-mentioned plural blas and to carry out the debug analysis, and the single 151 yuan of output one debug enable signal Sc1 of above-mentioned little processing are to enter a debug mode, memory storage 10 comprises a storage unit 12, in order to according to an address signal and a command signal, access one corresponding data, the one first to the 3rd buffer 14,16,18, couple storage unit 12, and a debug mode controller 20, in order to control above-mentioned first to the 3rd buffer 14,16,18 store above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data.
Then, step 23, one debug enable signal Sc1 is to debug mode controller 20 in microprocessing unit 151 outputs, make memory storage 10 enter a debug mode, be activation three buffer 14-18, whether the above-mentioned address signal of debug mode controller 20 detectings, above-mentioned command signal and above-mentioned corresponding data change, and when above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data change, cause Address Register 14, Instruction Register 16, data buffer 18 to begin to store address signal Add, command signal com and corresponding data D.
Then, step 25, the microprocessing unit 151 of electronic installation 200 is to carry out at least one tested program, therefore, debug mode controller 20 can be detected above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data and begin the living change of liquid, so in the time of can causing first to the 3rd buffer 14-18 to begin to store above-mentioned tested program respectively to carry out, the command signal that is produced, address signal and corresponding data.
At last, when electronic installation 200 was desired to carry out the debug analysis of tested program, the microprocessing unit 151 of electronic installation 200 can read above-mentioned address signal, command signal stored among first to the 3rd buffer 14-18, and above-mentioned corresponding data.And, carry out the debug analysis according to the above-mentioned address signal that reads, command signal and above-mentioned corresponding data.
Therefore the electronic installation with storage of debug mode of the present invention is tested, is analyzed and removes and stagger the time, and with or else need be by traditional logic analyser, and can reduce cost of development, and shorten the time of product development.
Claims (18)
1. memory storage with debug mode comprises:
One storage unit, in order to according to an address signal and a command signal, access one corresponding data;
The one first to the 3rd buffer couples said memory cells; And
One debug mode controller, in order to according to an external signal, above-mentioned first to the 3rd buffer of activation, and detect above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data and whether change, and when above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data change, cause above-mentioned first to the 3rd buffer to store above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data.
2. the memory storage with debug mode according to claim 1, wherein said memory cells comprises at least:
One command signal decoder is in order to decipher above-mentioned command signal;
One address signal code translator is in order to decipher above-mentioned address signal; And
One storage array is in order to store above-mentioned corresponding data.
3. the memory storage with debug mode according to claim 1, wherein above-mentioned first to the 3rd buffer is respectively to be a bit shift register, each bit shift register is in order to store at least one data.
4. the memory storage with debug mode according to claim 3, wherein above-mentioned bit shift register is made of bolt-lock.
5. the memory storage with debug mode according to claim 3, wherein above-mentioned bit shift register is made of flip-flop.
6. the debug method of an electronic installation comprises:
One memory storage with debug mode is provided, is arranged in the above-mentioned electronic installation, wherein above-mentioned memory storage comprises a storage unit, in order to according to an address signal and a command signal, and access one corresponding data; The one first to the 3rd buffer couples said memory cells; And a debug mode controller, store above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data in order to control above-mentioned first to the 3rd buffer;
Whether detect above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data changes;
Change in above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data; Cause above-mentioned three buffers to store above-mentioned address signal, command signal respectively, and above-mentioned corresponding data;
Read above-mentioned address signal, command signal stored in above-mentioned three buffers, and above-mentioned corresponding data; And
Carry out the debug analysis according to the above-mentioned address signal that reads, command signal and above-mentioned corresponding data.
7. the debug method of memory storage according to claim 6, wherein above-mentioned memory storage comprises at least:
One command signal decoder is in order to decipher above-mentioned command signal;
One address signal code translator is in order to decipher above-mentioned address signal; And
One storage array is in order to store above-mentioned corresponding data.
8. the debug method of memory storage according to claim 6, wherein above-mentioned first to the 3rd buffer is respectively to be a bit shift register, each bit shift register is in order to store at least one data.
9. the debug method of memory storage according to claim 8, wherein above-mentioned bit shift register is made of bolt-lock.
10. the debug method of memory storage according to claim 8, wherein above-mentioned bit shift register is made of flip-flop.
11. the electronic installation with storage of debug mode comprises:
One electronics has plural blas, and comprises a microprocessing unit at least, and in order to carrying out above-mentioned plural blas and to carry out the debug analysis, and above-mentioned microprocessing unit is exported an activation signal to enter a debug mode; And
One has the memory storage of debug mode, is arranged in the above-mentioned electronic installation, comprising:
One storage unit, when above-mentioned microprocessing unit was carried out above-mentioned blas, said memory cells was in order to according to an address signal and a command signal, access one corresponding data;
The one first to the 3rd buffer couples said memory cells; And
One debug mode controller, in order to according to above-mentioned enable signal, above-mentioned first to the 3rd buffer of activation, and detect above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data and whether change, and when above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data change, cause above-mentioned first to the 3rd buffer to store above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data;
Wherein above-mentioned microprocessing unit is according to above-mentioned first to the 3rd buffer stored above-mentioned address signal, above-mentioned command signal and above-mentioned corresponding data, carries out the debug analysis.
12. the electronic installation with storage of debug mode according to claim 11, wherein said memory cells comprises at least:
One command signal decoder is in order to decipher above-mentioned command signal;
One address signal code translator is in order to decipher above-mentioned address signal; And
One storage array is in order to store above-mentioned corresponding data.
13. the electronic installation with storage of debug mode according to claim 11, wherein above-mentioned first to the 3rd buffer is respectively to be a bit shift register, and each bit shift register is in order to store at least one data.
14. the electronic installation with storage of debug mode according to claim 13, wherein above-mentioned bit shift register is made of bolt-lock.
15. the electronic installation with storage of debug mode according to claim 13, wherein above-mentioned bit shift register is made of flip-flop.
16. the electronic installation with storage of debug mode according to claim 11, wherein above-mentioned electronics is a portable electronic devices.
17. the electronic installation with storage of debug mode according to claim 16, wherein above-mentioned electronics are an individual digital secretary (PDA).
18. the electronic installation with storage of debug mode according to claim 16, wherein electronics is a mobile phone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031008402A CN1519729A (en) | 2003-01-22 | 2003-01-22 | Storage device having debugging mode, electronic equipment possessing the storage device, and debugging method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031008402A CN1519729A (en) | 2003-01-22 | 2003-01-22 | Storage device having debugging mode, electronic equipment possessing the storage device, and debugging method |
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| CN1519729A true CN1519729A (en) | 2004-08-11 |
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| CNA031008402A Pending CN1519729A (en) | 2003-01-22 | 2003-01-22 | Storage device having debugging mode, electronic equipment possessing the storage device, and debugging method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034135B (en) * | 2006-03-06 | 2010-08-18 | 联发科技股份有限公司 | Integrated circuit with scan-based debugging and debugging method thereof |
| CN101620558B (en) * | 2008-07-01 | 2011-08-03 | 环旭电子股份有限公司 | General debugging-assistant device |
| CN103186431B (en) * | 2011-12-28 | 2015-11-25 | 英业达股份有限公司 | The aided analysis method of system mistake and device thereof |
| CN105247048A (en) * | 2013-05-31 | 2016-01-13 | 帝斯曼知识产权资产管理有限公司 | Immobilized proline-specific endoprotease |
| CN112634977A (en) * | 2019-09-24 | 2021-04-09 | 新唐科技股份有限公司 | Chip with debugging memory interface and debugging method thereof |
-
2003
- 2003-01-22 CN CNA031008402A patent/CN1519729A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034135B (en) * | 2006-03-06 | 2010-08-18 | 联发科技股份有限公司 | Integrated circuit with scan-based debugging and debugging method thereof |
| CN101620558B (en) * | 2008-07-01 | 2011-08-03 | 环旭电子股份有限公司 | General debugging-assistant device |
| CN103186431B (en) * | 2011-12-28 | 2015-11-25 | 英业达股份有限公司 | The aided analysis method of system mistake and device thereof |
| CN105247048A (en) * | 2013-05-31 | 2016-01-13 | 帝斯曼知识产权资产管理有限公司 | Immobilized proline-specific endoprotease |
| CN112634977A (en) * | 2019-09-24 | 2021-04-09 | 新唐科技股份有限公司 | Chip with debugging memory interface and debugging method thereof |
| CN112634977B (en) * | 2019-09-24 | 2023-11-17 | 新唐科技股份有限公司 | Chip with debug memory interface and debug method thereof |
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