CN1518797A - Antifuse reroute of dies - Google Patents

Antifuse reroute of dies Download PDF

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Publication number
CN1518797A
CN1518797A CNA028082524A CN02808252A CN1518797A CN 1518797 A CN1518797 A CN 1518797A CN A028082524 A CNA028082524 A CN A028082524A CN 02808252 A CN02808252 A CN 02808252A CN 1518797 A CN1518797 A CN 1518797A
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chip
circuit
coupled
fuse
contact
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CN1316744C (en
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���ġ����
凯文·杜斯曼
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MICROTECH CO Ltd
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MICROTECH CO Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/12—Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.

Description

The anti-fuse of tube core changes route
Technical field
Present invention generally relates to integrated circuit, relate to integrated circuit more precisely with contact able to programme.
Background technology
The semiconductor chip combination of knowing has the package die that comprises a plurality of contact solder joints.These contact solder joints are electrically coupled to each the discrete outside contact pin that extends from die package, are connected so that semiconductor is formed with outer member.Though this structure is acceptable in some applications, the inventor has realized that the signal path in chip can be changed under the situation of route (reroute) different physical location to the packaging part, is useful to some application.
Be used for the physical endpoint on the semiconductor chip is changed the technology of knowing of route, require the outer member such as framework and packaging part sometimes, for example the used the sort of element of chip laminate.And it is expensive that some technology implements, and needs a large amount of elements, and manufactures time-consumingly, usually causes extra testing equipment.According to the complexity of institute's development technology, for make one have change route the final chip of pin, need nearly 8 additional steps.And the loss of the speed of production that causes of desired additional parts, desired extra test and additional step, all have influence on have change route the manufacturing cost of chip of contact pin.
Summary of the invention
The present invention has overcome the shortcoming of before having known that changes route technology and chip laminate technology.According to the present invention, semiconductor chip is equipped with the routing circuit of internal programmable, so that signal path is assigned to the tie point of selection.This makes the user same chip manufacturing device and test component can be used for having in a large number the chip of different final structures.This technology starts and forbids that chip select feature, will contacts pin and change route to adapt to various sockets and to reorientate such as chip enable or the selection that is used for forming the input/output line of chip-stack contacts in the application of any number of pin comprising, all is useful.In chip-stack according to the present invention, in case chip is tested, chip just can be programmed, and cause to select signal path to be arranged in parallel, and the route of other signal path is chosen to the pin positions that is not used.So it is folded that these chips are carried on the back backing layer, promptly one at another top, and each contact tube instep is electrically coupled to together, thereby need not extra framework and pin changes routing plan.
According to one embodiment of the invention, provide the signal routing circuit.First signal path comprises first section and second section.Logical circuit is coupled to first section of first signal path, and first connection welding is coupled to second section of first signal path.The route matrix circuit is connected with first signal path that is arranged between first and second sections.The route matrix circuit can be programmed between first state and second state, and wherein, in first state, first section is coupled to second section, in second state, first section by decoupling in second section.Programmed circuit is coupled to and is used for the route matrix circuit of between first and second states route circuit being programmed.What wherein be concerned about is that programmed circuit can be introduced and may damage the signal that is connected to route matrix circuit or connection, and in programming process, programmed circuit preferably can be isolated from the route matrix circuit first and second sections of first signal path.
Except can be programmed in the individual signals path to be coupled to or decoupling in circuit logic, the route matrix circuit can also comprise a plurality of second sections, each a plurality of second sections are independently of one another, and route is determined to discrete tie point.Under this arrangement, first and second states of route matrix circuit can be programmed between first section and each a plurality of second sections, cause first section can be terminated to each connection on the route matrix second section side.As an alternative, first section can be programmed to route and be determined in a plurality of second sections one or more, so that the route of first section is determined between the possible physical connection position of any number.Be determined to the outside any a kind of accommodation that may make up that connects of physics as the path with an internal signal, the route that single physical connects can be determined to the internal signal paths of any number.Under this arrangement, first section also comprises a plurality of first sections, and each a plurality of first sections are independently of one another, and wherein first and second states of route matrix circuit can be programmed between each a plurality of first sections and second section.According to desired complexity and route option, first section can also comprise a plurality of first sections, and second section can also comprise a plurality of second sections, wherein, route matrix is able to programme, so that in a plurality of first sections any one optionally is coupled to and decoupling any one in a plurality of second sections.
Can determine with the routing infrastructure that at least one anti-fuse stores about route matrix.In a kind of circuit according to the present invention, anti-fuse can be arranged in series between first and second section of first signal path.Under this method, what be concerned about is that program voltage can damage the additional circuit that is coupled to anti-fuse, the route matrix circuit also comprises first program switch of series connection between the anti-fuse and first section, first program switch is coupled to programmed circuit effectively, and anti-fuse can be isolated from first section.Second program switch is connected alternatively between the anti-fuse and second section, and second program switch is coupled to programmed circuit effectively, and second section can be isolated from anti-fuse.
As a kind of accommodation of adopting the anti-fuse of connecting with first signal path, anti-fuse can be used as control signal and come the trigger switch matrix.Under this arrangement, the route matrix circuit also comprises the switch matrix between first and second sections that are arranged in first signal path, the anti-fuse that at least one is coupled to programmed circuit and the reading circuit that anti-fuse is coupled to switch matrix.This switch matrix comprises at least one switch, and can comprise extra logic, comprises demultiplexer and decoder according to the required complexity that changes route.Reading circuit is exported at least one anti-fuse is programmed the switch controlling signal that state is encoded.This signal is used to control effectively at least one switch.
The switch matrix that is coupled to anti-fuse wire readout circuit can have the first side contacts solder joint, the second side contacts solder joint and at least one and be arranged in switch between the first side contacts solder joint and the second side contacts solder joint, wherein, when anti-fuse is in first state, this switch is as open circuit, and when anti-fuse was in second state, this switch was as closed circuit.First and second states are represented the fusing of anti-fuse to be programming state and not to be fused and promptly be not programmed state.And the contact solder joint can only be embodied as the tie point to any side of switch element.And switch matrix can comprise a plurality of first side contacts solder joints, causes switch to be programmed, so that optionally the second side contacts solder joint is coupled to and decoupling any one in a plurality of first side contacts solder joints.As an alternative, switch matrix can comprise a plurality of first side contacts solder joints and a plurality of second side contacts solder joint.Under this arrangement, this switch can be programmed, so that optionally in a plurality of first side contacts solder joints any one is coupled to and decoupling any one in the second side contacts solder joint.
In second embodiment, but form semiconductor naked pipe core with the contact solder joint of internal distribution.The contact solder joint that this semiconductor element comprises logical circuit, route matrix able to programme, logical circuit is coupled to the signal path of route matrix and is coupled to route matrix.Route matrix comprises the switching circuit that can programme between first state and second state, wherein in first state, signal path is coupled to the contact solder joint, and in second state, signal path by decoupling in the contact solder joint.This semiconductor element can comprise a plurality of signal paths that logical circuit are coupled to route matrix alternatively.Under this arrangement, switching circuit can be programmed between first and second states, so that optionally determine any one route to the contact solder joint in a plurality of signal paths.As an alternative, this contact solder joint can also comprise a plurality of contact solder joints that are coupled to route matrix, and switching circuit can be programmed between first and second states, so that optionally determine any one route to signal path in a plurality of contact solder joints.The contact solder joint preferably also comprises a plurality of contact solder joints that are coupled to route matrix, and signal path preferably also comprises a plurality of signal paths that logical circuit are coupled to route matrix.Receive at route matrix under the situation of a plurality of contact solder joints and a plurality of signals, switching circuit can be programmed between first and second states, optionally in a plurality of contact solder joints any one is coupled to and decoupling any one in a plurality of signal paths.This switching circuit can be realized with at least one anti-fuse.For use can switch anti-fuse, this anti-fuse is placed between contact solder joint and the signal path by series connection, and programmed circuit is coupled to anti-fuse.As adopting anti-fuse is a kind of accommodation of switch, and anti-fuse can be used to control switch, comprises the switch based on transistor.Also comprise at the route matrix circuit under the situation of the on-off controller that comprises an anti-fuse at least, the anti-fuse programming circuit that is coupled to anti-fuse, the anti-fuse wire readout circuit that is coupled to anti-fuse and the switch that at least one is controlled by on-off controller, realized this point.And demultiplexer, decoder and other logical circuit are coupled at least one switch with this anti-fuse wire readout circuit.
Utilization can change the semiconductor element of route, can easily realize stacked scheme.Second semiconductor element can be with to have first semiconductor element that contacts able to programme stacked.Second semiconductor element preferably includes at least one contact that is not used that is not coupled to logical circuit.First and second semiconductor elements are carried on the back the back of the body, and the contact of tube core is coupled in parallel to together.Two semiconductor elements can comprise the contact that changes routing circuit and be not used alternatively.
The contact that can change route has various uses in the manufacturing of memory device, memory device wherein comprises the logical circuit with memory cell array, the Memory Controller that is coupled to the address decoder of memory cell array and is coupled to memory cell array.A plurality of conductive paths are coupled to logical circuit, at least one chip selection conductive path that wherein a plurality of conductive paths also comprise a plurality of I/O conductive paths that are coupled to Memory Controller and are coupled to Memory Controller.In addition, a plurality of contacts are coupled to a plurality of conductive paths, and able to programme changing between routing circuit places a plurality of contacts by series connection at least one of at least one and a plurality of conductive paths.In one application, changing routing circuit can be programmed, so that select conductive path to determine route and isolate to the chip between at least two in a plurality of contacts.Non-selected contact thereby be terminated to logical circuit and memory circuitry.As an alternative, changing routing circuit can be programmed, so that the I/O conductive path between a plurality of contacts is determined route and isolated.In any these are arranged, can provide the second memory spare identical or different with first memory spare.Two kinds of memory devices preferably have the contact that at least one is not used.These memory devices are carried on the back the back of the body, and the contact of device is by Parallel coupled.In target is to improve under the situation of total storage volume of chip laminate, and the chip that can change the memory chip of route is selected to be reallocated, and makes it the contact float that is not used with second memory spare.The chip of second memory spare select should with the contact float that is not used of first memory spare.Power line, input/output line, address wire or other line are oriented to the parallel alignment structure.So two kinds of devices can shared same data, address and power connect, and since the chip selection of each memory device comprise that discrete connection remains and can select respectively.
As an alternative, first memory device that can change route contacting of comprising that a plurality of input/output lines and similarity number purpose be not used and second memory spare comprises under the situation of the same number of contact that is not used, two kinds of devices can be programmed and carry on the back backing layer and fold, cause the contact float that is not used of the input/output line and the second memory spare of first memory spare, and the contact float that is not used of the I/O of second memory spare and first memory spare.All other contact is oriented to and the similar parallel alignment that is connected.Therefore, power contact, chip are selected contact and other reference contact float.Under this arrangement, enabling signal just starts two chips simultaneously, and the route of each memory device I/O contact is directly determined.So individual address can be individually in the word length that the increase on available total input/output line is provided on each memory device.
Be understandable that the present invention can be used to naked pipe core or the packaged chip finished are carried out reprogramming.And, the changing route and can be used to realize stacked tube core and chip stacked structure of contact.Though be described to the stacked of two devices, depend on number and the route of realization and the complexity of switching circuit of the available pin that is not used, can realize the lamination device of any number.And the present invention can be used to improve the capacity of stacked combination, is used for single chip is recombinated so that adapt to various different sockets, or is used for changing the feature or function of single or multiple devices.
Description of drawings
When reading in conjunction with following accompanying drawing, can understand the following detailed description of the preferred embodiment of the invention best, in these accompanying drawings, similar structure represents with similar reference number, and wherein:
Fig. 1 shows the logic line that can change on the semiconductor chip of encapsulation with the form of block diagram between two external pin connect;
Fig. 2 is the block diagram of the system of any one route during the one or more logic line of definition connect to several external pin on the semiconductor chip of encapsulation with anti-array of fuses;
Fig. 3 is used for rough schematic view at the circuit of the route of a logic line of definition between two external pin connect on the semiconductor chip of encapsulation;
Fig. 4 is the rough schematic view that changes the circuit of the signal path in the route semiconductor with anti-fuse, and anti-fuse is wherein connected with signal path; And
Fig. 5 shows a kind of stacked semiconductor chip, and one of its chips has had can change the logic line that is routed to different pins position on the semiconductor package part.
Embodiment
With the mode of example rather than the mode of restriction enforcement specific embodiments of the present invention is described with reference to the accompanying drawings.It being understood that the functional description according to herein, can realize other embodiment, and can combining structure and logical changes and do not depart from scope of the present invention.
With reference to Fig. 1, the present invention has been shown in simplified block diagram.The semiconductor 100 of encapsulation comprises that a plurality of external pin connect 102,104,106,108.Connect pin 102 and be not used, thereby electricity is isolated from logical circuit 120.The external signal that is applied to contact pin 102 will be terminated to logical circuit 120.Connect pin 108 and be coupled to logical circuit 120 via special circuit path 114.Circuit paths 118 is coupled to route matrix 116 with logical circuit 120.According to the state of route matrix 116, logical circuit 120 is coupled to via circuit paths 118 and 110 and is connected pin 104, is coupled to via circuit paths 118 and 112 to be connected pin 106.Perhaps, signal path 118 can end at for example node 122 places, and wherein signal path 118 is not coupled to any connection pin.It should be noted that at signal path 118 to be coupled under the situation of pin 104, connect pin 106, be applied to the signal that connects pin 106 thereby be terminated to logical circuit 120 from logical circuit 120 decouplings.It being understood that this logical circuit can be any circuit that comprises memory device, microprocessor, gate, transducer etc.And, can use the pin of any number, comprise electricity that isolate with pin conduction.And, the pin of conduction, comprise those that are coupled by route matrix, can carry with comprising and be connected, can comprise that it is the signal that log-on message, clock signal, reference signal, address information or treat will be applied to any other type of logical circuit that I/O data message, chip are selected with the power of supply voltage.In addition, change the application and the complexity of route, can realize being used for constituting any technology of knowing of route matrix 116 according to desired signal.Route matrix can be single switch, fuse, anti-fuse, or complexity on demand and comprise demultiplexer, decoder, switch matrix, switch arrays etc.
A kind of method of control route matrix is to utilize anti-fuse.Anti-fuse is a kind of circuit element that can be used to provide between the circuit node disposable programmable permanent electric optionally to connect.Can use similar in appearance to the structure of capacitor and realize anti-fuse.In its default setting, two conducting terminals are separated by dielectric layer.This provides high resistant between two terminals of anti-fuse, cause " shutoff " state and do not programme.Apply a big program voltage by means of two terminals crossing over anti-fuse, this anti-fuse can be programmed to " open-minded " state.When applying big voltage, medium is breakdown, forms the path of conduction between two terminals.The path of this conduction has reduced the resistance of anti-fuse effectively.Yet in case be programmed, this anti-fuse just can not be programmed and get back to off state.
With reference to Fig. 2, show block diagram, illustrated and used anti-fuse to redefine signal from an a kind of method that connects pin to the route of another connection pin.The signal path 128 of any number is coupled to route matrix 116 with logical circuit 120.The number of circuit paths 128 will depend on the number in the path for the treatment of to change, to change route or stopping.Signal path 128 is fed in the switch matrix 130.Switch matrix 130 signal path 128 that each is discrete is assigned to any one possible access path 126.The route of any one signal path 128 can be defined into one or more possible access path 126, and perhaps, any one signal path 128 can be terminated to access path 126.In order to determine the conversion figure, anti-array of fuses 134 is programmed by means of one or more the anti-fuse in the array that optionally fuses with programmed circuit 136.Latch cicuit 132 is a kind of reading circuits, and it reads the state of the anti-fuse in the anti-array of fuses 134, and control signal 138 is offered switch matrix 130.According to the number of the anti-fuse of realizing, latch cicuit 132 can be with the various state encodings of anti-fuse in the control line than peanut.Under the situation that latch cicuit is encoded to the anti-fuse state in the anti-array of fuses 134, switch matrix 130 comprises extra decoding logic.
With reference to Fig. 3, show the example of realizing pin programming and routing circuit 200.In this example, the route of signal 248 is defined into one of two possible connections 272 and 274.This can be used as example chip select signal is programmed into one of two possible connections, stays the connection (not shown) that is not used that is isolated from logical circuit.At first, it should be understood that the flexibility of typical anti-fuse and structure cause the designer to change the broad range of routing circuit design.And, can form any routing plan according to the chip purposes to be used for and the requirement of chip purposes.Therefore, Fig. 3 is considered to be exemplary and not restrictive.Briefly, changing routing circuit 200 comprises to be coupled to and latchs or reading circuit 132 and the anti-array of fuses 134 that is coupled to programmed circuit 136.The output of reading circuit 132 is coupled to switch matrix 130.Specifically, the conversion behavior of switch matrix 130 is subjected to the State Control of anti-array of fuses 134.Though what illustrate only has an anti-fuse 202 herein, it being understood that the consideration of the number etc. of the signal that changes route according to treating to programme, can realize the anti-fuse 202 of any number.Say that typically control signal Vcont1 208 is biased to the grid 210 that make transistor 212 and connects, program voltage Vprog 214 thereby be terminated to anti-fuse 202.Control signal Vcont2 216 is biased to the grid 218 that make transistor 220 and disconnects, anti-fuse 202 second dull and stereotyped 206 thereby be coupled to ground 222 effectively by transistor 220.The state of control signal Vcont3 224 is biased to the grid 226 that make transistor 228 and connects, and first flat board 204 with anti-fuse 202 is isolated from by the path of transistor 228 to ground 230 effectively.
By means of control signal Vlatch1 238 being setovered to disconnect the grid 240 of transistor 242, and further by means of control signal Vlatch2 232 being setovered to disconnect the grid 234 of transistor 236, effectively read-out voltage Vsense 246 is coupled to anti-fuse 202 by transistor 242 and 236, reading circuit 132 reads the state of anti-fuse 202.The grid 226 of transistor 228 are turned off, and by transistor 228 first flat board 204 of anti-fuse 202 are isolated from ground 230.Equally, the grid 210 of transistor 212 are switched on, thereby program voltage Vprog 214 is isolated from anti-fuse 202.The grid 218 of transistor 220 are disconnected, and second flat board 206 with anti-fuse 202 is connected to ground 222 by transistor 220 effectively.If anti-fuse 202 is not programmed, promptly do not fused, then the dielectric layer between first and second dull and stereotyped 204 and 204 is isolated from by anti-fuse 202 read-out voltage Vsense 246 to ground, so the voltage at node 244 places becomes read-out voltage 246.All are floated to the path on ground basically by anti-fuse 202.If anti-fuse 202 is programmed promptly and is fused, then form conductive path, and read-out voltage 246 there has been the path of arriving ground 222 by anti-fuse 202 and transistor 220 by the medium that first flat board 204 is separated in second flat board 206.This just pulls to ground with the voltage at reference node 244 places.Therefore, when anti-fuse 202 was not fused, reading circuit had realized approximating greatly the voltage of read-out voltage Vsense 246, and when anti-fuse 202 is fused, has realized approximating greatly the voltage on ground.It should be understood that in this simple case only a signal will change route.According to application, can utilize any more complicated reading and encoding scheme.For example, to change potentially under the situation of route, can utilize a plurality of anti-fuses 202 that can programme respectively separately at a large amount of signals.And reading of anti-fuse state can be encoded, or handles with any technology that comprises multiplexed and coding etc.
For anti-fuse 202 is programmed, Vcont2 216 is biased to the grid 218 of connecting transistor 220.Anti-fuse 202 is terminated to ground 222 by transistor 220 now.Equally, control signal Vlatch2 232 is biased to the grid 234 of connecting transistor 236, transistor 236 is turn-offed, thereby reading circuit 132 is isolated from anti-fuse 202.Then, control signal Vcont1 208 is by open-minded.Vcont1 208 is biased to the grid 210 that disconnect transistor 212.Therefore, program voltage Vprog 214 is coupled to second flat board 206 of anti-fuse 202.Disconnecting the grid 226 of transistor 228, transistor 228 is by open-minded by means of bias control signal Vprog3 224, so by transistor 228 first flat board 204 of anti-fuse 202 is coupled to ground 230.Be applied to second flat board 206 of anti-fuse 202 as program voltage Vprog 214, and first flat board 204 of anti-fuse 202 is connected to ground 230 o'clock, voltage difference between first and second dull and stereotyped 204 and 206 should be enough to puncture the medium that is formed between first and second dull and stereotyped 204 and 206, so form the circuit paths that a resistance has reduced.Turn-off transistor 236 and just the circuit outside the anti-fuse is isolated from program voltage Vprog 214.Blown anti-fuse 202 desired too high voltages may damage the other parts of circuit sometimes.Can not be subjected at all other circuit elements may needn't connecting the grid 234 of transistor 236 under the situation of influence of higher program voltage Vprog 214.Equally, transistor 212,220 and 228 should be designed to bear higher voltage and the electric current relevant with the programming of anti-fuse 202.And, because the device that anti-fuse 202 is a kind of disposable programmables, so programming operation only needs to carry out once the common some time after Computer-Assisted Design, Manufacture And Test.It should be understood that when device is in the form of semiconductor naked pipe core, can finish programming, perhaps, can in final packaging part, be programmed.At last, because the anti-fuse 202 of design is manufactured into the state that is not fused, so can not need programming.
Reference node 244 provides the signal that reflects anti-fuse 202 states.The voltage at reference node place is applied directly to the grid 268 of transistor 270.The reference voltage at node 244 places is by transistor 254 and 260 phase inverter circuits of forming.When reference voltage was low, the grid 258 at transistor 260 places were switched on, and phase inverter node 256 is terminated to ground 276 by transistor 260.Because phase inverter reference voltage 250 is added on the grid 252 of transistor 254, makes phase inverter node 256 can keep high voltage, so transistor 254 is always open-minded.When reference node 244 was high, the grid 258 of transistor 260 disconnected, and phase inverter node 256 is coupled to ground effectively.Therefore, the control signal at grid 262 places is opposite with grid 268 usually, and any one preset time only in the transistor 264 and 270 be in open-minded.Signal 248 is therefore by arriving connection 272 or connecting 274.The connection that is not used is terminated to circuit.
A kind of flexible arrangement that makes signal change route with anti-fuse is directly anti-fuse to be placed signal path.With reference to Fig. 4, signal 402 via transistor 404 with 412 and anti-fuse 414 be coupled to external pin and be connected 436.In course of normal operation, control signal Vcont1 is biased to the grid 406 that make transistor 404 and disconnects, and the grid 410 of transistor 412 also disconnect.Control signal Vcont2 420 is biased to the grid 422 that make transistor 426 and connects, and the reference signal of will programming 424 is isolated from anti-fuse 414.Equally, control signal Vcont3428 is biased to the grid 430 that make transistor 432 and connects, and anti-fuse 414 is isolated from the path on ground 434 by transistor 432.Therefore, programmed circuit is terminated to anti-fuse 414.If anti-fuse 414 is not programmed promptly and is not fused, then anti-fuse first dull and stereotyped 416 is isolated from the outside with medium between second flat board 418 with signal 402 and is connected pin 436.For signal 402 being coupled to the outside pin 436 that connects, anti-fuse is programmed promptly and is fused.
For anti-fuse 414 is programmed, control signal Vcont1 is biased to and isolates anti-fuse.Under this arrangement, the grid 406 of transistor 404 are switched on, and first flat board 416 of anti-fuse 414 is isolated from signal 402, and the grid 410 of transistor 412 are switched on, thereby second flat board 418 of anti-fuse 414 is isolated from the outside pin 436 that connects.Do like this is to avoid being subjected to the program voltage infringement for guard signal path 402 with the outside pin 436 that is connected.If each element can bear program voltage and do not injured, then need not these.In case isolated, control signal 420 just is biased to the grid 422 that make transistor 426 and is disconnected, and programming reference voltage Vprog 424 is coupled to first flat board 416 of anti-fuse 41 4.In addition, control voltage Vcont3 428 is biased to the grid 430 that disconnect transistor 432, and second flat board 418 of anti-fuse 414 is connected to ground 434 by transistor 432 effectively.Under this arrangement, electric current flows through anti-fuse 414, punctures the medium between first dull and stereotyped 416 and second flat board 418, produces conductive path between first and second flat boards 416 and 418 of anti-fuse 414.Though it should be understood that only to show an anti-fuse and only external pin connection, can utilize the anti-fuse of any number to be determined to the outside signal path that connects any number of pin.And, can adopt the technology of knowing, comprise demultiplexer, encoder, decoder, anti-array of fuses, anti-fuse matrix etc.
Laminated device
In the circuit shown in Fig. 3 or 4, can be easy to realize stacked device according to functional similarity.For example, memory chip can be laminated together, so that increase available word length or improve total memory capacity.To realize improving under the situation of memory capacity, can be with two or more a plurality of chip laminate to together.Power line, address wire and input/output line all are connected in parallel to together, and each chip to remain to that its chip selects be unique route of chip enable pin.Utilize the stacked framework of external complex, typically finished this point.
With reference to Fig. 5, show chip-stack 300.Chip-stack 300 comprises first chip 301 with a plurality of contact pins 304,308,312,316.Second chip 302 comprises contact pin 306,310,314,318.It is stacked that chip 301 and 302 is carried on the back back of the body formula, and the selection contact pin of first chip 301 is aimed at the corresponding contact pin of second chip 302, so that form the conduction coupling column of perpendicular.At least one chip 301 also comprises route matrix 332, so that at least one signal 322 to the selection 308 and 312 from logical circuit 330 to pin carries out inner reprogramming as shown, but be understandable that, as explaining more fully, the routing plan of any number all is possible herein.Route matrix 332 need not the desired external frame of stacked die and the outside changes routing circuit, and has also eliminated to making the requirement of lamination to the testing equipment of two different chips and repetition.Two identical chips can be laminated together, and perhaps, can stackedly have heteroid chip.And chip 301 and 302 can comprise route submatrix 332.
Before stacked, first chip 301 is programmed, so that determine the route of signal 322 to pin 308 or 312.The route of for example supposing signal path 322 is determined to pin 308.The pin 312 that is not programmed becomes and is isolated from logical circuit 330.The contact pin 310 of second chip 302 can be the contact pin that is not used, or the similar function that provides to the signal path 322 of first chip 301 of hypothesis for example.It is folded that chip 301 and 302 is carried on the back backing layer, contacts pin 310 perpendicular alignmnets on the pin that is programmed 308 that makes first chip 301 and second chip 302.The contact pin 312 that is not programmed on first chip 301 is aimed at the pin 314 of contacting of logic in distributing to second chip.
The signal that is changed route can be chip select signal or any other the external signal for the treatment of to be applied to chip-stack 300.And a plurality of lines can be changed route.For example, the several lines that comprise the I/O on first chip 301 can be changed route, so that in alignment with the pin that is not used on second chip 302.Equally, the I/O pin on second chip 302 can be changed route, so that in alignment with the pin that is not used on first chip 301.This technology can be used to any signal of chip-stack.And person skilled in the art it should be understood that this technology is applicable to that with it packaged die is such, is equally applicable to semiconductor naked pipe core.At last, according to the design that changes route matrix 332 that is realized, any number of dies can both be laminated together.
Need not the outside except being used for the changing the distribution of route pin of stacked die and change the route, the present invention also can be used to provide the able to programme single chip solution that can be applicable to that several different pins distribute.For example, by means of the pin that default structure is provided for a kind of socket, but on enough complicated chip, provide route matrix, so that signal path is directed to different pins again to be connected, can be used to several different sockets with a kind of microprocessor, make chip can work in different sockets.
As the third accommodation, provide the inner option that can change route.For example, function and feature by the extensive application of optionally forbidding or starting in, can utilize single logic chip.For example, a kind of chip can as two kinds of disable feature be connected less chip model and make, test and sell.Perhaps, the user may wish that pin is become not to be used.In this application, pin is terminated to logic, but internal signal paths may need to guide again.For example, in a kind of simple application, by means of forbidding that one of external pin connection causes a NAND gate input, and will once cause the signal path of present forbidden connection to be connected internally to the position that this opens, the NAND gate chip of one 3 input can be become the NAND gate of one 2 input by internal conversion.This makes identical chip-die can be used in multiple purpose.
Person skilled in the art it should be understood that and can implement programming of the present invention before or after final assembling.When semiconductor was in the form of naked pipe core, anti-fuse arrangement described herein can be programmed, and is packaged into its final form then, perhaps, can encapsulate the naked pipe core, then programming.
Described the present invention in detail with reference to its preferred embodiment, obviously, can carry out various corrections and change and do not depart from the scope of the present invention of claims defined.

Claims (76)

1. signal routing circuit, it comprises:
First signal path with first section and a plurality of second sections, each described a plurality of second sections are independently of one another;
Be arranged in the route matrix circuit that described first section is connected with described first signal path between described a plurality of second sections, described route matrix circuit can with described first section form first state that contact and with second state that contacting of described first section is disconnected between programme for each described a plurality of second sections; And
Be coupled to the programmed circuit of described route matrix circuit, described programmed circuit is arranged to optionally be each described a plurality of second section programmings between described first and second states.
2. according to the signal routing circuit of claim 1, wherein, described first section also is coupled to logical circuit.
3. according to the signal routing circuit of claim 2, wherein, each described second section also is coupled to relevant contact solder joint.
4. according to the signal routing circuit of claim 1, wherein, each described second section also is coupled to logical circuit.
5. according to the signal routing circuit of claim 4, wherein, described first section also is coupled to the contact solder joint.
6. according to the signal routing circuit of claim 1, also comprise a plurality of first sections, wherein, described route matrix is able to programme, so that any one of described a plurality of first sections optionally is coupled to and decoupling any one in described a plurality of second sections.
7. according to the signal routing circuit of claim 1, wherein, described route matrix circuit comprises the anti-fuse between described second section that is arranged in series in described first section and selection, and wherein, described programmed circuit is arranged to the described anti-fuse of programming between described first and second states.
8. according to the signal routing circuit of claim 7, wherein, described route matrix circuit also comprises first program switch of series connection between described anti-fuse and described first section, and described first program switch is coupled to described programmed circuit effectively.
9. according to the signal routing circuit of claim 7, wherein, described route matrix circuit also comprises second program switch of series connection between described second section of described anti-fuse and described selection, and described second program switch is coupled to described programmed circuit effectively.
10. according to the signal routing circuit of claim 1, wherein, described route matrix comprises:
Be arranged in the switch matrix between described first and second sections of described first signal path;
At least one anti-fuse; And
Described at least one anti-fuse is coupled to the reading circuit of described switch matrix, wherein, described switch matrix can be programmed between second state of described second section by decoupling at first state and described first section that described first section is coupled to described second section; And
The described programmed circuit described anti-fuse that is arranged to optionally programme, so as between described first and second states described switch matrix of control.
11. signal routing circuit according to claim 10, wherein, described reading circuit is exported at least one switch controlling signal, the programming state of described at least one anti-fuse is encoded, and described switch matrix is controlled by described at least one control signal effectively.
12. according to the signal routing circuit of claim 11, wherein, described switch matrix also comprises decoding logic, so that control its conversion with described at least one control signal.
13. a signal routing circuit, it comprises:
The anti-fuse that can programme from first state to second state;
Be coupled to the anti-fuse programming circuit of described anti-fuse;
Be coupled to the anti-fuse wire readout circuit of described anti-fuse; And
Route matrix, it is coupled to described anti-fuse wire readout circuit and has first side contacts, second side contacts and at least one is arranged in switch between described first side contacts and second side contacts, wherein, when described anti-fuse is in described first state, described at least one switch is as open circuit, and when described anti-fuse was in described second state, described switch was as connecting circuit.
14. signal routing circuit according to claim 13, wherein, described route matrix also comprises a plurality of first side contacts, and described at least one switch is able to programme, so that optionally described second side contacts is coupled to and any combination of decoupling in described a plurality of first side contacts.
15. according to the signal routing circuit of claim 14, wherein, described at least one switch is able to programme, so that described second contact is selected contact to change to be routed to second of described a plurality of first side contacts to select contact from first of described a plurality of first side contacts.
16. signal routing circuit according to claim 13, wherein, described route matrix also comprises a plurality of first side contacts and a plurality of second side contacts, and described at least one switch is able to programme, so that optionally any combination of described a plurality of first side contacts is coupled to and any combination of decoupling in described second side contacts.
17. but first semiconductor element with contact solder joint of internal distribution, it comprises:
Logical circuit;
Route matrix able to programme with switching circuit;
Be coupled to the access path of described switching circuit matrix; And
Described logical circuit is coupled to a plurality of signal paths of described route matrix, and wherein, described switching circuit is able to programme between first and second states, so that determine that optionally any one is to route of described access path in described a plurality of signal paths.
But 18. according to first semiconductor element of the contact solder joint with internal distribution of claim 17, wherein, described route matrix also comprises:
At least one anti-fuse;
Be coupled to the programmed circuit of described at least one anti-fuse; And
Be coupled to the anti-fuse wire readout circuit of described at least one anti-fuse and described switching circuit.
19. a signal routing circuit, it comprises:
First signal path with first section and second section;
Be coupled to the logical circuit of described first section of described first signal path;
With the parallel route matrix circuit of described first signal path that is arranged between described first and second sections, described route matrix circuit can be programmed between second state of described second section by decoupling at first state and described first section that described first section is coupled to described second section; And
Be coupled to the programmed circuit of described route matrix circuit, described programmed circuit is arranged to the optionally described routing circuit of programming between described first and second states, and described route matrix circuit is isolated from described first and second sections of described first signal path in programming process.
20. according to the signal routing circuit of claim 19, wherein, described route matrix comprises the anti-fuse of series connection between described first and second sections.
21. a signal routing circuit, it comprises:
First signal path with first section and second section;
Be coupled to the logical circuit of described first section of described first signal path;
Be coupled to first connection welding of described second section of described first signal path;
The route matrix circuit, it comprises and is arranged in series at least one anti-fuse of the described first signal path positioned parallel between described first and second sections, and described route matrix circuit can be programmed between second state of described second section by decoupling at first state and described first section that described first section is coupled to described second section; And
Be coupled to the programmed circuit of described route matrix circuit, described programmed circuit is arranged to the optionally described route matrix circuit of programming between described first and second states.
22. according to the signal routing circuit of claim 21, wherein, described route matrix circuit also comprises first program switch of series connection between described anti-fuse and described first section, described first program switch is coupled to described programmed circuit effectively.
23. according to the signal routing circuit of claim 22, wherein, described route matrix circuit also comprises second program switch of series connection between described anti-fuse and described second section, described second program switch is coupled to described programmed circuit effectively.
24. according to the signal routing circuit of claim 21, wherein, described at least one anti-fuse is isolated from described first and second sections of described first signal path by electricity in programming process.
25. a semiconductor element lamination, it comprises:
First semiconductor element, it has:
First logical circuit;
A plurality of first tube core contact solder joints;
The first via is by matrix circuit; And
Described first logical circuit is coupled to a plurality of first tube core signal paths of described a plurality of first tube core contact solder joints;
Wherein, the route of at least one described a plurality of first tube core signal path is determined to described first route matrix, the route of at least one described a plurality of first tube core contact solder joint is determined to described first route matrix, and the described first via is able to programme by matrix circuit, is coupled in the described first via by in described a plurality of first tube cores contact solder joints of matrix circuit any one so that be determined to with will being coupled to any one Route Selection in described a plurality of first tube core signal paths of described route matrix;
And,
Second semiconductor element, it has:
Second logical circuit;
A plurality of second tube core contact solder joints; And
A plurality of second tube core signal paths, each described a plurality of second tube core signal paths are coupled to the described second tube core logical circuit with the selection contact solder joint of described a plurality of second tube core contact solder joints;
Wherein, described first and second semiconductor elements are carried on the back the back of the body each other, and each described a plurality of first tube core contact solder joints are coupled to the relevant contact solder joint of described a plurality of second tube core contact solder joints.
26. semiconductor element lamination according to claim 25, wherein said second tube core also comprises the secondary route matrix circuit, and wherein the route of at least one described a plurality of second tube core signal path is determined to described secondary route matrix circuit, and the route of at least one described a plurality of second tube core contact solder joint is determined to described secondary route matrix circuit.
27. the semiconductor element lamination according to claim 25 also comprises:
The semiconductor element that at least one is extra, it has:
Logical circuit;
A plurality of contact solder joints;
The route matrix circuit; And
Described logical circuit is coupled to a plurality of signal paths of described a plurality of contact solder joints;
The route of at least one described a plurality of signal path is determined to described route matrix, and the route of at least one described a plurality of contact solder joint is determined to described route matrix;
Described at least one extra semiconductor element and described first and second tube cores are carried the back of the body on the back, and each described a plurality of contact solder joints are coupled to described a plurality of first tube core contacts solder joint with second tube core relevant contact solder joint.
28. according to the semiconductor element lamination of claim 25, wherein, the programmed circuit that described first route matrix also comprises at least one anti-fuse and is coupled to described at least one anti-fuse.
29. according to the semiconductor element lamination of claim 28, wherein, described at least one anti-fuse is placed at least one described a plurality of first tube core signal path to contact between the solder joint with at least one described first tube core by series connection.
30. according to the semiconductor element lamination of claim 29, wherein, the described first via is arranged in programming process described at least one anti-fuse is isolated from described first logical circuit by matrix circuit.
31. according to the semiconductor element lamination of claim 25, wherein, described route matrix circuit also comprises:
Switch matrix;
At least one anti-fuse;
Be coupled to the programmed circuit of described at least one anti-fuse; And
Described at least one anti-fuse is coupled to the reading circuit of described switch matrix, wherein, described switch matrix is determined to the described first via with route and optionally is coupled to decoupling by the signal path of the selection of the described first tube core signal path of matrix circuit and is determined to the described first via is contacted the selection of solder joint by described first tube core of matrix circuit contact solder joint in route.
32. semiconductor element lamination according to claim 31, wherein, described reading circuit is exported at least one switch controlling signal, the state that is programmed of described at least one anti-fuse is encoded, and described switch matrix is controlled by described at least one control signal effectively.
33. chip assembly parts, it comprises:
Has first chip of a plurality of connection pins and able to programme so that internal signal changed the routing circuit that changes of second pin that is routed to described a plurality of contact pins from first pin of described a plurality of contact pins; And
Second chip with a plurality of contact pins, wherein, at least one of described a plurality of contact pins is not used;
The selection pin of described a plurality of contact pins of wherein said first chip is coupled to the relevant pin of described a plurality of contact pins of described second chip.
34. according to the chip assembly parts of claim 33, wherein, described first and second chips are laminated together.
35. chip assembly parts according to claim 33, wherein, described first and second chips are carried on the back to be carried on the back together, cause described first chip described a plurality of contact pins selection pin perpendicular in alignment with and be coupled to the relevant pin of described a plurality of contact pins of described second chip.
36. according to the chip assembly parts of claim 33, wherein, described first chip described changes routing circuit and comprises anti-fuse and change routing circuit.
37. chip assembly parts according to claim 33, wherein, described first chip also comprises the selection pin of the described a plurality of contact pins that are coupled to described second chip and decoupling at least one contact pin that is not used of described at least one contact pin that is not used of described second chip.
38. according to the chip assembly parts of claim 33, wherein:
Described a plurality of contact pins of described first chip also comprise at least one first chip I/O pin and at least one first chip is selected pin; And
Described a plurality of contact pins of described second chip also comprise at least one second chip I/O pin and at least one second chip is selected pin;
Wherein, described at least one first chip I/O pin is coupled to described at least one second chip I/O pin, described at least one first chip selection pin is coupled to described at least one contact pin that is not used of described second chip, and described at least one second chip selects pin to be coupled to described at least one contact pin that is not used of described first chip.
39. according to the chip assembly parts of claim 33, wherein:
Described a plurality of contact pins of described first chip also comprise at least one first chip I/O pin and at least one first chip is selected pin; And
Described a plurality of contact pins of described second chip also comprise at least one second chip I/O pin and at least one second chip is selected pin;
Wherein, described at least one first chip is selected pin to be coupled to described at least one second chip and is selected pin, described at least one first chip I/O pin is coupled to described at least one contact pin that is not used of described second chip, and described at least one second chip I/O pin is coupled to described at least one contact pin that is not used of described first chip.
40. according to the chip assembly parts of claim 33, wherein, the described routing circuit that changes comprises at least one anti-fuse.
41. according to the chip assembly parts of claim 33, wherein, the described routing circuit that changes also comprises:
At least one anti-fuse;
Be coupled to the anti-fuse programming circuit of described at least one anti-fuse;
Be coupled to the anti-fuse wire readout circuit of described at least one anti-fuse; And
At least one switch that is subjected to described anti-fuse wire readout circuit control effectively between described internal signal and at least one the described a plurality of contact pin.
But 42. the semiconductor element with contact solder joint of internal distribution, it comprises:
First semiconductor element, it has:
Logical circuit;
Route matrix able to programme with switching circuit;
Described logical circuit is coupled at least one signal path of described route matrix;
Be coupled at least one contact solder joint of described route matrix; And
Described switching circuit is able to programme, so that with any one route in described at least one signal path be determined to be isolated from described at least one contact in the solder joint any one, wherein, the described switching circuit programmed circuit that comprises at least one anti-fuse and be coupled to described at least one anti-fuse;
Second semiconductor element, it has:
Logical circuit;
A plurality of contact solder joints;
Described logical circuit is coupled to a plurality of signal paths of described a plurality of contact solder joints; And
Be isolated from least one contact solder joint that is not used of described logical circuit;
Wherein, described first and second semiconductor elements are carried on the back the back of the body, and each contact solder joint of described first semiconductor element be coupled to described second semiconductor element described a plurality of contact solder joints relevant solder joint with described at least one be not used contact solder joint.
43. a semiconductor chip stack, it comprises:
First semiconductor chip, it has:
First logical circuit;
A plurality of first chip contact pins;
The first via is by matrix circuit; And
Described first logical circuit is coupled to a plurality of first chip signal paths of described a plurality of first chip contact pins;
Wherein, the route at least one described a plurality of first chip signal path is determined to described first route matrix, the route of at least one described a plurality of first chip contact pin is determined to described first route matrix, and the described first via is able to programme by matrix circuit, is coupled in the described first via by in described a plurality of first chips contact pins of matrix circuit any one so that be determined to with will being coupled to any one Route Selection in described a plurality of first chip signal paths of described first route matrix;
And,
Second semiconductor chip, it has:
Second logical circuit;
A plurality of second chip contact pins; And
A plurality of second chip signal paths, each described a plurality of second chip signal paths are configured to the contact pin of the selection of described a plurality of second chip contact pins is coupled to described second chip logic circuit, wherein, described first and second semiconductor chips are carried on the back the back of the body each other, and each described a plurality of first chip contact pins are coupled to the relevant contact pin of described a plurality of second chip contact pins.
44. semiconductor chip stack according to claim 43, wherein said second chip also comprises the secondary route matrix circuit, and wherein the route at least one described a plurality of second chip signal path is determined to described secondary route matrix circuit, and the route of at least one described a plurality of second chip contact pin is determined to described secondary route matrix circuit.
45. according to the semiconductor chip stack of claim 43, wherein, described route matrix comprises series connection and places at least one described a plurality of first chip signal path to contact at least one anti-fuse between the pin with at least one described first chip.
46. according to the semiconductor chip stack of claim 43, wherein, described first route matrix also comprises:
At least one anti-fuse;
Be coupled to the programmed circuit of described anti-fuse;
Be coupled to the reading circuit of described at least one anti-fuse; And
Be coupling at least one described a plurality of first chip signal path and contact at least one switch that is coupled to described reading circuit effectively between the pin with at least one described first chip.
47. a memory circuit, it comprises:
Logical circuit, the Memory Controller that it comprises memory cell array, is coupled to the address decoder of described memory cell array and is coupled to described memory cell array;
Have first section that is coupled to described logical circuit and first signal path of a plurality of second sections, each described a plurality of second sections are independently of one another;
With the parallel route matrix circuit of described first signal path that is arranged between described first section and described a plurality of second sections, described route matrix circuit can described first section be coupled to first state of selection section of described a plurality of second sections and described first section by decoupling between the selection section of described a plurality of second sections to each described a plurality of second sections programmings; And
Be coupled to the programmed circuit of described route matrix circuit, described programmed circuit is arranged between described first and second states each described a plurality of second sections described route matrix circuit of optionally programming.
48. according to the memory circuit of claim 47, wherein, described first signal path comprises the chip select signal path.
49. according to the memory circuit of claim 47, wherein, described route matrix comprises at least one the anti-fuse that places between described first section and at least one described a plurality of second section.
50. according to the memory circuit of claim 49, wherein, described at least one anti-fuse is isolated from described first logical circuit by electricity in programming process.
51. memory circuit according to claim 47, wherein, described first signal path also comprises a plurality of first sections that are coupling between described logical circuit and the described route matrix circuit, and described route matrix circuit programmable is so that be coupled in described a plurality of first sections any one and decoupling any one in described a plurality of second sections.
52. according to the memory circuit of claim 51, wherein, described a plurality of first sections respectively comprise the input/output signal path.
53. according to the memory circuit of claim 47, wherein, described route matrix also comprises:
At least one anti-fuse;
Be coupled to the programmed circuit of described anti-fuse;
Be coupled to the reading circuit of described at least one anti-fuse; And
Be coupling between described a plurality of first section and described a plurality of second section and be coupled at least one switch of described reading circuit effectively.
54. memory circuit according to claim 53, wherein, described reading circuit is exported at least one switch controlling signal, the programming state of described at least one anti-fuse is encoded, and described at least one switch is controlled by described at least one control signal effectively.
55. according to the memory circuit of claim 54, wherein, described switch matrix also comprises decoding logic, so that control described at least one switch with described at least one control signal.
56. a memory device, it comprises:
The storage chip packaging part;
Be included in the logical circuit in the described storage chip packaging part, the Memory Controller that it comprises memory cell array, is coupled to the address decoder of described memory cell array and is coupled to described memory cell array;
Be coupled to a plurality of contact pins of described storage chip packaging part;
Have first signal path of first section that is coupled to described logical circuit and a plurality of second sections that are coupled to described a plurality of selection pins that contact pin, each described a plurality of second sections are independently of one another;
With the parallel route matrix circuit of described first signal path that is arranged between described first section and described a plurality of second sections, described route matrix circuit can described first section be coupled to first state of selection section of described a plurality of second sections and described first section by decoupling between first state of the selection section of described a plurality of second sections to each described a plurality of second sections programmings; And
Be coupled to the programmed circuit of described route matrix circuit, described programmed circuit is arranged between described first and second states each described a plurality of second sections described route matrix circuit of optionally programming.
57. according to the memory device of claim 56, wherein, described first signal path comprises the chip select signal path.
58. according to the memory device of claim 56, wherein, described route matrix comprises at least one the anti-fuse that places between described first section and described a plurality of second section.
59. according to the memory device of claim 58, wherein, described at least one anti-fuse is isolated from described first logical circuit by electricity in programming process.
60. memory device according to claim 56, wherein, described first signal path also comprises a plurality of first sections that are coupling between described logical circuit and the described route matrix circuit, and described route matrix circuit programmable is so that be coupled in described a plurality of first sections any one and decoupling any one in described a plurality of second sections.
61. according to the memory device of claim 60, wherein, described a plurality of first sections respectively comprise the input/output signal path.
62. according to the memory device of claim 60, wherein, described route matrix also comprises:
At least one anti-fuse;
Be coupled to the programmed circuit of described anti-fuse;
Be coupled to the reading circuit of described at least one anti-fuse; And
Be coupling between described a plurality of first section and described a plurality of second section and be coupled at least one switch of described reading circuit effectively.
63. memory device according to claim 62, wherein, described reading circuit is exported at least one switch controlling signal, the programming state of described at least one anti-fuse is encoded, and described at least one switch is controlled by described at least one control signal effectively.
64. according to the memory device of claim 63, wherein, described switch matrix also comprises decoding logic, so that control described at least one switch with described at least one control signal.
65. a memory device die stacks, it comprises:
First semiconductor element, it has:
First logical circuit, the first memory controller that it comprises first memory cell array, is coupled to first address decoder of described first memory cell array and is coupled to described first memory cell array;
A plurality of first tube core contact solder joints;
Described first logical circuit is coupled to a plurality of first tube core signal paths of described a plurality of first tube core contact solder joints; And
Be coupling at least one described a plurality of first tube core signal path and contact the first via between the solder joint with at least one described a plurality of first tube core by matrix circuit, the described first via is able to programme by matrix circuit, so as will to be coupled to described route matrix any one described a plurality of first tube core signal path Route Selection be determined to and be coupled in the described first via by the described a plurality of first tube cores contact solder joints of any one of matrix circuit; And
Second semiconductor element, it has:
Second logical circuit, the second memory controller that it comprises second memory cell array, is coupled to second address decoder of described second memory cell array and is coupled to described second memory cell array;
A plurality of second tube core contact solder joints; And
A plurality of second tube core signal paths, each described a plurality of second tube core signal paths are coupled to the described second tube core logical circuit with the selection contact solder joint of described a plurality of second tube core contact solder joints, wherein, described first and second semiconductor elements are carried on the back the back of the body each other, and each described a plurality of first tube core contact solder joints are coupled to the relevant contact solder joint of described a plurality of second tube core contact solder joints.
66. a memory device chip-stack, it comprises:
First semiconductor chip, it has:
First logical circuit, the first memory controller that it comprises first memory cell array, is coupled to first address decoder of described first memory cell array and is coupled to described first memory cell array;
A plurality of first chip contact pins;
Described first logical circuit is coupled to a plurality of first chip signal paths of described a plurality of first chip contact pins; And
Be coupling at least one described a plurality of first chip signal path and contact the first via between the pin with at least one described a plurality of first chip by matrix circuit, the described first via is able to programme by matrix circuit, so as will to be coupled to described route matrix any one described a plurality of first chip signal path Route Selection be determined to and be coupled in the described first via by the described a plurality of first chips contact pins of any one of matrix circuit; And
Second semiconductor chip, it has:
Second logical circuit, the second memory controller that it comprises second memory cell array, is coupled to second address decoder of described second memory cell array and is coupled to described second memory cell array;
A plurality of second chip contact pins; And
A plurality of second chip signal paths, described second chip logic circuit is coupled to the selection contact pin of described a plurality of second chip contact pins in each described a plurality of second chip signal paths, wherein, described first and second semiconductor chips are carried on the back the back of the body each other, and each described a plurality of first chip contact pins are coupled to the relevant contact pin of described a plurality of second chip contact pins.
67. according to the memory device chip-stack of claim 66, wherein:
The first storage chip packaging part has:
First logical circuit, the first memory controller that it comprises first memory cell array, is coupled to first address decoder of described first memory cell array and is coupled to described first memory cell array;
Be coupled to a plurality of first chip contact pins of the described first storage chip packaging part;
Respectively be coupling in described first logical circuit and contact a plurality of first chip signal paths between the selection pin of pin with described a plurality of first chips;
Be coupled to the first chip select signal path of described first logical circuit;
Be coupling in the described first chip select signal path and at least two described a plurality of route matrix circuit able to programme that contact between the pin, it is programmed, so that the route in the described first chip select signal path is determined to the selection pin of described at least two described a plurality of contact pins of the contact pin of stipulating that first chip is not used; And
The second storage chip packaging part has:
Second logical circuit, the second memory controller that it comprises second memory cell array, is coupled to second address decoder of described second memory cell array and is coupled to described second memory cell array;
Be coupled to a plurality of second chip contact pins of the described second storage chip packaging part, comprise the contact pin that second chip is not used;
A plurality of second chip signal paths, it comprises that respectively being coupling in described second logical circuit contacts the second chip select signal path between the selection pin of pin with described a plurality of second chips, wherein, it is folded that the described first and second storage chip packaging parts are carried on the back backing layer, and each described a plurality of first chip contact pins are coupled to the relevant contact pin of described a plurality of second chip contact pins, cause the described first chip select signal path to be terminated to described second logical circuit, and the described second chip select signal path is terminated to described first logical circuit.
68. memory chip lamination according to claim 67, wherein, the described first chip select signal path is coupled to the contact pin that described second chip is not used, and the described second chip select signal path is coupled to the contact pin that described first chip is not used.
69. according to the memory chip lamination of claim 67, wherein, described route matrix comprises and places described a plurality of first chips of the described first chip select signal path and at least one to contact at least one anti-fuse between the pin.
70. according to the memory chip lamination of claim 67, wherein, described route matrix also comprises:
At least one anti-fuse;
Be coupled to the programmed circuit of described anti-fuse;
Be coupled to the reading circuit of described at least one anti-fuse; And
Be coupling in the described first chip select signal path and contact at least one switch that is coupled to described reading circuit between the pin and effectively with described at least two described a plurality of first chips.
71. a memory chip lamination, it comprises:
The first memory chip package, it has:
First logical circuit, the first memory controller that it comprises first memory cell array, is coupled to first address decoder of described first memory cell array and is coupled to described first memory cell array;
Be coupled to a plurality of first chip contact pins of described first memory chip package;
Be coupled to a plurality of first chip input/output signal paths of described first logical circuit;
Be coupling in described a plurality of first chip I/O path and described a plurality of route matrix circuit able to programme that contact between the pin, it is programmed, so that the route in each described a plurality of first chip input/output signal paths is determined to the selection pin of described a plurality of contact pins of the contact pin of stipulating that first chip is not used; And
The second memory chip package, it has:
Second logical circuit, the second memory controller that it comprises second memory cell array, is coupled to second address decoder of described second memory cell array and is coupled to described second memory cell array;
Be coupled to a plurality of second chip contact pins of the described second storage chip packaging part, comprise the contact pin that a plurality of second chips are not used;
A plurality of second chip input/output signal paths, respectively being coupling in described second logical circuit contacts between the selection pin of pin with described a plurality of second chips, wherein, it is folded that the described first and second memory chip package parts are carried on the back backing layer, and each described a plurality of first chip contact pins are coupled to the relevant contact pin of described a plurality of second chip contact pins, cause the described first chip input/output signal path to be terminated to described second logical circuit, and the described second chip input/output signal path is terminated to described first logical circuit.
72. memory chip lamination according to claim 71, wherein, the described first chip input/output signal path is coupled to the selection pin of the contact pin that described second chip is not used, and the described second chip input/output signal path is coupled to the selection pin of the contact pin that described first chip is not used.
73. according to the memory chip lamination of claim 71, wherein, described route matrix comprises and places at least one described first chip input/output signal path to contact at least one anti-fuse between the pin with at least one described a plurality of first chip.
74. according to the memory chip lamination of claim 71, wherein, described route matrix also comprises:
At least one anti-fuse;
Be coupled to the programmed circuit of described anti-fuse;
Be coupled to the reading circuit of described at least one anti-fuse; And
Be coupling in the described first chip input/output signal path and contact at least one switch that is coupled to described reading circuit between the pin and effectively with described a plurality of first chips.
75. one kind contacts solder joint with signal from first with anti-array of fuses and changes the method that is routed to the second contact solder joint, it comprises:
Anti-fuse with first state and second state is provided;
Provide reading circuit, so that test described first and second states of described anti-fuse;
Between the first contact solder joint and signal path, provide switch, described switch has on-state and off-state, in on-state, described signal path is coupled to the described first contact solder joint, in off-state, described signal path is terminated to the described first contact solder joint, and the disconnection of described switch and on-state are determined by described reading circuit; And
Described anti-fuse programming is arrived one of described first and second states.
76. a method of making the chip stacked device, it comprises the following step:
Provide and have first chip that a plurality of contact pins and pin able to programme change routing circuit;
Provide and have a plurality of contact pins and second chip that contacts pin that is not used;
The described first chip pin is changed routing circuit programme, be routed to predetermined contact pin so that internal signal changed; And
Described first and second chips are carried on the back carry on the back together, described a plurality of contacts of described first chip are electrically coupled to described a plurality of contacts of described second chip, cause the described predetermined contact pin of described first chip to aim at and be coupled to the described contact pin that is not used of described second chip.
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US20020130687A1 (en) 2002-09-19
US6633183B2 (en) 2003-10-14
CN1316744C (en) 2007-05-16
US20020149391A1 (en) 2002-10-17
US6633180B2 (en) 2003-10-14
EP2285002A3 (en) 2014-07-09
EP2285002A2 (en) 2011-02-16
EP1386398A2 (en) 2004-02-04
WO2002075926A3 (en) 2003-11-06
KR100649911B1 (en) 2006-11-27
US20030012071A1 (en) 2003-01-16
US6417695B1 (en) 2002-07-09
EP2088675A2 (en) 2009-08-12
JP4128081B2 (en) 2008-07-30
EP1386398B1 (en) 2015-12-30
KR20030093243A (en) 2003-12-06
JP2004535661A (en) 2004-11-25
EP2088675A3 (en) 2014-07-09
AU2002252359A1 (en) 2002-10-03
WO2002075926B1 (en) 2003-12-18
WO2002075926A2 (en) 2002-09-26

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