CN1517676A - Decode correction method and its circuit for coarce code of absolute matrix encoder - Google Patents

Decode correction method and its circuit for coarce code of absolute matrix encoder Download PDF

Info

Publication number
CN1517676A
CN1517676A CNA031109098A CN03110909A CN1517676A CN 1517676 A CN1517676 A CN 1517676A CN A031109098 A CNA031109098 A CN A031109098A CN 03110909 A CN03110909 A CN 03110909A CN 1517676 A CN1517676 A CN 1517676A
Authority
CN
China
Prior art keywords
memory under
under program
channel signal
eprom
rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA031109098A
Other languages
Chinese (zh)
Other versions
CN1275019C (en
Inventor
万秋华
龙科慧
佘荣红
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changchun Institute of Optics Fine Mechanics and Physics of CAS
Original Assignee
Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changchun Institute of Optics Fine Mechanics and Physics of CAS filed Critical Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority to CN 03110909 priority Critical patent/CN1275019C/en
Publication of CN1517676A publication Critical patent/CN1517676A/en
Application granted granted Critical
Publication of CN1275019C publication Critical patent/CN1275019C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

A decode correcting method and circuit for the corase codes of absolute matrix encoder is disclosed. Its technical scheme includes such steps as writing the designed decode correcting data on an erasable program memory chip, choosing the corase code matrix's code track signal, fine code track signal and correcting code track signal, which are output from the absolute matrix encoder, amplifying and shaping them, inputting them to the address input pins of said erasable program memory chip, and determining the match of the output pins on said chip with corrected binary codes.

Description

Method and circuit thereof that the thick sign indicating number decoding of a kind of absolute matrix scrambler is proofreaied and correct
Technical field: the invention belongs in the photoelectricity test technical field, especially relate to method and circuit thereof that the thick sign indicating number decoding of a kind of absolute matrix scrambler is proofreaied and correct.
Technical background: optical electric axial angle encoder is representative angular displacement sensor, be widely used in multiple occasion, its thick sign indicating number angle measurement data are the thick sign indicating number photosignals by scrambler output, obtain after decoding is proofreaied and correct after handling through the amplification shaping again.
The process that the thick sign indicating number decoding of generalized case matrix encoder is proofreaied and correct is, earlier matrix coder (thick sign indicating number) is translated into cyclic binary code (also claiming lattice snow sign indicating number), then cyclic binary code, again according to smart code channel, the relation of proofreading and correct code channel and thick code channel, judge the position that thick sign indicating number will be proofreaied and correct, the correction that adds deduct, thus realize that with smart sign indicating number be the treatment for correcting of benchmark to thick sign indicating number.
Before the present invention, the prior art the most approaching with the present invention, two kinds of situations are arranged usually, and a kind of is the thick sign indicating number decoding of absolute matrix scrambler correction hardware treatment circuit (" optical-mechanical " 1985 the 5th phase P65-70 " Matrix Photoelectric Rotary Encoder " Cao Zhenfu).As shown in Figure 1: select a circuit 2, alternative circuit 3, NOR gate circuit 4, full adder circuit 5 to form by odd even decision circuitry 1, four.
This kind hardware handles circuit, the components and parts of use are many, bulky, Heavy Weight, take up room very greatly, influence the main body instrument layout, also lack general reliability simultaneously.In order to overcome this shortcoming, people have developed the thick sign indicating number decoding of another kind of absolute matrix scrambler again and have proofreaied and correct single-chip microcomputer treatment circuit (the Matrix Photoelectric Rotary Encoder single-chip microcomputer treatment circuit that Chinese Academy of Sciences's Changchun ray machine is developed).As shown in Figure 2: form by latch 6, latch 7, scm managing system 8, I/D interface circuit 9.This single-chip microcomputer process software circuit volume is little, the reliability height, but the time of data processing is long, inefficiency, more than the thick sign indicating number of two kinds of absolute matrix scramblers decoding correcting circuits all have certain shortcoming and problem.
Summary of the invention: in order to overcome shortcoming and the problem that above-mentioned two kinds of circuit exist, the objective of the invention is to set up a kind of new method that realizes that thick sign indicating number decoding is proofreaied and correct to the absolute matrix scrambler, by the circuit that this method realizes, volume is little, in light weight, the volume that takes up space is little, reliability is high, processing speed is fast, high efficiency.
The technical problem to be solved in the present invention is: set up the method that the thick sign indicating number decoding of a kind of absolute matrix scrambler is proofreaied and correct.Produce the thick sign indicating number of a kind of absolute matrix scrambler decoding correcting circuit by this method.
The technical scheme of technical solution problem such as Fig. 3, Fig. 4, shown in Figure 5: at first adopt a slice can wipe memory under program (E 2ROM or EPROM) 12, by computing machine 10 and programmer 11 toward wiping the decoding correction data that injection designs in advance in the memory under program 12:
a 1＝A 1??????????????????????????????????????????????b 1＝a 1
a 2＝A 2??????????????????????????????????????????????b 2＝x 1a 1＝a 1a 2
a 3＝B 1A 1+B 2A 1???????????????????????????????????b 3＝x 2a 3＝a 1a 2a 3
a 4＝B 1A 1+B 2A 1???????????????????????????????????b 4＝x 3a 4＝a 1a 2a 3a 4
a 5＝C 4A 1A 2+C 3A 1A 2+C 2A 1A 2+C 1A 1A 2??????b 5＝x 4a 5＝a 1a 2......a 5
a 5＝C 3A 1A 2+C 2A 1A 2+C 1A 1A 2+C 4A 1A 2??????b 6＝x 5a 6＝a 1a 2......a 6
a 7＝C 2A 1A 2+C 1A 1A 2+C 4A 1A 2+C 3A 1A 2??????b 7＝x 6a 7＝a 1a 2......a 7
a 8＝C 1A 1A 2+C 4A 1A 2+C 3A 1A 2+C 2A 1A 2??????b 8＝x 7a 8＝a 1a 2......a 8
??G 1???G 2???D 1???b 8 ????x 1??x 2??x 3??x 4??x 5??x 6??x 7??x 8
??0????0????0????0 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??0????0????0????1 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8 ????+1
??0????0????1????0 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8 ????+1
??0????0????1????1 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??0????1????0????0 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8 ????-1
??0????1????0????1 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??0????1????1????0 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??0????1????1????1 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8 ????-1
??1????0????0????0 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??1????0????0????1 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??1????0????1????0 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??1????0????1????1 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??1????1????0????0 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??1????1????0????1 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??1????1????1????0 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
??1????1????1????1 ????b 1??b 2??b 3??b 4??b 5??b 6??b 7??b 8
A in the decoding correction data 1a 2a 3a 4a 5a 6a 7a 8Be cyclic binary code, A wherein 1A 2, B 1B 2, C 1C 2C 3C 4Be thick sign indicating number matrix code channel signal; b 1b 2b 3b 4b 5b 6b 7b 8Be natural binary code, X wherein 1X 2X 3X 4X 5X 6X 7X 8Be the natural binary code after the treatment for correcting, G 1G 2Be smart code channel signal, D 1For proofreading and correct the code channel signal; Next is the C that selects absolute matrix scrambler (13) output 4C 3C 2C 1B 2B 1A 2A 1Thick sign indicating number matrix code channel signal, G 2G 1Be smart code channel signal, D 1For proofread and correct the code channel signal after by amplification shaping device (14) lead-in wire and can wipe memory under program E 2The address input lead pin A of ROM or EPROM (12) 0A 1A 2A nThe selection that is complementary; Determine to wipe the output lead pin D of memory under program 12 more as required 0D 1D 2D 7With the binary code X after the extraction treatment for correcting 8X 7X 2X 1Coupling.
According to the thick sign indicating number decoding of the absolute matrix scrambler of above-mentioned foundation bearing calibration, the thick sign indicating number of the absolute matrix scrambler of formation decoding correcting circuit as shown in Figure 5: can wipe memory under program (E in a slice 2ROM or EPROM) in 12, storage has the decoding correction data that designs in advance; A 1A 2, B 1B 2, C 1C 2C 3C 4Be thick sign indicating number matrix code channel signal, X 1X 2X nBe the natural binary code after proofreading and correct, G 1G 2Be smart code channel signal, D 1For proofreading and correct the code channel signal, be provided with address input lead pin A in the left side that can wipe memory under program 12 0A 1A 2A nAnd with the scrambler of its coupling output code channel signal lead C 4C 3C 2C 1B 2B 1A 2A 1G 2G 1The right side is provided with can wipe memory under program function output terminal pin D 0D 1D 2D nWith with the decoding correction data of its coupling lead-in wire X nX 2X 1Can wipe memory under program 12 left sides and also have sheet to select terminal pin OE and read and allow terminal pin OE to be connected with the power supply address, the right side also has power supply to draw a pin V PpAnd programming terminal pin PGM is connected with phone.
Good effect of the present invention: convenient and simple easy row, the circuit volume is little, in light weight, reliability is high, processing speed is fast, high efficiency.
Description of drawings: Fig. 1 is the thick sign indicating number decoding of a prior art absolute matrix scrambler correction hardware treatment circuit structural representation, Fig. 2 is that single-chip microcomputer treatment circuit structural representation is proofreaied and correct in the thick sign indicating number decoding of prior art absolute matrix scrambler, Fig. 3 injects the synoptic diagram of deciphering the correction data method by computing machine and programmer toward wiping in the inventive method in the memory under program, Fig. 4 is the thick sign indicating number of scrambler output in the inventive method, smart sign indicating number, proofread and correct the lead-in wire of code channel signal after amplifying shaping and the synoptic diagram that can wipe memory under program address input lead pin coupling, Fig. 5 is the thick sign indicating number of an absolute matrix scrambler of the present invention decoding correcting circuit synoptic diagram.
Embodiment: Fig. 3 is pressed in method invention of the present invention and method program shown in Figure 4 is implemented, computing machine 10 among Fig. 3 adopts PC486 or PC586 computing machine, programmer 11 adopts the RF1800 programmer, the scrambler 13 that memory under program 12 adopts 27C64 can wipe among memory under program, Fig. 4 adopts MTX65 or MTX40 absolute matrix scrambler, amplify shaping 14 and adopt LM124 amplifier or LM139 comparer, memory under program 12 adopts 27C64 can wipe memory under program.
Circuit invention among the present invention is implemented by structure shown in Figure 5, injects the decoding correction data by mode shown in Figure 3, implements to wipe memory under program by mode shown in Figure 4 and is connected with scrambler.

Claims (2)

1, the method for the thick sign indicating number decoding of a kind of absolute matrix scrambler correction is characterized in that at first adopting a slice can wipe memory under program E 2ROM or EPROM (12), by computing machine (10) and programmer (11) toward wiping memory under program E 2The decoding correction data of the decoding correction data table that injection designs in advance among ROM or the EPROM (12), a in the decoding correction data 1a 2a 3a 4a 5a 6a 7a 8Be cyclic binary code, A wherein 1A 2, B 1B 2, C 1C 2C 3C 4Be thick sign indicating number matrix code channel signal; B 1B 2B 3B 4B 5B 6B 7B 8Be natural binary code, X wherein 1X 2X 3X 4X 5X 6X 7X 8Be the natural binary code after the treatment for correcting, G 1G 2Be smart code channel signal, D 1For proofreading and correct the code channel signal; Next is the C that selects absolute matrix scrambler (13) output 4C 3C 2C 1B 2B 1A 2A 1Thick sign indicating number matrix code channel signal, G 2G 1Be smart code channel signal, D 1For proofread and correct the code channel signal after by amplification shaping device (14) lead-in wire and can wipe memory under program E 2The coupling of the address input lead pin of ROM or EPROM (12); Determine as required again to wipe memory under program E 2ROM or EPROM (12) output lead pin D 0D 1D 2D 3D 4D 5D 6D 7With the binary code X after the extraction treatment for correcting 8X 7X 6X 5X 4X 3X 2X 1Coupling,
2, the thick sign indicating number of a kind of absolute matrix scrambler decoding correcting circuit is characterized in that can wiping memory under program E in a slice 2In ROM or the EPROM (12), storage has the decoding correction data that designs in advance; Can wipe memory under program E 2The left side of ROM or EPROM (12) is provided with address input lead pin A 0A 1A 2A nAnd with the scrambler of its coupling output code channel signal lead C 4C 3C 2C 1B 2B 1A 2A 1G 2G 1The right side is provided with can wipe memory under program function output terminal pin D 0D 1D 2D nWith with the decoding correction data of its coupling lead-in wire X nX 2X 1Can wipe memory under program E 2Also have sheet to select terminal pin OE on the left of ROM or the EPROM (12) and read to allow terminal pin OE to be connected with the power supply address, the right side also has power supply to draw a pin V PpAnd programming terminal pin PGM is connected with phone.
CN 03110909 2003-01-17 2003-01-17 Decode correction method and its circuit for coarce code of absolute matrix encoder Expired - Fee Related CN1275019C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 03110909 CN1275019C (en) 2003-01-17 2003-01-17 Decode correction method and its circuit for coarce code of absolute matrix encoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 03110909 CN1275019C (en) 2003-01-17 2003-01-17 Decode correction method and its circuit for coarce code of absolute matrix encoder

Publications (2)

Publication Number Publication Date
CN1517676A true CN1517676A (en) 2004-08-04
CN1275019C CN1275019C (en) 2006-09-13

Family

ID=34283300

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 03110909 Expired - Fee Related CN1275019C (en) 2003-01-17 2003-01-17 Decode correction method and its circuit for coarce code of absolute matrix encoder

Country Status (1)

Country Link
CN (1) CN1275019C (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101846529A (en) * 2010-05-20 2010-09-29 哈尔滨工业大学 Decoding circuit of spaceborne absolute type photoelectric axial angle encoder based on DSP (Digital Signal processor)
CN104596550A (en) * 2015-01-28 2015-05-06 哈尔滨工业大学 Coarse code decoding circuit of satellite-bone absolute type photoelectric encoder and adaptive sampling method implemented thereby
CN108981765A (en) * 2018-07-27 2018-12-11 上海航天控制技术研究所 A kind of absolute optical encoder Measurement channel Method of fault-tolerant design

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101846529A (en) * 2010-05-20 2010-09-29 哈尔滨工业大学 Decoding circuit of spaceborne absolute type photoelectric axial angle encoder based on DSP (Digital Signal processor)
CN104596550A (en) * 2015-01-28 2015-05-06 哈尔滨工业大学 Coarse code decoding circuit of satellite-bone absolute type photoelectric encoder and adaptive sampling method implemented thereby
CN104596550B (en) * 2015-01-28 2017-05-03 哈尔滨工业大学 Coarse code decoding circuit of satellite-bone absolute type photoelectric encoder and adaptive sampling method implemented thereby
CN108981765A (en) * 2018-07-27 2018-12-11 上海航天控制技术研究所 A kind of absolute optical encoder Measurement channel Method of fault-tolerant design

Also Published As

Publication number Publication date
CN1275019C (en) 2006-09-13

Similar Documents

Publication Publication Date Title
CN1241329C (en) Method and arrangement for decoding convolutionally encoded codeword
US6961921B2 (en) Pipeline architecture for maximum a posteriori (MAP) decoders
CN101162449A (en) NAND FLASH controller and data interactive method with NAND FLASH chip
CN102880567B (en) data read-write system
CN1728563A (en) Turbo code translator and Turbo interpretation method
CN1275019C (en) Decode correction method and its circuit for coarce code of absolute matrix encoder
Wong et al. Error detection in arithmetic coding with artificial markers
CN104243095A (en) Code word type blind identification method for convolutional code and linear block code
CN109634578B (en) Program generation method based on text description
CN103746702B (en) Lossless data compression method and lossless data compression device
CN104573600B (en) A kind of recognition methods based on static wheeled coding
CN100559509C (en) Check code wiring method and writing station thereof in the BCH error correcting technique
CN101534130B (en) Data interlacing method and device thereof, data deinterlacing method and device and encoder thereof
CN2735301Y (en) Programmable logic array based absolute photoelectric shaft encoder decoding circuit
CN116150209A (en) Report computing system, method, electronic equipment and storage medium
CN100570754C (en) Error correction information disposal route and treating apparatus thereof in the BCH error correcting technique
CN114678074A (en) Hidden addressing DNA storage coding design method
KR102041874B1 (en) Memory controller changing partial data in memory device and method for changing partial data thereof
CN102571107A (en) System and method for decoding high-speed parallel Turbo codes in LTE (Long Term Evolution) system
CN1455565A (en) Parallel Turbo coding-decoding method based on block processing for error control of digital communication
CN201036008Y (en) Check code writing device in BCH error correction technique
KR102002044B1 (en) Memory controller and memroy system including ecc encoder for generating new parity
CN1176541C (en) Method for enhancing product code decoding speed and decoding device
CN201134270Y (en) NAND FLASH controller
CN201927052U (en) Bar code image correcting device based on track codes

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee