CN1507590A - External connection device, host device and data communication system - Google Patents

External connection device, host device and data communication system Download PDF

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Publication number
CN1507590A
CN1507590A CNA038001640A CN03800164A CN1507590A CN 1507590 A CN1507590 A CN 1507590A CN A038001640 A CNA038001640 A CN A038001640A CN 03800164 A CN03800164 A CN 03800164A CN 1507590 A CN1507590 A CN 1507590A
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mentioned
main equipment
data
external connection
invalid
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CN1297915C (en
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坂东秀明
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Sony Corp
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Sony Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Table Equipment (AREA)

Abstract

This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card ( 1 ) and a host device ( 2 ) are connected with each other in accordance with a six-wire-system half-duplex protocol using four-bit parallel signals, a bus state signal, and a clock signal. When the state of the bus state signal is a state of accepting interruption, the memory card ( 1 ) sends an interrupt signal (INT) to four-bit parallel buses. Different elements of interruption are allocated to the respective bits of the four-bit parallel signals. That is, the bit at which the INT signal is sent varies depending on the content of interruption.

Description

External connection apparatus, main equipment and data communication system
Technical field
The present invention relates to the main equipment that external connection apparatus and this external connection apparatus connected of IC storage arrangement of being connected with signal conditioning packages such as computing machines etc., relate in particular to the data communication system that has adopted these external connection apparatus and main equipment.
The application is to serve as that right of priority is advocated on the basis in Japan in the Japanese patent application No. 2002-045252 of application on February 21st, 2002, and this application is quoted by being referenced cause the application.
Background technology
In the past, as the external memory media of main equipments such as information portable terminal device, desktop computer, notebook computer, portable telephone, audio devices, electric household appliance, employing can be to the built-in card type movable small IC storage arrangement of semiconductor memory of these equipment loading, unloading.
Nonvolatile semiconductor memories (IC storer) such as the general onboard flash memory storer of sort memory device are deposited various numerical datas such as Still image data, motion image data, speech data, music data in this semiconductor memory.This IC storage arrangement works as the external memory media such as main equipments such as information portable terminal device, desktop computer, notebook computer, portable telephone, audio devices, electric household appliances.
In this IC storage arrangement, the interface by regulation comes control action from the main equipment side.In general, the IC storage arrangement is passed on processing instruction, move control from the main equipment side.
The access speed of flash memories that is used for the IC storage arrangement is lower.Thereby pass on operation for shortening main equipment and the data between the IC storage arrangement, stipulate that it is effective coming the interrupt request of notifier processes end etc. from IC storage arrangement side.
Summary of the invention
The object of the present invention is to provide the main equipment that external connection apparatus and this external connection apparatus connected of the problem points that exists in a kind of IC storage arrangement of eliminating in the past, especially adopted the data communication system of these external connection apparatus and main equipment.
Another object of the present invention provides a kind ofly can supply with look-at-me to main equipment effectively from external connection apparatus, the data that shorten main equipment and external connection apparatus are passed on the external connection apparatus and the main equipment in processing time, especially a kind of data communication system that has adopted these external connection apparatus and main equipment.
The external connection apparatus involved in the present invention that proposes for achieving the above object is a kind of external connection apparatus that is connected with main equipment, possesses data communication units, its and main equipment between transmit data by data bus two-way communication; The bus state signal receiving element, it receives the bus state signal of the state of expression data bus from above-mentioned main equipment; Controller, it carries out the action control of this equipment according to transmitting the action directive that comprises in the data, data communication units becomes at the state of bus state signal accepts from this equipment during to the state of the interruption of main equipment, and the information of expression based on the interruption factor content that action directive took place that provides to controller from main equipment is sent to above-mentioned main equipment by data bus.
In the external connection apparatus that the present invention relates to, become at the state of bus state signal and to accept from this equipment during to the state of the interruption of main equipment, with expression based on the information of the interruption factor content that action directive took place that provides to controller from main equipment as look-at-me, send to main equipment by data bus.
Main equipment involved in the present invention is the main equipment that a kind of external connection apparatus connects, and possesses data communication units, its and external connection apparatus between transmit data by data bus two-way communication; The bus state signal transmitting element, its bus state signal that will represent the state of data bus sends to external connection apparatus; Controller, its steering order that will carry out the action control of external connection apparatus covers the transmission data and issues, data communication units becomes at the state of bus state signal accepts from external connection apparatus during to the state of the interruption of this equipment, receives the information of expression based on the interruption factor content that action directive took place that provides to above-mentioned external connection apparatus from this equipment by data bus from external connection apparatus.
In the main equipment that the present invention relates to, become at the state of bus state signal and to accept from external connection apparatus during to the state of the interruption of this equipment, with expression based on the information of the interruption factor content that action directive took place that provides to external connection apparatus from this equipment as look-at-me, received from external connection apparatus by data bus.
Other purpose of the present invention and the concrete strong point that is obtained by the present invention can further bright dawns according to following the explanation with reference to the illustrated embodiment of accompanying drawing.
Description of drawings
Fig. 1 is that expression has been used storage card of the present invention and adopted the oblique view of the main equipment of this storage card.
Fig. 2 is an oblique view of watching storage card from face side.
Fig. 3 is an oblique view of watching storage card from rear side.
Fig. 4 is the block scheme of the insider architecture of expression storage card.
Fig. 5 is the structural drawing that is used to carry out the interface function that the data between storage card and the main equipment transmit.
Fig. 6 is used for accompanying drawing that the signal that passes on is described between storage card and main equipment.
Fig. 7 is the accompanying drawing that is used to illustrate the Content of Communication under each state.
Fig. 8 is the timing diagram that writes parallel data, bus state and clock when dividing into groups to pass on.
Fig. 9 is a timing diagram of reading parallel data, bus state and clock when dividing into groups to pass on.
Figure 10 be write grouping and read grouping when passing on engaged signal and the timing diagram of ready signal.
Figure 11 is the accompanying drawing that expression constitutes the internal register of status register group.
Figure 12 is the accompanying drawing of the position content in the expression INT register.
Figure 13 is the accompanying drawing of expression corresponding to the operating state of the storage card of each place value in the INT register.
Figure 14 is the accompanying drawing that expression constitutes the internal register of parameter register group.
The accompanying drawing of the transfer of data when Figure 15 is expression SET_CMD_TPC.
The accompanying drawing of the transfer of data when Figure 16 is expression EX_SET_CMD_TPC.
Figure 17 is the accompanying drawing of expression steering order one example.
Embodiment
Below, the example of enumerating the data processing equipment that the present invention has been applied to small IC storage arrangement movably and this small IC storage arrangement is used as external memory media describes.
In addition in the following description, the small IC storage arrangement is called storage card, the data processing equipment that has connected this storage card is called main equipment.
At first, with reference to Fig. 1, the summary of having used main equipment of the present invention and the storage card that is connected with this main equipment is explained.
The storage card 1 that the present invention relates to has nonvolatile semiconductor memory (IC storer) in inside, can deposit various numerical datas such as Still image data, motion image data, speech data, music data.This storage card 1 works as the external memory media such as main equipments 2 such as information portable terminal device, desktop computer, notebook computer, portable telephone, audio devices, electric household appliances.
Storage card 1 takes off under mouthfuls 3 the state and uses having inserted be arranged at main equipment 2 slotting as shown in Figure 1.The user can freely carry out taking off mouthfuls 3 insertion and extracting at storage card 1 slotting.Therefore, also the storage card 1 that has inserted certain main equipment can be extracted, insert other main equipment.That is, this storage card 1 can be used for the exchanges data between the different main equipments.
Storage card 1 and main equipment 2 pass on the parallel interface of the parallel agreement of 6 line formula half-duplexs of 4 bit parallel data, clock signal and these 6 signals of bus state signal and carry out passing on of data by having adopted.
The storage card 1 that the present invention relates to as shown in Figure 2, form a kind of be roughly rectangular laminar, with the length L of length direction 1Be made as 50mm, with width W 1Be made as 21.45mm, with thickness D 1Being made as 2.8mm forms.With a face of storage card 1 as surperficial 1a, with another face as back side 1b.Distolateral back side 1b side at storage card 1 length direction as shown in Figure 3, is provided with 10 plane electrodes, and promptly the splicing ear group 4.Each electrode that constitutes splicing ear group 4 is arranged in parallel on the Width of storage card 1.Between each, be provided with the partition 5 that stands vertically from back side 1b at electrode and electrode.Each partition 5 is used to prevent that the splicing ear that is connected in each electrode from contacting with other electrode.At the central portion of the end side of storage card 1 back side 1b, as shown in Figure 3, be provided with the slide switch 6 that is used to prevent the mistake deletion.
Be equipped with in the main equipment 2 of said memory card 1, be provided with and be used for inserting take off storage card 1 slotting and take off mouthfuls 3.Insert and to take off mouthfuls 3 as shown in Figure 1, in the front face side of main equipment 2 as width W corresponding to storage card 1 1And thickness D 1Opening and form.Take off the splicing ear of mouthfuls 3 storage cards 1 that insert main equipments 2 by main equipment 2 sides and be connected to each electrode that constitutes splicing ear group 4 by inserting, can realize maintenance, in case anti-avulsion falls to main equipment 2.The splicing ear of main equipment 2 sides is answered with the electrode pair that constitutes the splicing ear group 4 that is arranged at the storage card 1 that is loaded in addition, has 10 contacts.
The storage card 1 that the present invention relates to will be provided with the distolateral as insertion end of splicing ear group 4, as direction of insertion, take off mouthful 3 pack main equipments 2 by inserting with arrow X1 direction among Fig. 2.The storage card 1 that is loaded into main equipment 2 after each contact of the splicing ear of each electrode that constitutes splicing ear group 4 and main equipment 2 sides is connected, but just become the state of receiving and transmitting signal.
Next, with reference to Fig. 4, the inner structure of the storage card 1 that the present invention relates to is explained.
The storage card 1 that the present invention relates to possesses parallel interface (I/F) 12, register circuit 13, data buffer circuit 14, ECC circuit 15, register I/F controller 16, nonvolatile semiconductor memory 17, oscillation control circuit 18 as shown in Figure 4.
Parallel I/F circuit 12 is to adopt 6 line formula half-duplex parallel mode data transport protocols, and main equipment 2 between carry out the circuit that data are passed on.
Register circuit 13 is storages such as the internal state in the action directive at memory I/F controller 16 that passes on from main equipment (following this action directive is called steering order), the storage card 1, the circuit of file control information etc. when carrying out steering order in necessary a plurality of parameters, the nonvolatile semiconductor memory 17.This register circuit 13 is by these two visits from main equipment 2 and memory I/F controller 16.In addition, main equipment 2 utilizes the transport protocol instruction of stipulating on the data transport protocol of this storage card (to call TPC (TransferProtocol Command) in the following text.), register circuit 13 is conducted interviews.That is, under the occasion that steering order that main equipment 2 is deposited in to register circuit 13 and various parameter write and read, adopt TPC to carry out.
Data buffer circuit 14 is to the data that write nonvolatile semiconductor memory 17 and the memory circuitry temporarily preserved from the data that nonvolatile semiconductor memory 17 is read.Promptly, writing under the occasion of data to nonvolatile semiconductor memory 17 from main equipment 2, writing object data is passed on to data buffer circuit 14 from main equipment 2 according to the data transport protocol, then, memory I/F controller 16 writes nonvolatile semiconductor memory 17 with the object data of depositing in the data buffer circuit 14 that writes.From nonvolatile semiconductor memory 17 under the occasion of main equipment 2 sense datas, memory I/F controller 16 will be read object data from nonvolatile semiconductor memory 17 and read, temporarily deposit data buffer circuit 14, then, this is read object data and is transferred to main equipment 2 according to the data transport protocol from data buffer circuit 14.
In addition, data buffer circuit 14 has the data capacity of the predetermined data unit of writing (such as, 512 bytes identical with the page size of flash memories).Main equipment 2 utilizes TPC in addition, and data buffer circuits 14 is conducted interviews.That is, under the occasion that the data that main equipment 2 is deposited in to data buffer circuits 14 write and read, adopt TPC to carry out.
15 pairs in ECC circuit writes the data additional error correcting code (ECC) of nonvolatile semiconductor memory 17.In addition, ECC circuit 15 carries out handling at the error correction of these data of reading based on the bug patch code that is additional to the data of reading from nonvolatile semiconductor memory 17.Such as, in the bug patch code, to additional 3 bytes of 512 byte data units.
Memory I/F controller 16 is according to the steering order of depositing in the register circuit 13, carries out renewal processing of the data of depositing in the control of other function of control, storage card 1 of data safety management of control, nonvolatile semiconductor memory 17 of the exchanges data between data buffer circuit 14 and the nonvolatile semiconductor memory 17 and the register circuit 13 etc.
Nonvolatile semiconductor memory 17 is a kind of such as nonvolatile semiconductor memories such as NAND type flash memories.The volume ratio of nonvolatile semiconductor memory 17 is as being 16M byte, 32M byte, 64M byte, 128M byte.The deleted block unit of nonvolatile semiconductor memory 17 is such as the 16K byte.The read-write unit is called page or leaf, and is identical with data buffer circuit 14, is 512 bytes.The Action clock that oscillation control circuit 18 takes place in this storage card 1.
Be provided with VSS terminal, VCC terminal, DATA0 terminal, DATA1 terminal, DATA2 terminal, DATA3 terminal, BS terminal, CLK terminal, INS terminal in the splicing ear of storage card 1.In addition, because 2 VSS terminals are set, thereby 10 splicing ears are set in storage card 1 altogether.Main equipment 2 sides also are provided with same splicing ear.
The VSS terminal is connected with VSS (0 volt of voltage of benchmark).This VSS terminal connects the ground wire of main equipment side and the ground wire of storage card side, makes main equipment consistent with 0 volt of reference potential of storage card.The supply voltage of VCC terminal (VCC) is supplied with from main equipment.
By the DATA0 terminal, the data-signal (DATA0) of lowest order is transfused to output in the 4 bit parallel data of passing between storage card 1 and main equipment 2.By the DATA1 terminal, the 2nd bit data signal (DATA1) that begins from low level in the 4 bit parallel data of passing between storage card 1 and main equipment 2 is transfused to output.By the DATA2 terminal, the 3rd bit data signal (DATA2) that begins from low level in the 4 bit parallel data of passing between storage card 1 and main equipment 2 is transfused to output.By the DATA3 terminal, the 4th bit data signal (DATA3) that begins from low level in the 4 bit parallel data of passing between storage card 1 and main equipment 2 is transfused to output.
By the BS terminal, bus state signal is imported to storage card from main equipment.By the CLK terminal, clock signal is imported from main frame 2.The INS terminal judges whether storage card inserts the insertion of jack/extract detection to be used to being used for main equipment 2.The INS terminal ground connection of storage card 1, the INS terminal of main equipment 2 by resistance by on draw.
Next, with reference to Fig. 5, the functional structure of the interface that the data that are used to carry out between storage card 1 and the main equipment 2 are transmitted is explained.
The interface function of main equipment 2 is made of file manager 31, TPC interface 32, parallel interface 33 as shown in Figure 5.The interface function of storage card 1 is made of parallel interface 33, register 35, data buffer 36, Memory Controller 37, storer 38 in addition.
File manager 31 carries out the management of the file deposited in the file deposited in the storage card 1 and other medium of main equipment on the operating system of main equipment.File manager 31 is to wait the function that realizes by the controller in the main equipment 2.
TPC interface 32 becomes the lower layer of file manager 31.TPC interface 32 is undertaken the register 35 in the storage card 1 and the visit of data buffer 36 by the data transport protocol of having stipulated the distinctive instruction of this interface (TPC:Transfer Protocol Command).This TPC interface 32 is to wait the function that realizes by the controller in the main equipment 2.
Parallel interface 33,34 becomes the lower layer of TPC interface 32, is the Physical layer of this interface system. Parallel interface 33,34 is according to passing on the data transport protocol of 4 bit parallel data, clock, these 6 signals of bus state signal, i.e. the parallel agreement of 6 line formula half-duplexs is carried out data and passed on.Parallel interface the 33, the 34th, the function that realizes by parallel interface 12.
Register 35 is deposited the address, the file control information when carrying out steering order in necessary a plurality of parameters, the storer of the data of visit the internal state, storer 38 of the steering order of passing on from main frame, storage card etc.Register 35 is the functions that realize on the register circuit 13 of storage card 1.
Data buffer 36 is the data that write of a subtend storer 38 and the buffer zone temporarily preserved from the data that storer 38 is read.Data buffer 36 is the functions that realize on the data buffer circuit 14 of storage card 1.
Memory Controller 37 is according to instruction of depositing in the register 35 and various information, carries out that data between data buffer 36 and the storer 38 are read, write, the controls such as renewal of various information in deletion and the register 35.Memory Controller 37 is the functions by the memory I on the main equipment 2/F controller 16 is realized.
Storer 38 is memory of data districts, by Memory Controller 37, is assumed to an independent model.Storer 38 is the functions that realized by the nonvolatile semiconductor memory on the storage card 1 17.
In the main equipment and storage card of above-mentioned formation, the data of depositing in other medium by file manager 31 management can be transferred to storer 38 by above-mentioned parallel interface 33,34.The data of depositing in the storer 38 can be transferred to other medium by the file management management by above-mentioned parallel interface 33,34 in addition.
Next, the storage card 1 that the present invention relates to and the data transport protocol between the main equipment 2 are explained.
Feature as the data transport protocol of storage card 1 and main equipment 2 has following several: define 4 bus states, what identification transmitted data passes on direction and attribute; Utilize TPC, conduct interviews from the register circuit 13 and the data buffer circuit 14 of 2 pairs of storage cards 1 of main equipment; Main equipment 2 utilizes steering order to carry out the action control of storage card 1; Utilize CRC (CyclicRedundancy Check codes) to carry out the error-detecting of transfer of data between storage card 1 and the main equipment 2; Regulation from storage card 1 to look-at-me (INT signal) of main equipment 2 etc.
Storage card 1 and main equipment 2 are connected by bus state signal (BS), 4 parallel data signals, these 6 signals of clock signal (SCLK) as shown in Figure 6.
Parallel data signal is the data-signal that passes between storage card 1 and main equipment 2.Parallel data signal transmits the parallel data (DATA[3:0]) of 4 bit wides, and pass on direction and the attribute of its parallel data (DATA[3:0]) change according to the state by the bus state signal regulation.
Bus state signal be in a kind of state of regulation parallel data signal and each state parallel data signal pass on beginning signal regularly.This bus state signal is passed on to storage card 1 from main equipment 2.Its state is divided into 1 state (BS0) that does not carry out packet communication and is in 3 states in the packet communication (4 states of total of BS1～BS3).Bus state signal is pressed the switching timing of High and Low, comes switching state successively from BS0 to BS3.
Clock signal is the clock of parallel data signal and bus state signal.Clock signal is passed on to storage card from main equipment.3 states of clock signal in packet communication (must be exported during BS1～BS3).
Content of Communication under each state as shown in Figure 7.
BS0 is a kind of can passing in the parallel data signal line from the state of storage card 1 to the look-at-me (INT signal) of main equipment 2.The INT signal passes on to clock is asynchronous.In BS0, do not carry out packet communication.The signal level of the bus state signal of expression BS0 is represented with Low.The operating state that reflects storage card 1 in addition in this INT signal, its content aftermentioned.
BS1 is a kind of state that passes on TPC in the parallel data signal line.The signal level of the bus state of expression BS1 is represented with High.TPC passes on to storage card 1 from main equipment 2.TPC is a kind of the be used for register circuit 13 of main equipment 2 visit storage cards 1 and instruction of data buffer circuit 14.The instruction of have the instruction carrying out handling or read processing at writing of the data of data buffer circuit 14 among the TPC, carrying out handling or read processing at writing of the data of register circuit 13, the steering order of carrying out being provided to memory I/F controller 16 write the instruction etc. of the processing of register circuit 13.Particular content aftermentioned to TPC and steering order.
Among BS2 and the BS3, from main equipment 2 to storage card 1 transfer of data write grouping and from storage card 1 to the reading the grouping of main equipment 2 transfer of data, the parallel data of passing on the parallel data signal (DATA[3:0]) to pass on direction and attribute different.The kind of this grouping writes grouping or reads grouping and decided by the content of the TPC that passes on by BS1.
Fig. 8 represents to write the timing diagram of grouping, below the BS2 that writes when grouping, the content of BS3 is explained.
Writing the BS2 in when grouping, the transfer of data on the parallel data signal become to register circuit 13 and data buffer circuit 14 write object data and this writes the CRC of object data.At BS2, the transfer of data on the parallel data signal is passed on to storage card 1 from main equipment 2.
Writing the BS3 in when grouping, the transfer of data on the parallel data signal becomes from storage card 1 take place that the line is busy (BSY) signal and ready (RDY) signal.BS3 when writing grouping, engaged signal on the parallel data signal and ready signal are passed on to main equipment 2 from storage card 1.Writing the BS3 in when grouping, carrying out at the TPC that passes on to storage card 1 from main equipment 2 at BS1 and BS2 and the processing of transfer of data.Storage card 1 (that is, is handled still unclosed occasion) in the processing of just carrying out at this TPC and transfer of data, main equipment 2 is sent engaged signal.Like this, storage card 1 is after this processing finishes, to main equipment 2 ready for sending signals.Engaged signal and ready signal only are transferred to the signal wire of lowest order (DATA0) in 4 parallel data signals.Engaged signal is to make the signal wire of lowest order (DATA0) reach the signal of high level state.Ready signal is to make the signal wire of lowest order (DATA0) be in the signal that repeats the state of high level and low level by each clock alternately.Like this, by transmitting engaged signal and ready signal, can establish transfer of data not write grouping the time BS3 regularly down storage card 1 and the signal exchange of main equipment 2.
Fig. 9 represents to read the timing diagram of grouping, below the BS2 that reads when grouping, the content of BS3 is explained.
BS2 when reading grouping, the transfer of data on the parallel data signal becomes engaged signal and the ready signal that takes place from storage card 1.BS when reading grouping, according to the TPC that passes on to storage card 1 from main equipment 2 at BS1, storage card 1 carries out the preparation of passing on of data.Storage card 1 (that is, passes on and prepares still unclosed occasion) in preparing at passing on of the data of TPC, and main equipment 2 is sent engaged signals.Like this, storage card 1 is after this passes on the preparation end, to main equipment 2 ready for sending signals.Like this, by transmitting engaged signal and ready signal, can establish the signal exchange of storage card 1 and main equipment 2 among the BS2 that reads grouping of transfer of data not.
Reading the BS3 in when grouping, the transfer of data on the parallel data signal become from register circuit 13 and data buffer circuit 14 read object data and this reads the CRC of object data.At BS3, the transfer of data on the parallel data signal is passed on to main equipment 2 from storage card 1.
Figure 10 is illustrated in the engaged signal of BS2, BS3 generation and the detailed timing diagram of ready signal.As shown in Figure 10, engaged signal and ready signal only are transferred to the signal wire of lowest order (DATA0) in 4 parallel data signals.Other position (DATA1～3) becomes the low level.Main equipment 2 receives only the signal that has been sent to DATA0, ignores other signal.Lowest order (DATA0) is corresponding to the conveyer line of the serial data of the storage card that has adopted 3 traditional line formula half-duplex agreements.Therefore, this storage card 1 has the interchangeability with conventional memory card.
Be explained to the INT signal that main equipment 2 passes on from storage card 1 when next, bus state being BS0.
In the storage card 1, flash memories is used as nonvolatile semiconductor memory 17 and uses.Access time at flash memories is compared very long with storage card 1 with the data time of passing between the main equipment 2.Thereby for shortening the data processing operation of main equipment 2 sides, on the data transport protocol, it is effective that regulation is come the interrupt request of notifier processes end etc. from storage card 1 side.That is,, can in visit, the CPU processing of main equipment 2 sides be opened to other processing at flash memories by the interrupt request of regulation from storage card 1.
At BS0, after in the storage card 1 certain interrupt request having taken place, storage card 1 passes on look-at-me (INT signal) to main equipment 2.INT signal and clock signal are non-synchronously from storage card 1 output.When BS0, when any one position of the signal wire of parallel data (DATA[3:0]) reaches the high level, just mean from storage card 1 side interrupt request has taken place.In addition, when any one position of parallel data (DATA[3:0]) all becomes the low level, mean that just storage card 1 is in the execution of processing, does not have interrupt request.
Here, from the interruption key element that storage card 1 takes place, have several.Such as, the fact that is used for having finished at the action of the steering order that has been provided to storage card 1 control be communicated to main equipment 2 interruption, be used for having taken place when having carried out action control in the steering order that has been provided to storage card 1 relatively interruption that the wrong fact is communicated to main equipment 2, interruption that the fact that can not carry out the interruption of main equipment 2 request visits, the steering order that is used for providing from storage card 1 is communicated to main equipment 2 etc.
In storage card 1, above-mentioned each each key element of interrupting is assigned to each position of parallel data (DATA[3:0]), according to the interruption that is taken place the line that reaches the high level is changed.That is, according to the interruption content that is taken place by storage card 1, the different INT signal of digit position that reaches the high level when BS0 takes place from storage card 1.
Main equipment 2 is when BS0, and by monitoring each level of parallel data (DATA[3:0]), detecting from storage card 1 has had interrupt request, and the level that detects which digit position has simultaneously reached high, also detects the interruption key element of storage card 1 simultaneously.
Relative therewith, in traditional memory card system, only whether interrupt request is arranged from storage card side direction host computer side notice.Therefore, even from storage card interrupt request has been arranged, host computer side can not confirm to interrupt key element simultaneously with this request, must establish packet communication, reads the interruption key element to the storage card side.Relative therewith, in the storage card 1 and main equipment 2 under embodiments of the present invention, data line is 4, utilize this point can come each key element of assigned interrupt to each, thereby main equipment 2 can be confirmed this key element simultaneously with interrupt request.
Therefore in the present invention, under the occasion that has taken place from the interrupt request of storage card 1, main equipment 2 can need not to be used to confirm the packet communication of this request content.That is, can shorten data between storage card 1 and the main equipment 2 passes on execution time of operation.
In addition in this example, the INT signal of storage card 1 becomes each place value of depositing in the INT register that has reflected based on the operating state of steering order.The INT register is set in the status register group in the register circuit 13.The parallel interface 12 of storage card 1 is when bus state signal is represented BS0, each place value with reference to this INT register, if this place value becomes effectively (1), then will be driven to the high level with this corresponding data line, if this place value becomes invalid (0), then will be driven to the low level with this place value corresponding data line.Relation for each value of the particular content of this INT register and INT register and parallel data (DATA[3:0]) describes by following register circuit project.
Next, register circuit 13 is explained.
Register circuit 13 is made of a plurality of internal registers.Internal register in the register circuit 13 is classified by following 1～5 according to its purposes.
1. deposit the status register group of the state etc. of storage card 1
2. deposit the parameter register group of the parameter of execution of being used to instruct etc.
3. press each page setup of flash memories, can deposit the additional data registers group of the management data etc. of each page
4. deposit the register address register of the address that is used for specific access location at above-mentioned 1,2,3 each register
5. the order register of the steering order that provides from main equipment 2 is provided
In the status register group, as shown in figure 11, have INT register, status register, type register, classification register, these 4 kinds of internal registers of sort register.In each internal register in the status register group, its value of depositing is upgraded by memory I/F controller 16.Each internal register in the status register group can visit by READ_REG_TPC (READ_REG_TPC is an instruction the TPC, its details aftermentioned) from main equipment 2, and main equipment 2 is output as read-only.Each internal register in the status register group can be deposited 8 place value in addition, sets the address respectively.
The INT register
The INT register is a register of having set the operating state of storage card 1.Value in this INT register is upgraded by memory I/F controller 16 according at the result of the action that is provided to the steering order of storage card 1 from main equipment 2.The INT register is a kind of eight bit register as shown in figure 12.In the INT register, operating state is set to lowest order (D0) and the high 3 (D5～D7) in 8.Remaining position gives over to standby in addition.
The position D7 of INT register is CED (Command End) position.The CED position is that expression (is an instruction among the TPC by EX_SET_CMD_TPC or SET_CMD_TPC.The details aftermentioned) execution of the steering order of the She Zhiing position of having finished.The what is called here carry out to finish expression and carries out and finish in addition, with its execution be normal termination or wrong finish irrelevant.The CED position is when the steering order based on EX_SET_CMD_TPC or SET_CMD_TPC is provided with and during original state, its place value is become invalid (0) by memory I/F controller 16, when the execution based on the steering order of EX_SET_CMD_TPC or SET_CMD_TPC finished, its place value was become effectively (1) by memory I/F controller 16.
The position D6 of INT register is ERR (Error) position.The ERR position is that the expression conduct is carried out by EX_SET_CMD_TPC or the register access instruction (steering order) of SET_CMD_TPC setting and the result of safety command (steering order), and it in carrying out wrong position has taken place.The ERR position is taking place when wrong, its place value is become effectively (1) by memory I/F controller 16, by new EX_SET_CMD_TPC or SET_CMD_TPC, after its steering order was set up or has removed error condition, its place value was become invalid (0) by memory I/F controller 16.
The position D5 of INT register is BREQ/PRG (Buffer Request/Progress) position.The BREQ/PRG position is that expression has been carried out as carrying out the register access instruction (steering order) set by EX_SET_CMD_TPC or SET_CMD_TPC and the result of safety command (steering order), and it carries out the position of situation under the occasion that the inside deletion is handled and format is handled to the request of access of data buffer circuits 14 and nonvolatile semiconductor memory 17 at main equipment 2 that is taken place by this execution.Such as, be a kind of expression have existence under the occasion that writes instruction of nonvolatile semiconductor memory 17 at the data of data buffer circuit 14 write request, exist under the occasion of the data sense order of nonvolatile semiconductor memory 17 from the reception request of the reading request of the data of data buffer circuit 14, secure data etc.The BREQ/PRG position is when having taken place respectively to ask, its place value is become effectively (1) by memory I/F controller 16, taken place based on the occasion at the visit of the TPC of this request by main equipment 2 under, its place value is become invalid (0) by memory I/F controller 16.The BREQ/PRG position is according to the situation of carrying out of format and deletion in addition, and its place value is upgraded by memory I/F controller 16.
The position D0 of INT register is CMDNK (Command Nack) position.The CMDNK position is the position that expression can not be carried out the instruction of being set by EX_SET_CMD_TPC or SET_CMD_TPC.In the time can not carrying out the steering order of setting by EX_SET_CMD_TPC or SET_CMD_TPC, its place value is become effectively (1) by memory I/F controller 16, in the time can carrying out the steering order of being set by EX_SET_CMD_TPC or SET_CMD_TPC, its place value becomes invalid (0).
In the INT register, set above-mentioned position.Like this, by the combination of each place value in the INT register, operating state shown in Figure 13 can be represented as the operating state at the storage card 1 of before this steering order.
That is, at CED=1, ERR=0, BREQ/PRG=0, under the occasion of CMDNK=0, the execution of the steering order that expression is provided is the operating state of normal termination.At CED=1, ERR=1, BREQ/PRG=0, under the occasion of CMDNK=0, the wrong operating state that finishes of the execution of the steering order that expression is provided.At CED=0, ERR=0, BREQ/PRG=1, under the occasion of CMDNK=0, the execution of the steering order that expression is provided is normally being carried out, and proposes the operating state of request of access over against main equipment 2.At CED=0, ERR=1, mistake under the occasion of CMDNK=0, has taken place in the execution of the steering order that expression is provided in BREQ/PRG=1, and proposes the operating state of request of access over against main equipment 2.At CED=0, ERR=0, BREQ/PRG=0, under the occasion of CMDNK=0, the executory operating state of the steering order that is provided is provided in expression.At CED=0, ERR=1, BREQ/PRG=0 is under the occasion of CMDNK=0, during the deletion that expression is in nonvolatile semiconductor memory 17 is carried out or the operating state in the format.At CED=1, ERR=0, BREQ/PRG=0, under the occasion of CMDNK=1, the operating state of the steering order that is provided can not be provided in expression.
In addition, each in the INT register is when having set new steering order by EX_SET_CMD_TPC or SET_CMD_TPC, and its value becomes original state (all place values are 0 state) by memory I/F controller 16.
The relation of INT register and INT signal
Here, as mentioned above, the value of each (CED, ERR, BREQ/PRG, CMDNK) in this INT register is reflected to the INT signal.The parallel interface 12 of storage card 1 according to everybody value (CED, ERR, BREQ/PRG, CMDNK) of this INT register, is driven into high level or low level with each data line of parallel data (DATA[3:0]) when state is BS0.Each of INT register is as follows with the relation of each line of parallel data.
DATA0：CED
DATA1：ERR
DATA2：BREQ/PRG
DATA3：CMDNK
Parallel interface 12 state be BS0 during in continue with reference to the value in the INT register, if the place value in the INT register is effective (1), then corresponding data line is driven into high level (1),, then corresponding data line is driven into low (0) if invalid.Main equipment 2 state be BS0 during in, the level of each data line of parallel data (DATA[3:0]) is monitored, judge whether interrupt request from storage card 1.Main equipment 2 is having from storage card 1 under the occasion of interrupt request, that is, judge a certain data line from the low level under the occasion that the high level changes, the level that detects which data line is becoming high, detects above-mentioned operating state shown in Figure 13.Like this, main equipment 2 carries out corresponding processing according to detected operating state.
As shown in figure 14, be provided with each internal register of systematic parameter register, data counts/security parameter register, data address/correction register, TPC parameter register, order parameter register in the parameter register group.In each internal register in the parameter register group, its value of depositing is upgraded by main equipment 2, in that memory I/when F controller 16 was carried out steering orders, this value was referenced.Each internal register in the parameter register group can be from main equipment 2 by WRITE_REG_TPC, EX_SET_CMD_TPC (one of TPC.The details aftermentioned) visits.Each internal register in the parameter register group is set the address by per 8 bytes in addition.
Data counts/security parameter register
In data counts/security parameter register, deposit execution necessary data number when main equipment 2 is provided to the register access instruction (steering order) of storage card 1.Such as, the data of sense data long grade of data long and that write data when nonvolatile semiconductor memory 17 write data is set during from nonvolatile semiconductor memory 17 sense datas.In data counts/security parameter register, deposit necessary various setting values when carrying out safety command (steering order) in addition.The size of this data counts/security parameter register is 16, sets 2 addresses by 8 units.
Data address/correction register
In data address/correction register, deposit execution address on the necessary nonvolatile semiconductor memory 17 when main equipment 2 is provided to the register access instruction (steering order) of storage card 1.Such as, the front end address of read-out position during from nonvolatile semiconductor memory 17 sense datas, the front end address etc. of writing position was set when nonvolatile semiconductor memory 17 was write data.In addition in data counts/security parameter register, deposit when carrying out safety command (steering order) necessary correction number.The size of this data counts/security parameter register is 32, sets 4 addresses by 8 units.
In addition, be referenced during the execution of READ_DATA, the READ_INFO of data counts/security parameter register and data address/correction register in register access instruction (steering order), WRITE_DATA, WRITE_INFO etc.In above-mentioned in addition data counts/security parameter register and data address/correction register, write data by the WRITE_REG_TPC among the TPC, EX_SET_CMD_TPC.The content details aftermentioned of these steering orders in addition.
The register address register is a kind of when main equipment 2 utilizes TPC to visit above-mentioned status register group and parameter register group, preestablishes the front end address and the long register of data of institute's access register.
By WRITE_REG_TPC (one of TPC.The details aftermentioned) can carry out data to above-mentioned status register group and parameter register group and write, by READ_REG_TPC (one of TPC.The details aftermentioned) but sense data.But, among these WRITE_REG_TPC, the READ_REG_TPC, the information of particular register position is not involved as argument.Therefore, utilize under the occasion that these WRITE_REG_TPC, READ_REG_TPC come register is conducted interviews at main equipment 2, address and the data to this register address register set condition registers group and parameter register group are long in advance.Like this, under the occasion that WRITE_REG_TPC, READ_REG_TPC are provided, memory I/F controller 16 carries out the processing corresponding to each instruction with reference to the information of depositing in this register address register.In addition, this register address register having been deposited the long TPC of register address and data is SET_R_W_REG_ADRS_TPC (details aftermentioned).
Order register is the register that the steering order that provides from main equipment 2 is provided.Memory I/F controller 16 carries out exercises control according to the steering order that is deposited at this order register.The TPC that this order register is deposited steering order is SET_CMD_TPC, EX_SET_CMD_TPC (details aftermentioned).
Next, TPC (Transfer Protocol Command) is explained.
TPC is the instruction of stipulating on the data transport protocol of this storage card 1 and main equipment 2.Register circuit 13 and the data buffer circuit 14 of TPC in 2 pairs of storage cards 1 of main equipment is used to when conducting interviews.TPC becomes the timing of BS1 and is passed on to storage card 1 from main equipment 2 at bus state signal.Below the digital content of this TPC and concrete movement content thereof are explained.
An example of below representing TPC.
READ_LONG_DATA_TPC
READ_SHORT_DATA_TPC
READ_REG_TPC
GET_INT_TPC
WRITE_LONG_DATA_TPC
WRITE_SHORT_DATA_TPC
WRITE_REG_TPC
SET_R_W_REG_ADRS_TPC
SET_CMD_TPC
EX_SET_CMD_TPC
READ_LONG_DATA_TPC is the order of reading 512 byte datas from data buffer circuit 14.That is, be a kind of order that the total data of depositing in the data buffer circuit 14 is passed on to main equipment 2.READ_LONG_DATA_TPC is the order of reading.That is, READ_LONG_DATA_TPC BS1 from main equipment 2 after storage card 1 distribution, 512 byte datas in the data buffer circuit 14 are passed on to main equipment 2 from storage card 1 at BS3.
READ_SHORT_DATA_TPC is the order that will be read from data buffer circuit 14 by the long data of data that the TPC parameter register is set.That is, be a kind of order that the stated amount of data of depositing in the data buffer circuit 14 is passed on to main equipment 2.READ_SHORT_DATA_TPC is the order of reading.That is, READ_SHORT_DATA_TPC BS1 from main equipment 2 after storage card 1 distribution, the specified byte data in the data buffer circuit 14 are passed on to main equipment 2 from storage card 1 at BS3.
READ_REG_TPC is the order of reading the value of the register of setting the address.The register of setting the address is each internal register of status register group, parameter register group and additional register set.The address location of the register that is read out (front end address and data are long) is the value of depositing in the register address register.That is, under the occasion of the value in the reference register, be necessary in advance the register address register to be write the destination address position.The TPC that the address location is write this register address register is SET_R_W_REG_ADRS_TPC.READ_REG_TPC is the order of reading.That is, READ_REG_TPC BS 1 by from main equipment 2 after storage card 1 distribution, the predetermined bits data in the destination register are passed on to main equipment 2 from storage card 1 at BS3.
GET_INT_TPC is that the internal register of sense status register group is the order of the value (8 place value) of INT register.This GET_INT_TPC deposits the address location to the register address register as above-mentioned READ_REG_TPC, but reads the value of INT register.GET_INT_TPC is sense command.That is, GET_INT_TPC BS1 by from main equipment 2 after storage card 1 distribution, 8 bit data in the INT register are passed on to main equipment 2 from storage card 1 at BS3.
WRITE_LONG_DATA_TPC is the order that data buffer circuits 14 is write 12 byte datas.That is, be a kind of order that the total data of data buffer circuit 14 is passed on to data buffer circuit 14 from main equipment 2.WRITE_LONG_DATA_TPC is the order that writes.That is, WRITE_LONG_DATA_TPC BS1 by from main equipment 2 after storage card 1 distribution, 512 byte datas that write data buffer circuit 14 are passed on to storage card 1 from main equipment 2 at BS2.
WRITE_SHORT_DATA_TPC is the order that will be write data buffer circuits 14 by the long data of data of TPC parameter register setting.That is be a kind of stated amount of data to be transferred to order in the data buffer circuit 14 from main equipment 2.WRITE_SHORT_DATA_TPC is the order that writes.That is, WRITE_SHORT_DATA_TPC BS1 by from main equipment 2 after storage card 1 distribution, the data that write the specified byte of data buffer circuit 14 are passed on to storage card 1 from main equipment 2 at BS2.
WRITE_REG_TPC is the order of reading the value of the register of setting the address.The register of setting the address is each internal register of status register group, parameter register group and additional register set, but the register that can be write by main equipment 2 is parameter register group and additional register set.The address location (front end address and data are long) that writes register is the value that is deposited at the register address register.That is, in to register, write under the occasion of numerical value, be necessary in advance the register address register to be write the destination address position.The TPC that the address location is write this register address register is SET_R_W_REG_ADRS_TPC.WRITE_REG_TPC is the order that writes.That is, WRITE_REG_TPC BS1 by from main equipment 2 after storage card 1 distribution, the data that write in the destination register are passed on to storage card 1 from main equipment 2 at BS2.
SET_R_W_REG_ADRS_TPC is the order that will deposit the register address register by the address location of register of READ_REG_TPC, WRITE_REG_TPC visit.SET_R_W_REG_ADRS_TPC is the order that writes.That is, SET_R_W_REG_ADRS_TPC BS1 by from main equipment 2 after storage card 1 distribution, the data that write the register address register are passed on to storage card 1 from main equipment 2 at BS2.
SET_CMD_TPC is to be the order that steering order is deposited order register with the action command at memory I/F controller 16.After steering order was deposited in the order register by SET_CMD_TPC, memory I/F controller 16 carried out the action control based on this steering order.Its movement content is such as at the action of storer control, at the action of each function beyond the storer or the action of relevant data safety etc.In addition, according to the movement content of steering order, move with reference to the value that is deposited in the parameter register sometimes.Under this occasion, be necessary to utilize above-mentioned WRITE_REG_TPC in advance by the grouping before the distribution SET_CMD_TPC, the internal register of stipulating in the parameter register is write numerical value.SET_CMD_TPC is the order that writes.That is, SET_CMD_TPC BS1 by from main equipment 2 after storage card 1 distribution, the code that writes the steering order of order register is passed on to storage card 1 from main equipment 2 at BS2.
EX_SET_CMD_TPC is to data counting/security parameter register and when data address/the correction register is deposited data, order register is deposited the order of steering order.Under the occasion of passing on by EX_SET_CMD_TPC as the memory reference instruction of steering order, in data counts/security parameter register, deposit the data volume of the data that nonvolatile semiconductor memory 17 is conducted interviews, in data address/correction register, the data address of depositing nonvolatile semiconductor memory 17.In addition, under the occasion of passing on by EX_SET_CMD_TPC, in data counts/security parameter register, deposit the parameter that safety management is used, in data address/correction register, deposit correction that safety management uses number as the safety command of steering order.Passing on by this EX_SET_CMD_TPC under the occasion of steering order, before memory I/F controller 16 is carried out these steering orders, data counting/security parameter register and data address/correction register are being deposited transfer of data.
EX_SET_CMD_TPC is the order that writes.That is, EX_SET CMD_TPC BS1 by from main equipment 2 after storage card 1 distribution, the code of steering order etc. is passed on to storage card 1 from main equipment 2 at BS2.
Here, data identical with EX_SET_CMD_TPC are passed on action and also can be utilized SET_CMD_TPC to realize.Yet, move with reference to the value that is deposited at the internal register in the parameter register group under the occasion of steering order of control passing on, such as passing under the occasion of steering orders such as READ_DATA, READ_INFO, WRITE_DATA, WRITE_INFO, must be in advance data that should reference be transferred to parameter register.That is, before carrying out SET_CMD_TPC, must pass on SET_R_W_REG_ADRS and WRITE_REC_TPC earlier.
Relative therewith, under the occasion that has adopted EX_SET_CMD_TPC, also can not utilize WRITE_REG_TPC that data are deposited data counts/security parameter register and data address/correction register in advance.That is,, pass on action just then only need 1 grouping can be implemented in the data that need 3 groupings under the situation that adopts SET_CMD_TPC if utilize EX_SET_CMD_TPC.
Therefore,, also can not carry out and pass on the grouping operation of SET_R_W_REG_ADRS and WRITE_REG_TPC, can realize the high speed of handling if adopt EX_SET_CMD_TPC to pass on steering order.
Figure 15 has represented to carry out the concrete transfer of data example of passing on to storage card 1 from main equipment 2 under the occasion of SET_CMD_TPC.Figure 16 has represented to carry out the concrete transfer of data example of passing on to storage card 1 from main equipment 2 under the occasion of EX_SET_CMD_TPC.This Figure 15 and transfer of data shown in Figure 16 are passed on when BS2.
Having carried out transfer of data under the occasion of SET_CMD_TPC becomes the CRC of order code and 2 bytes of 1 byte.The order code of 1 byte is the specific code that makes memory I/steering order that F controller 16 is carried out.Order code is deposited at order register.
The transfer of data of having carried out under the occasion of EX_SET_CMD_TPC becomes the address/correction data of the order code of 1 byte, the counting of 2 bytes/security parameter data, 2 bytes, the CRC of 2 bytes.Counting/security parameter data are the data that are deposited at data counts/security parameter register.Address/correction data are the data that are deposited at data address/correction register.
As Figure 15 and shown in Figure 16, transfer of data one side's of EX_SET_CMD_TPC data length is compared longer with the transfer of data of SET_CMD_TPC.Therefore, under main equipment 2 passes on the occasion of not comparable data counting/security parameter register and data address/order code that the correction register is carried out, be not to adopt EX_SET_CMD_TPC, but adopted the side of SET_CMD_TPC to become shorter grouping.Therefore, by setting SET_CMD_TPC and EX_SET_CMI_TPC,, can make and handle more high speed according to the selection that the steering order of being passed on suits as the instruction of TPC.
Below, steering order is explained.
Steering order is from the action directive that memory I/F controller 16 provide of main equipment 2 to storage card 1.Steering order is deposited order register in the storage card 1 by the SET_CMD_TPC of TPC or EX_SET_CMD_TPC from main equipment 2.Memory I/F controller 16 is carried out the action control corresponding to this steering order after steering order is deposited in the order register.Like this, when carrying out this action control, each value in the INT register is suited to upgrade.
Steering order is divided into 3 kinds of memory reference instruction, function command and safety commands.Memory reference instruction is the instruction that the nonvolatile semiconductor memory on the storage card 1 17 is conducted interviews.Function command is the instruction that each function on the storage card 1 is conducted interviews.Safety command is to be used to realize that the works wooden fork protects the instruction of necessary security function.
Have in the memory reference instruction such as from nonvolatile semiconductor memory 17 to the instruction of data buffer circuit 14 sense datas, write the instruction of data, the instruction etc. of data on the deletion nonvolatile semiconductor memory 17 to nonvolatile semiconductor memory 17 from data buffer circuit 14.
Have in the function command such as making this storage card 1 return to the format instruction of factory state and making dormancy instruction that the action of the oscillator 18 of storage card 1 stops etc.
Have instruction in the safety command, carry out instruction, the instruction of random number etc. takes place at the operation of the key that locks in the content key such as the intrinsic ID that reads this storage card 1.
Here, Figure 17 represents an example of memory reference instruction.
In the memory reference instruction, as shown in figure 17, have READ_DATA, WRITE_DATA, READ_INFO, READ_ATRB, STOP, ERASE etc.
READ_DATA is the assigned address order of sense data continuously from the user area of nonvolatile semiconductor memory 17.Memory I/F controller 16 is after providing this READ_DATA, and the address of depositing in comparable data address/correction register conducts interviews to this address on the nonvolatile semiconductor memory 17, from this address read-outing data.The data of being read were once passed on to data buffer circuit 14.Memory I/F controller 16 is fully loaded at data buffer circuit 14, promptly read 512 byte datas after, make the BREQ/PRG position of INT register become effectively (1), main equipment 2 is issued the interruption of transfer request.Like this, after the data in the main equipment 2 sense data buffer circuits 14, follow-up data is passed on to data buffer circuit 14 from nonvolatile semiconductor memory 17.Memory I/F controller 16 repeats above-mentioned processing, the data of the data volume of depositing in sense data counting/security parameter register.Like this, do not make a mistake ground sense data, last till end always after, make the CMD position of INT register become effectively (1), end process.Taken place under the wrong occasion in this external processing procedure, when the CMD position that makes the INT register becomes effectively (1), made the ERR position become effectively (1), with this end process.
WRITE_DATA is the order that is deposited at the data of data buffer circuit 14 from the assigned address continuous recording of the user area of nonvolatile semiconductor memory 17.Memory I/F controller 16 is after providing WRITE_DATA, and the address of depositing in comparable data address/correction register conducts interviews to this address on the nonvolatile semiconductor memory 17, writes data from this address.The data that write are the data that are deposited at data buffer circuit 14.Memory I/F controller 16 becomes the free time in data buffer circuit 14, promptly write 512 byte datas after, make the BREQ/PRG position of INT register become effectively (1), to the interruption of main equipment 2 distribution transfer request.Like this, in data buffer circuit 14, write data by main equipment 2 after, follow-up data is write to nonvolatile semiconductor memory 17 from data buffer circuit 14.Memory I/F controller 16 repeats above-mentioned processing, the data of the data volume of depositing in writing data counts/security parameter register.Like this, after not writing data with not making a mistake and lasting till end always, make the CMD position of INT register become effectively (1), end process.Taken place under the wrong occasion in this external processing procedure, when the CMD position that makes I NT register becomes effectively (1), made the ERR position become effectively (1), with this end process.
READ_INFO is the order from the continuous sense data of assigned address in the information volume district of the system region of nonvolatile semiconductor memory 17.The processing sequence of memory I/F controller 16 is identical with READ_DATA.
WRITE_INFO is the order that the assigned address in the information volume district of the system region of nonvolatile semiconductor memory 17 is write continuously data.The processing sequence of memory I/F controller 16 is identical with WRITE_DATA.
READ_ATRB is the order of reading attribute information from nonvolatile semiconductor memory 17.Memory I/F controller 16 is read the attribute information in the nonvolatile semiconductor memory 17 after this READ_ATRB is provided, be transferred to data buffer circuit 14.
STOP is the order that finishes the execution of READ_DATA, WRITE_DATA, READ_INFO, WRITE_INFO, READ_ATRB processing midway.Memory I/F controller 16 stops READ_DATA, WRITE_DATA, READ_INFO, WRITE_INFO, READ_ATRB carries out processing after STOP is provided.
ERASE is the order from the assigned address deleted data of user area.Memory I/F controller 16 is after providing ERASE, with reference to the address that is deposited at data address/correction register, from the position of depositing shown in this address, the data on the nonvolatile semiconductor memory 17 of the data volume of depositing in the deleted data counting/security parameter register.
More than to having adopted portable storage card of the present invention and this storage card being described as the main equipment that external memory media uses.The present invention is defined in to use this storage card.Such as, also the present invention can be used for camera apparatus as the external connection device of main equipment.Under this occasion, memory I/F controller 16 carries out the action control of camera apparatus, also sets the instruction of camera control usefulness in this external steering order.
The present invention is defined in reference to the illustrated the foregoing description of accompanying drawing in addition, under the prerequisite that does not exceed with claim scope of paying and purport thereof, can carry out various changes, displacement or equal with it behavior, to this insider Ying Mingxiao.
Utilizability on the industry
In the external connection apparatus and main equipment involved in the present invention, at the shape of bus state signal When attitude becomes state from external connection apparatus to main equipment that accept the interruption from, will represent based on from The interruption that the action directive that main equipment provides to the controller of external connection apparatus takes place is wanted The information of plain content is as the interrupt signal that provides from external connection apparatus to main equipment, by number Pass on according to bus, thereby pass through with reference to interrupt signal, main equipment can be judged external connection apparatus The interruption key element that takes place. Therefore, main equipment need not to connect with the outside after having received interrupt signal The equipment of connecing communicates to confirm to interrupt key element, can carry out at once corresponding to this interruption key element Alignment processing. Therefore, in the external connection apparatus and main equipment that the present invention relates to, externally connect Connecing equipment side has had under the occasion of interrupt requests, can shorten the data transfer operation.

Claims (28)

1. external connection apparatus that is connected to main equipment is characterized in that:
Possess
Data communication units, its and above-mentioned main equipment between transmit data by data bus two-way communication;
The bus state signal receiving element, it receives the bus state signal of the state of the above-mentioned data bus of expression from above-mentioned main equipment;
Controller, it carries out the action control of this equipment according to the action directive that comprises in the above-mentioned transmission data,
Above-mentioned data communication units is at the state of above-mentioned bus state signal accepts from this equipment during to the state of the interruption of main equipment, and the information of expression based on the interruption factor content that action directive took place that provides to above-mentioned controller from main equipment is sent to above-mentioned main equipment by above-mentioned data bus.
In the claim 1 record external connection apparatus, it is characterized in that:
Above-mentioned data communication units will be interrupted the information of factor content as expression, the action status information of the operating state of this equipment came to send to above-mentioned main equipment by above-mentioned data bus when expression had been carried out action control based on the action directive that provides to above-mentioned controller from main equipment.
In the claim 1 record external connection apparatus, it is characterized in that:
Possess the register of depositing above-mentioned action status information,
The above-mentioned action directive that provides from main equipment is provided for above-mentioned controller, and the operating state according to based on this equipment of this execution upgrades the action status information in the above-mentioned register,
Above-mentioned data communication units is in to accept from this equipment at the state of above-mentioned bus state signal and during to the state of the interruption of main equipment, the above-mentioned action status information that is deposited at above-mentioned register is sent to above-mentioned main equipment by above-mentioned data bus.
In the claim 3 record external connection apparatus, it is characterized in that:
Comprise in the above-mentioned action status information
1 information (CED position) of representing the operating state that the execution of above-mentioned action directive has finished;
1 information (ERR position) of representing the operating state that the execution of above-mentioned action directive makes mistakes;
Expression is accepted from 1 information (BREQ/PRG position) of main equipment to the operating state of the visit of this equipment as the result who has carried out above-mentioned action directive;
The execution of representing above-mentioned action directive is 1 information (CMDNK position) of impossible operating state.
In the claim 4 record external connection apparatus, it is characterized in that:
Above-mentioned data bus transmits at least 4 bit parallel data,
Above-mentioned data communication units as 4 bit parallel data, comes above-mentioned CED position, above-mentioned ERR position, above-mentioned BREQ/PRG position and above-mentioned CMDNK position to send to above-mentioned main equipment by above-mentioned data bus.
In the claim 5 record external connection apparatus, it is characterized in that:
Asynchronous above-mentioned CED position, above-mentioned ERR position, above-mentioned BREQ/PRG position and the above-mentioned CMDNK position of transmitting of transmission clock of above-mentioned data communication units and the above-mentioned data bus that provides from above-mentioned main equipment.
In the claim 5 record external connection apparatus, it is characterized in that:
Above-mentioned controller makes the CED position effective when the execution normal termination of above-mentioned action directive, makes the ERR position invalid, makes the BREQ/PRG position invalid, makes the CMDNK position invalid.
In the claim 5 record external connection apparatus, it is characterized in that:
Above-mentioned controller has taken place to make the CED position effective when wrong in the execution of above-mentioned action directive, makes the ERR position effective, makes the BREQ/PRG position invalid, makes the CMDNK position invalid.
In the claim 5 record external connection apparatus, it is characterized in that:
Above-mentioned controller normally carries out in the execution of above-mentioned action directive, and accepts from main equipment and during to the visit of this equipment, make the CED position invalid, makes the ERR position invalid, makes the BREQ/PRG position effective, makes the CMDNK position invalid.
In the claim 5 record external connection apparatus, it is characterized in that:
Above-mentioned controller makes a mistake in the execution of above-mentioned action directive, and accepts from main equipment and during to the visit of this equipment, make the CED position invalid, makes the ERR position effective, makes the BREQ/PRG position effective, makes the CMDNK position invalid.
11. the external connection apparatus of record in the claim 5 is characterized in that:
Above-mentioned controller in the execution that is in above-mentioned action directive in, make the CED position invalid, make the ERR position invalid, make the BREQ/PRG position invalid, make the CMDNK position invalid.
12. the external connection apparatus of record in the claim 5 is characterized in that:
Above-mentioned controller makes the CED position effective carrying out in the above-mentioned action directive, makes the ERR position invalid, makes the BREQ/PRG position invalid, makes the CMDNK position effective.
13. the external connection device of record in the claim 1 is characterized in that:
Face shaping is the card type.
14. a main equipment that connects external connection apparatus is characterized in that:
Possess
Data communication units, its and the said external connection device between transmit data by data bus two-way communication;
The bus state signal transmitting element, its bus state signal that will represent the state of above-mentioned data bus sends to above-mentioned external connection apparatus;
Controller, its steering order that will carry out the action control of external connection apparatus covers above-mentioned transmission data and issues,
Above-mentioned data communication units is at the state of above-mentioned bus state signal accepts from external connection apparatus during to the state of the interruption of this equipment, receives the information of expression based on the interruption factor content that action directive took place that provides to above-mentioned external connection apparatus from this equipment by above-mentioned data bus from the said external connection device.
15. the main equipment of record in the claim 14 is characterized in that:
Above-mentioned data communication units receives the information of interrupting factor content as expression by above-mentioned data bus from the said external connection device, the action status information of the operating state of this equipment when expression has been carried out action control based on the action directive that provides to above-mentioned controller from main equipment.
16. the main equipment of record in the claim 15 is characterized in that:
Comprise in the above-mentioned action status information
1 information (CED position) of representing the operating state that the execution of above-mentioned action directive has finished;
1 information (ERR position) of representing the operating state that the execution of above-mentioned action directive makes mistakes;
Expression is accepted from 1 information (BREQ/PRG position) of main equipment to the operating state of the visit of this equipment as the result who has carried out above-mentioned action directive;
The execution of representing above-mentioned action directive is 1 information (CMDNK position) of impossible operating state.
17. the main equipment of record in the claim 16 is characterized in that:
Above-mentioned data bus transmits at least 4 bit parallel data,
Above-mentioned data communication units as 4 bit parallel data, by above-mentioned data bus, receives above-mentioned CED position, above-mentioned ERR position, above-mentioned BREQ/PRG position and above-mentioned CMDNK position from the said external connection device.
18. the main equipment of record in the claim 17 is characterized in that:
Asynchronous above-mentioned CED position, above-mentioned ERR position, above-mentioned BREQ/PRG position and the above-mentioned CMDNK position of receiving of transmission clock of above-mentioned data communication units and the above-mentioned data bus that provides to above-mentioned external connection apparatus from this equipment.
19. the main equipment of record in the claim 17 is characterized in that:
Above-mentioned controller is effective in the CED position, and the ERR position is invalid, and the BREQ/PRG position is invalid, when the CMDNK position is invalid, judges the execution normal termination of above-mentioned action directive.
20. the main equipment of record in the claim 17 is characterized in that:
Above-mentioned controller is effective in the CED position, and the ERR position is effective, and the BREQ/PRG position is invalid, and when the CMDNK position was invalid, judgement was to have taken place in the mistake in the execution of above-mentioned action directive.
21. the main equipment of record in the claim 17 is characterized in that:
Above-mentioned controller is invalid in the CED position, and the ERR position is invalid, and the BREQ/PRG position is effective, when the CMDNK position is invalid, judges that the execution of above-mentioned action directive is normally carried out, and is is accepting from the visit of main equipment to external connection apparatus.
22. the main equipment of record in the claim 17 is characterized in that:
Above-mentioned controller is invalid in the CED position, and the ERR position is effective, and the BREQ/PRG position is effective, when the CMDNK position is invalid, judges in the execution of above-mentioned action directive mistake has taken place, and accepting from the visit of this equipment to external connection apparatus.
23. the main equipment of record in the claim 17 is characterized in that:
Above-mentioned controller is invalid in the CED position, and the ERR position is invalid, and the BREQ/PRG position is invalid, when the CMDNK position is invalid, judgement be in the execution of above-mentioned action directive in.
24. the main equipment of record in the claim 17 is characterized in that:
Above-mentioned controller is effective in the CED position, and the ERR position is invalid, and the BREQ/PRG position is invalid, and when the CMDNK position was effective, judgement can not be carried out above-mentioned action directive.
25. the main equipment of record in the claim 14 is characterized in that:
The face shaping of said external connection device is the card type.
26. a data communication system that possesses main equipment and be connected to the external connection apparatus of this main equipment is characterized in that:
Above-mentioned main equipment has
Data communication units, its and the said external connection device between transmit data by data bus two-way communication;
The bus state signal transmitting element, its bus state signal that will represent the state of above-mentioned data bus sends to above-mentioned external connection apparatus;
Controller, its steering order that will carry out the action control of external connection apparatus covers above-mentioned transmission data and issues,
The said external connection device has
Data communication units, its and above-mentioned main equipment between transmit data by data bus two-way communication;
The bus state signal receiving element, it receives the bus state signal of the state of the above-mentioned data bus of expression from above-mentioned main equipment;
Controller, it carries out the action control of this equipment according to the action directive that comprises in the above-mentioned transmission data,
The data communication units of above-mentioned main equipment and said external connection device is at the state of above-mentioned bus state signal accepts from external connection apparatus during to the state of the interruption of main equipment, sends expression information based on the interruption factor content that action directive took place that from main equipment to external connection apparatus provide from external connection apparatus to main equipment by above-mentioned data bus.
27. the data communication system of record in the claim 26 is characterized in that:
The data communication units of above-mentioned main equipment and said external connection device will be interrupted the information of factor content as expression, and the action status information of the operating state of external connection apparatus sent to main equipment from external connection apparatus by above-mentioned data bus when expression had been carried out action control based on the action directive that provides to external connection apparatus from main equipment.
28. the data communication system of record in the claim 26 is characterized in that:
The face shaping of said external connection device is the card type.
CNB038001640A 2002-02-21 2003-02-19 External connection device, host device and data communication system Expired - Fee Related CN1297915C (en)

Applications Claiming Priority (2)

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JP2002045252A JP4178809B2 (en) 2002-02-21 2002-02-21 Externally connected device and host device
JP45252/2002 2002-02-21

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CN1297915C CN1297915C (en) 2007-01-31

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JP (1) JP4178809B2 (en)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102207921A (en) * 2010-06-01 2011-10-05 钰创科技股份有限公司 System and method of achieving multi-port storage media based on UASP protocol

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005222201A (en) * 2004-02-04 2005-08-18 Matsushita Electric Ind Co Ltd Memory access device and semiconductor memory card
JP2007527579A (en) 2004-02-23 2007-09-27 レクサー・メディア・インコーポレーテッド Secure compact flash
US7664902B1 (en) * 2004-03-16 2010-02-16 Super Talent Electronics, Inc. Extended SD and microSD hosts and devices with USB-like high performance packetized interface and protocol
KR100909364B1 (en) 2007-02-06 2009-07-24 삼성전자주식회사 Memory controller and method of blocking system clock exposure
US7870305B2 (en) * 2007-03-09 2011-01-11 Microsoft Corporation Proxy association for devices
US8064205B2 (en) * 2008-05-19 2011-11-22 Dell Products, Lp Storage devices including different sets of contacts
US20100030962A1 (en) * 2008-08-04 2010-02-04 Sherif Sirageldin Storage facility for data handling devices
JP5673949B2 (en) * 2011-03-18 2015-02-18 大日本印刷株式会社 Semiconductor memory device capable of executing format processing in accordance with internal state, and format processing method of semiconductor memory device
JP5694101B2 (en) * 2011-09-20 2015-04-01 株式会社東芝 Memory device, host device
US9647997B2 (en) 2013-03-13 2017-05-09 Nagrastar, Llc USB interface for performing transport I/O
USD759022S1 (en) * 2013-03-13 2016-06-14 Nagrastar Llc Smart card interface
USD729808S1 (en) * 2013-03-13 2015-05-19 Nagrastar Llc Smart card interface
USD758372S1 (en) 2013-03-13 2016-06-07 Nagrastar Llc Smart card interface
US9888283B2 (en) 2013-03-13 2018-02-06 Nagrastar Llc Systems and methods for performing transport I/O
USD780763S1 (en) 2015-03-20 2017-03-07 Nagrastar Llc Smart card interface
USD864968S1 (en) 2015-04-30 2019-10-29 Echostar Technologies L.L.C. Smart card interface

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5416945A (en) * 1977-07-08 1979-02-07 Nippon Telegr & Teleph Corp <Ntt> Signal transmission system
JPS5614329A (en) * 1979-07-16 1981-02-12 Nec Corp Data processing system
US5805844A (en) * 1996-10-07 1998-09-08 Gustin; Jay W. Control circuit for an interface between a PCI bus and a module bus
JPH117505A (en) * 1997-06-17 1999-01-12 Fujitsu Ltd Card type storage medium
IT1308343B1 (en) * 1999-02-03 2001-12-11 St Microelectronics Srl PROCEDURE TO ARBITRATE INTERRUPTION PRIORITIES BETWEEN PERIPHERALS IN A MICROPROCESSOR BASED SYSTEM
US6618789B1 (en) * 1999-04-07 2003-09-09 Sony Corporation Security memory card compatible with secure and non-secure data processing systems
US6839857B2 (en) * 2000-01-13 2005-01-04 Sony Computer Entertainment Inc. Interrupt controller in an interface device or information processing system
JP2001202254A (en) * 2000-01-21 2001-07-27 Yaskawa Electric Corp Microprocessor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102207921A (en) * 2010-06-01 2011-10-05 钰创科技股份有限公司 System and method of achieving multi-port storage media based on UASP protocol
CN102207921B (en) * 2010-06-01 2015-11-25 钰创科技股份有限公司 Based on system and the method thereof of UASP protocol realization multiport Storage Media

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JP2003241908A (en) 2003-08-29
US20040172488A1 (en) 2004-09-02
US7051128B2 (en) 2006-05-23
DE60317771D1 (en) 2008-01-10
EP1477902A4 (en) 2006-09-06
JP4178809B2 (en) 2008-11-12
EP1477902B1 (en) 2007-11-28
CN1297915C (en) 2007-01-31
WO2003071437A1 (en) 2003-08-28
US7318113B2 (en) 2008-01-08
KR100987205B1 (en) 2010-10-12
DE60317771T2 (en) 2008-12-04
KR20040086502A (en) 2004-10-11
EP1477902A1 (en) 2004-11-17

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