CN1507151A - Variable impedance network for integrated circuits - Google Patents
Variable impedance network for integrated circuits Download PDFInfo
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- CN1507151A CN1507151A CNA021559511A CN02155951A CN1507151A CN 1507151 A CN1507151 A CN 1507151A CN A021559511 A CNA021559511 A CN A021559511A CN 02155951 A CN02155951 A CN 02155951A CN 1507151 A CN1507151 A CN 1507151A
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Abstract
A variable impedance network is used to construct the potentiometer and digital-to-analog converter (DAC), the impedance network is constructed to reduce the number of circuits compared with the conventional method, and the reduction ratio of the excessive circuits comprises exponentially increased transistors and the same number of taps required by the potentiometer.
Description
Technical field
The present invention relates to a kind of variable impedance network, particularly a kind of variable impedance network that is used in integrated circuit.
Background technology
Variableimpedance (impedance) network normally with manual adjustment to provide, so that influence a certain tense of the residing circuit of network as selectable impedance.These variable impedance networks normally form with variable resistor (resistor), also are called potentiometer (Potentiometer), but the circuit variable impedance network that forms with variable inductance or electric capacity.
Data Processing need incessantly potentiometer to be adjusted, and for the circuit under the control of data processing system external electronic circuits, potentiometric manual adjustment is extremely inconvenient when carrying out circuit operation by external electronic circuits.Because data processing system must change the value of variable impedance network often in the time, and this time much smaller than the required time of the manual adjustment of finishing variable impedance element, therefore, promptly once used the integrated circuit variable impedance network of special-purpose in prior art, these networks allow attenuation degrees externally to be adjusted under data processing system digital control.
For example, Tanaka, et al., the United States Patent (USP) notification number 4,468 of proposition, 607, illustrate that promptly ladder attenuator is controlled by the binary numerical value of commutation circuit device, wherein in the switch step of commutation circuit (switch circuit), one or more decling phase can be introduced into the signal path, yet the explanation of Tanaka need have a large amount of blocked impedance elements and the switching device of using as impedance on a large scale.According to this, Drori, et al., the United States Patent (USP) notification number 5,084,667 of proposition promptly proposes to reduce with the enforcement amount of variable impedance element the fractional dose of resistance, and then utilizes a sequence permutation resistance to finish equivalent solution.
Summary of the invention
Main purpose of the present invention provides a kind of impedance network, and this impedance network has one and finishes terminal to, a vernier terminal and several first group of anti-element.Wherein, the vernier terminal is to provide tap joint position in the selection resistance value of impedance network, and is to select with a specific added value.And several first impedance components are to be configured to provide a scope resistance value, and wherein the quantity of vernier switching device is than having a fixing impedance component of added value of selecting in the impedance network for few.
Provide a kind of method that disposes impedance network according to another object of the present invention, the method comprises first configuration, be several first resistance of configuration, wherein these first resistance are optionally to connect side by side, then sequence connects several second resistive elements, wherein each resistive element comprises by the formed equivalent resistance of above-mentioned first resistance, carry out second configuration afterwards, be the second above-mentioned resistive element to be carried out the correspondence configuration, optionally connect the vernier terminal of the node of second resistive element again to impedance network with the center of impedance network.
Description of drawings
What Fig. 1 (A) illustrated is known variable-resistor network;
What Fig. 1 (B) illustrated is standard central authorities tap potentiometers (Center-tappedpotentiometer);
What Fig. 2 illustrated is an impedance network array structure of foundation first preferred embodiment of the present invention;
What Fig. 3 illustrated is a resistor network array structure of using according to the conduct 64 tap potentiometers of second preferred embodiment of the present invention;
What Fig. 4 illustrated is that known method and new method are being used the transistorized comparison diagram of potentiometer wiper;
What Fig. 5 illustrated is the flow chart of the new method of foundation the 3rd preferred embodiment of the present invention at setting impedance network array.
Embodiment
Because of suspecting above-mentioned state about the known variable impedance network, the present invention promptly provides the alternate embodiment about variable impedance network, can reduce and comprise the transistorized multicircuit of crossing of potentiometer wiper, for above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, below lift preferred embodiment, and conjunction with figs. elaborates, but the present invention is not so limited.
What illustrate in Fig. 1 (A) is about a known variable-resistor network 100, this variable-resistor network 100 comprises counter 102, control circuit 104, decoder 106 and network array 108, and wherein network array 108 comprises transistor array 110 and electric resistance array 112.In given example, network array 108 has three terminals (terminal), be respectively H, L and W, therefore, network array 108 promptly is the comparation potentiometer 120 of simulation shown in Fig. 1 (B), wherein, when terminal W was the center tap of corresponding potentiometer 120, terminal H was corresponding end terminal with L.
In the example that Fig. 1 (A) illustrates, electric resistance array 112 comprises the resistive element (R) of 32 series arrangement, being expressed as 32 tap joint position at potentiometer 120 vernier nodes (wiper node), but any resistive element may provide the resistance value littler or bigger than this example.In addition, the vernier transistor that transistor array 110 comprises is the resistive element in order to various combination between connecting terminal H and the W.
Wherein can decide specific combination, and count value is to be changed by two signals, is respectively U/D and INCR by the count value that stores in the counter 102.The U/D signal is whether the count value that stores in the decision counter 102 can be by the corresponding predetermined quantity that increases signal (INCR).In addition, counter 102 is to couple 1 pair of N decoder 106, N=32 wherein, the output of decoder 106 is the vernier transistors in the oxide-semiconductor control transistors array 110, because N is the maximum that is stored in the counter 102, and in electric resistance array 112, have a N node, so the corresponding given count value of each node, each node is can be by the vernier transistor of signal and transistor array 110 corresponding and couple with terminal W.
The value that is stored in counter 102 can be converted to the memory of control circuit 104 because of the specific voltage of wafer selection wire (CS), and simultaneously, the wafer selection wire also can activation counter 102.When the wafer selection wire is to be in logic low state, then counter 102 is the signals on reaction U/D and the INCR line, and this makes circuit can control variable-resistor network 100 and goes to change the value that is stored in the counter 102.
When power supply is supplied to variable-resistor network 100, control circuit 104 also can be supervised service voltage (Vcc and Vss) to be written into storage values in the memory to counter 102, and this can guarantee before power supply enters the final value that the counter that removes from variable-resistor network 100 102 is stored, can be resumed when power supply enters variable-resistor network 100 again.
Along with above-mentioned method at Fig. 1 (A) and Fig. 1 (B) is described, N vernier transistor can produce N tap joint position, therefore, when N change big (for example, N＞100), the zone that the vernier transistor couples can obviously increase, particularly when the specification of vernier resistance value reduces (for example, 50 ohm or lower).
According to this, embodiments of the invention promptly at above-mentioned because of the N value becomes big problem, provide the less vernier of a kind of need transistorized variable impedance network.Further, it can be not only resistance that embodiments of the invention extend into the element that the impedance network that comprised uses, and also other element for example is electric capacity or inductance.In following first embodiment, impedance network is to be equipped with several sequences to connect the right binary numerical method of resistance, wherein each between be to connect in mode arranged side by side.Yet, in second preferred embodiment, can surpass two resistance so that broader resistance value to be provided with arrangement mode configuration arranged side by side, therefore, can further reduce the vernier number of transistors.In the 3rd preferred embodiment, can provide shunting transistor (bypass transistor) to shunt specific transistor, this also can provide the more resistance value of wide region.
A kind of impedance network array configurations 200 according to first preferred embodiment of the present invention is illustrated in Fig. 2.In this embodiment, network array 200 is to dispose several sequences to connect resistance right, and wherein each is to being to connect in mode arranged side by side, in the present embodiment, several sequences connect resistance to being to be connected in junction nodes, and are identical with the right resistance value of the resistance of connection arranged side by side.In the present embodiment, switching device as transistor, is the resistance that sequence connects resistance centering, resistance arranged side by side to be provided or not to connect resistance.Particularly, transistor can be a field-effect transistor (Field-Effect Transistor; Be called for short FET), and the right resistance value of several sequences connection resistance is not taken charge of.In the present embodiment, it is symmetrical according to Centroid 0 that several sequences connect the right resistance value of resistance, each resistance to be via as transistorized switching device go to select different sequence resistance combinations, optionally to be connected to vernier terminal (W), particularly when transistor can be a field-effect transistor.
Impedance network array configurations 200 can arrange to have two restrictive conditions, wherein first restrictive condition is that the linking resistor in the array (as potentiometer) 200 is fixed, and this restrictive condition need be observed, it is constant promptly need to keep finishing to be connected resistor between terminal H and the L, to guarantee potentiometric suitable running, and second restrictive condition is to produce all possible tap at potentiometric each node place, and along with each tap provides a cell resistance (R), therefore, follow the 21R of 22 1R taps to be connected the potentiometric allocation plan of resistor as shown in Figure 2.
In order to reach first restrictive condition, binary sequence is to center on Centroid 0 and mapping, is complementary at resistance between H and the W and the resistance between W and L consequently, and then makes the linking resistor can be fixed to 21R.For instance, if select the 1R on H to the W end (promptly to obtain with 2R||2R by turn-on transistor T1 and Tw2, wherein || be meant configuration arranged side by side), then the resistance of 20R then must be other electric resistance arrays to select W to L to hold by unlatching T2 and T3, and the configuration that wherein produces 20R can be (4R||4R)+(8R||8R)+8R+4R+2R=2R+4R+8R+4R+2R.In this embodiment, be denoted as TX, the transistor that X is expressed as between 1～6 is called transmission transistor (Pass transistor), and is denoted as TwX, and the transistor that X is expressed as between 1～7 is called vernier transistor (Wiper transistor).Therefore, when the vernier transistor allowed each sequence resistance to merge enforcement, it was configuration arranged side by side that transmission transistor can allow transistor.
Second restrictive condition can utilize following formula to guarantee to reach all minimum (R) taps that increase by being connected resistor:
Rend-to-end＝Rmax+Rmin
Wherein Rmax is the maximum resistance (promptly being half place that is configured in network array) that is configured in network array 200 centers (as sign 0 place of Fig. 2); And Rmin is the minimum resistance that is configured in network array 200 centers (as sign 0 place of Fig. 2).
In the embodiment that Fig. 2 illustrated, Rmax is 14R, and Rmin is 7R, therefore in this configuration, Rmin=Rmax/2, and Rend-to-end=14R+7R=21R, this is connected resistor and satisfies two above-mentioned restrictive conditions, and, all possible 22 taps have been produced to 21R potentiometer 200.According to this, reach the 1R on H to the W end, as above routine described, need turn-on transistor T1 and Tw2, need turn-on transistor T2 to cooperate to utilize the 20R on all the other network arrays on W to the L end simultaneously with T3.And to reach the 2R that H to W holds, and then need turn-on transistor Tw2, need turn-on transistor T2, T3 and T6 to cooperate simultaneously to utilize the 19R on all the other network arrays on W to the L end.Reach the 3R on H to the W end, need turn-on transistor T1, T2 and Tw3, need turn-on transistor T3 to cooperate simultaneously to utilize the 18R on all the other network arrays on W to the L end, the rest may be inferred, under the situation that increases 1R, same arrangement also can be set, and promptly needs to provide from 4R to 21R remaining resistance value.
Please refer to table 1, what it illustrated is the resistor network allocation list that disposes about 64,128 and 256 tap potentiometers, and relevant electric resistance structure value and sequence.Though this table only shows three kinds of configuring conditions, further class structure is all similar on arranging for other.For instance, Fig. 3 illustrates promptly be the present invention's second preferred embodiment about the potentiometric resistor network configuration 300 of 64 taps (64-tap).
Table one
| Total class | ?R TOTAL | ?R MIN | ?R MAX | Network configuration |
| 64 | ?63R | ?21R | ?42R | ?2R????4R????8R????16R????12R ?12R???16R???8R????4R?????2R |
| 128 | ?127R | ?41R | ?86R | ?2R????4R????8R????16R????32R ?24R???24R???32R???16R????8R ?4R????2R |
| 256 | ?255R | ?85R | ?170R | ?2R????4R????8R????16R????32R ?64R???44R???44R???64R????32R ?16R???8R????4R????2R |
As mentioned above, present embodiment promptly by demand still less the vernier transistor and be better than existing network configuration, universal method is to do linear programming with tap quantity, this universal method needs N+i vernier transistor under the situation of N tap, yet, the method of present embodiment then is to oppose with tap quantity to counting planning, promptly needs under the situation of N tap
Individual vernier transistor.
Table 2 illustrates is different that resource is used between the new method of universal method and Fig. 2 to Fig. 5 of Fig. 1.Wherein, one of advantage of new method comprises that this minimizing further provides because of the caused effective parasitic capacitance of vernier transistor, therefore, also can increase potentiometric frequency response than the apparent transistorized demand of minimizing vernier that lands of universal method.Yet, new method but needs the unit sizes of manying resistor (unit size resistor) than universal method, wherein to use the quantity of many unit sizes resistor promptly be 2.66 times of universal method (i.e. (4 quadrant) * (total electrical tissue 2/3) * (N-1 minimum resistance amount)) to new method, need N unit sizes resistor because be used in the N ohmic resistor of new method, be with many unit sizes of needs resistor, for instance, though in the network of Fig. 2, only illustrate 12 resistors, but before the synthetic 56R of 12 resistor-junctions, need 56 unit sizes resistors, but because the unit sizes resistor is not to be the main region contributor for overall dimensions, so the influence that increase unit sizes resistor is caused promptly can be overcome by the transistorized minimizing of vernier as far as possible, particularly for having the potentiometer of a large amount of taps.
Table two
| The resistance tap | Unit sizes resistive element amount (having) | The vernier transistor (having) of transistor total amount-only | Resistive element amount (new method) | The transmission transistor amount | Vernier and transmission transistor total amount (new method) | Unit sizes resistive element total amount |
| 22 | ?21 | ?22 | ?12 | ?7 | ?13 | ?56 |
| 32 | ?31 | ?32 | ?16 | ?9 | ?17 | ?83 |
| 64 | ?63 | ?64 | ?20 | ?1?1 | ?21 | ?168 |
| 128 | ?127 | ?129 | ?24 | ?13 | ?25 | ?339 |
| 256 | ?255 | ?256 | ?28 | ?15 | ?29 | ?680 |
| 1024 | ?1023 | ?1024 | ?36 | ?19 | ?37 | ?2728 |
What Fig. 4 illustrated is at the comparison diagram that uses on the vernier transistor amount between known method and the new method.Wherein Fig. 4 points out to utilize new method to reduce the situation that comprises the transistorized circuit of vernier with index.
Please refer to Fig. 5, it illustrates is new method according to the configuration impedance network array of the present invention's the 3rd preferred embodiment.The method comprises step 500, optionally connects several first resistance of configuration in mode arranged side by side, wherein resistance be selectively enabling with connection switching device arranged side by side, and these resistance arranged side by side have same resistance value.In step 502, several second resistive elements are to connect in the sequence mode, and wherein each resistive element comprises by the formed equivalent resistance of several first resistance, but the resistance value of the second different resistive elements can be selected with different values.In step 504, second resistive element is to do the mapping configuration with the center of network array, then in step 506, can connect the vernier terminal with selectivity by each resistive element of activation.
Connect the right impedance network of resistance and do to disclose in detail at having several sequences at this, wherein every pair is with connection arranged side by side, and the resistance that connects when sequence is when having unequal value, and the resistance of connection arranged side by side promptly has equal value.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, according to this, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention, and when being used for a variety of modifications and variations.For instance, though when the resistance of sequence connection has unequal value, the resistance that connects can have equal value side by side, and different combinations equal and not constant resistance can also similar fashion be configured with the formation impedance network.Other lifts an example explanation, though promptly present embodiment is to illustrate that to form potentiometer other intend transducer (Digital-to-AnalogConverter as digital revolving die; Be called for short DAC) circuit also can form, in other examples, structure of being familiar with and function do not describe in detail at this, avoiding fuzzy target of the present invention, so protection scope of the present invention defines and is as the criterion when looking accompanying claim.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 02155951 CN1507151B (en) | 2002-12-12 | 2002-12-12 | Variable impedance network for integrated circuits |
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| CN 02155951 CN1507151B (en) | 2002-12-12 | 2002-12-12 | Variable impedance network for integrated circuits |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108809317A (en) * | 2017-05-04 | 2018-11-13 | 亚德诺半导体集团 | Digital analog converter (DAC) terminal |
| CN109036318A (en) * | 2018-09-11 | 2018-12-18 | 惠科股份有限公司 | Driving device and driving method of display panel |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5654679A (en) * | 1996-06-13 | 1997-08-05 | Rf Power Products, Inc. | Apparatus for matching a variable load impedance with an RF power generator impedance |
| US6331768B1 (en) * | 2000-06-13 | 2001-12-18 | Xicor, Inc. | High-resolution, high-precision solid-state potentiometer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108809317A (en) * | 2017-05-04 | 2018-11-13 | 亚德诺半导体集团 | Digital analog converter (DAC) terminal |
| CN108809317B (en) * | 2017-05-04 | 2022-04-05 | 亚德诺半导体国际无限责任公司 | Digital-to-analog converter (DAC) terminal |
| CN109036318A (en) * | 2018-09-11 | 2018-12-18 | 惠科股份有限公司 | Driving device and driving method of display panel |
| WO2020052099A1 (en) * | 2018-09-11 | 2020-03-19 | 惠科股份有限公司 | Driving apparatus and driving method for display panel |
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