CN1503145A - Method for realizing PCI multi-function card - Google Patents
Method for realizing PCI multi-function card Download PDFInfo
- Publication number
- CN1503145A CN1503145A CNA021530122A CN02153012A CN1503145A CN 1503145 A CN1503145 A CN 1503145A CN A021530122 A CNA021530122 A CN A021530122A CN 02153012 A CN02153012 A CN 02153012A CN 1503145 A CN1503145 A CN 1503145A
- Authority
- CN
- China
- Prior art keywords
- bus
- function
- pci
- multifunction
- card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Bus Control (AREA)
Abstract
This invention provides a method for realizing interactive connection of peripheral cells (PCI) with multifunction cards more effectively which is to design bit 7 to be 1 in OEH address header type in its configuration space of master function to utilize the function number of the configuration access to join in PCI configuration register decoding to the generate another function IDSEL# ased in multifunction cards when a configuration register addresses, when another function applies for master equipment bus, the main function of PIC multifunction arbitrates for the bus application and applies for bus to PCI bus so as to realize multifunction card.
Description
Technical field the present invention specifically, is the method that realizes the mutual connecting bus of peripheral component (PCI) multifunction card about a kind of about realizing the method for multifunction card.
Background technology is along with the improve of computer technology, and on personal computer (PC), PCI has substituted ISA gradually, eisa bus becomes the new standard of the local bus of computing machine, even ISA, eisa bus no longer are provided on some personal computer.But because motherboard resources, the PCI slot that provides on personal computer is limited, generally has only 3-6, for ever-increasing configuration requirement, and PCI slot resource some anxiety that just seems relatively.If can on a pci card, realize two or more PCI functions, can save the PCI slot resource of system effectively, reduce the production cost of PCI integrated circuit board factory simultaneously.
In " though PCI local bus standard " agreement to how realizing that the PCI multifunction card has explanation, but owing to realize that PCI's is multi-functional different with the single function of PCI aspect a lot, comprising the multi-functional configuration space decoding of PCI, preventing of main device bus application conflict, the arbitration that bus is used.Therefore, only custom-designed multifunctional circuit, otherwise integrated circuit board production firm can't simply be originally that with two the circuit design for single function pci card design becomes a multi-functional pci card.If row that sticks into for the design of single function wherein once can be improved, make it promptly can use on unifunctional pci card, during simultaneously as multifunction card, another card for single function design simply can be synthesized multifunction card again, more combination is provided for integrated circuit board manufacturer, realizes the variation of product easily.
Summary of the invention the invention provides a kind of method of more effective realization PCI multifunction card for above purpose, and this method comprises:
In the configuration space of the PCI multifunction card function of tonic chord, multi-functional indicating bit, be that position 7 in the leader type field (Header Type) of 0EH address is necessary for 1.
When the configuration register addressing, utilize the function of configuration access number to participate in the decoding of PCI configuration register, produce the configuration register address signal (IDSEL#) of another function that is used for multifunction card;
When multi-functional another function of PCI is carried out the main device bus application, carry out the arbitration of bus application by the multi-functional function of tonic chord of PCI, and carry out the application of bus to pci bus.
Description of drawings has been pointed out theme of the present invention particularly in claims of present patent application, and clearly it has been proposed patent protection.Yet with reference to following detailed description and accompanying drawing, relevant structure that can better understand the present invention and implementation method with and purpose, feature and advantage.
Fig. 1 is the block diagram of the method for realization PCI multifunction card of the present invention;
Fig. 2 is explanation is realized IDSEL2# decoding by function 0 a schematic diagram;
Fig. 3 be the explanation multifunction card carry out the bus filing of the award by function 0.
Specific implementation method has been described specific details and so that provide the present invention has comprehensively been understood in the following detailed description.Yet the professional and technical personnel will appreciate that the present invention also can implement with other similar details.
By " PCI local bus standard " regulation, the PCI function must provide the information of " identity and feature ", therefore, each PCI function, each function that comprises multi-functional pci card all will provide above information by special-purpose " configuration space (Configuration Space) ", with reference to following table.
Byte offset | 32 16 15 0 of sense bit | |||
????00H | Device code (Device ID) | Vendor code (Vendor ID) | ||
????04H | Status word (Status) | Command word (Command) | ||
????08H | Base class code (Base Class Code) | Subclass code (Sub Class Code) | Specified register DLL (dynamic link library) (Prog.I/F) | Revision (Revision ID) |
????0CH | Include self-test (BIST) | Leader type (Header Type) | Time-delay counting (Latency Timer) | Cache memory sizes (Cache Line Size) |
????10H ????14H ????18H ????1CH ????20H ????24H | Base address register (Base Address Register) |
????28H | CardBus bus configuration district register (CardBus CIS Pointer) | |||
????2CH | Subsystem code (Subsystem ID) | Suppliers of the subsystems' code (Subsystem Vendor ID) | ||
????30H | Expansion ROM base address register (Expansion ROM Base Address) | |||
????34H ????38H | Keep (Reserved) | |||
????3CH | Maximum latent time (Max_Lat) | The minimum response time (Min_Gnt) | Interrupt pin number (Interrupt Pin) | Interrupt trunk number (Interrupt Line) |
Last table explanation be information in the configuration space that provides of PCI function, comprising: whether the PCI plug-in card is arranged on the slot; The function that this pci card has (providing) by PCI base class code; The production firm of this PCI plug-in card (providing) by vendor code; Product type (providing) by device code; And this pci card needs configuration and shared computer resource.
By " PCI local bus standard " regulation, the position 7 that is positioned at the leader type field (Head Type) of 0EH byte is used for identifying a multifunctional equipment.If this position is 0 then represents that corresponding apparatus is a single-function device; Otherwise, if 1 this equipment of explanation is multifunctional equipment.Although the invention is not restricted to this, as a specific embodiment of the present invention, this value can be set by the port pin: when external terminal connect high level, this position was 1; When external terminal connect low level, this position was 0.As of the present invention another is embodiment, and this value also can be downloaded (as network card equipment) by external EEPROM when powering in system automatically by being stored in fixed bit among the external EEPROM.Such realization makes this equipment both can work in No. 0 function of multifunctional equipment, can independently be used in single-function device again.
For multifunctional equipment, stipulate according to " PCI local bus standard ", 0 class configuration access can be accepted and respond to requirement, and can accept the function number field that 0 class view is asked configuration, utilize its IDSEL# pin, AD[1:0], and AD[10:8] these three conditions of encoded radio determine whether responding corresponding configuration response.If equipment is multifunctional equipment, must have function No. 0, and second function can be 1~7 any one central number.In the present invention, utilize function No. 0, to IDSEL# pin, AD[1:0], and AD[10:8] encoded radio decipher, produce the required IDSEL2# signal of second function.Although the invention is not restricted to this,, utilize as AD[1:0 as a specific embodiment of the present invention]=00, AD[10:8]=001, during IDSEL#=0, the useful signal of generation IDSEL2# offers the visit that second function is configured function.Fig. 2 offers the specific implementation that the IDSEL2# of second function deciphers.
When two functions of multifunctional equipment can be operated in holotype following time, if bus application signal wire REQ# and GNT# are not arbitrated, will produce bus contention, data manipulation can't be gone on, more serious meeting causes systemic breakdown.Can both carry out normal data transfer operation in order to make two functions, by No. 0 function bus application and acquisition are arbitrated, although the invention is not restricted to this, as a specific embodiment of the present invention, as shown in Figure 3, be responsible for the bus request of this function and function 1 is handled by the pci bus filing of the award logic of No. 0 function inside, here, this moderator adopts the algorithm of fixed mechanism, the bus request that is this function is made as high priority, and the bus request of function 1 is a low priority, when two functions are applied for bus simultaneously, at first obtains bus by function 0.
Though herein declarative description certain this feature of the present invention and a kind of implementation method, for the professional and technical personnel, many modifications, replacement, variation and equivalent substitution will appear.Therefore, protection scope of the present invention is as the criterion by the scope of appended claim.
Claims (2)
1. realize that peripheral component connects the method for (PCI) multifunction card alternately for one kind, this method may further comprise the steps:
-position 7 of the leader type of pci configuration space is made as 1;
-utilize IDSEL#, AD[1:0], AD[10:8] produce the signal wire IDSEL2# that is used for second function is carried out the PCI configuration access;
-with the bus application signal wire (REQ#) of second function as input, and send bus application request to pci bus, after obtaining the bus right to use, bus arbitration logic by function 0 determines the priority that bus is used, and uses affirmation line (GNT2#) to offer second function conflict free bus.
2. a peripheral component connects (PCI) multifunction card alternately, and this card may further comprise the steps:
-position 7 of the leader type of pci configuration space is made as 1;
-utilize IDSEL#, AD[1:0], AD[10:8] produce the signal wire IDSEL2# that is used for second function is carried out the PCI configuration access;
-with the bus application signal wire (REQ#) of second function as input, and send bus application request to pci bus, after obtaining the bus right to use, bus arbitration logic by function 0 determines the priority that bus is used, and uses affirmation line (GNT2#) to offer second function conflict free bus.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB021530122A CN100353347C (en) | 2002-11-25 | 2002-11-25 | Method for realizing PCI multi-function card |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB021530122A CN100353347C (en) | 2002-11-25 | 2002-11-25 | Method for realizing PCI multi-function card |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1503145A true CN1503145A (en) | 2004-06-09 |
CN100353347C CN100353347C (en) | 2007-12-05 |
Family
ID=34234879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB021530122A Expired - Fee Related CN100353347C (en) | 2002-11-25 | 2002-11-25 | Method for realizing PCI multi-function card |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN100353347C (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101101584B (en) * | 2006-07-03 | 2010-12-29 | 索尼株式会社 | Card type peripheral apparatus and host apparatus |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11513150A (en) * | 1995-06-15 | 1999-11-09 | インテル・コーポレーション | Architecture for I / O processor integrating PCI to PCI bridge |
JPH09153009A (en) * | 1995-12-01 | 1997-06-10 | Hitachi Ltd | Arbitration method for hierarchical constitution bus |
US6560663B1 (en) * | 1999-09-02 | 2003-05-06 | Koninklijke Philips Electronics N.V. | Method and system for controlling internal busses to prevent bus contention during internal scan testing |
-
2002
- 2002-11-25 CN CNB021530122A patent/CN100353347C/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101101584B (en) * | 2006-07-03 | 2010-12-29 | 索尼株式会社 | Card type peripheral apparatus and host apparatus |
Also Published As
Publication number | Publication date |
---|---|
CN100353347C (en) | 2007-12-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW379294B (en) | Interfacing direct memory access devices to a non-isa bus | |
US4905182A (en) | Self-configuring memory management system with on card circuitry for non-contentious allocation of reserved memory space among expansion cards | |
CN106557340B (en) | Configuration method and device | |
US7062578B2 (en) | Flexible processing hardware architecture | |
EP0780772A2 (en) | A computer system with multiple PC card controllers and a method of controlling I/O transfers in the system | |
US20060190656A1 (en) | Flexible processing hardware architecture | |
US5056060A (en) | Printed circuit card with self-configuring memory system for non-contentious allocation of reserved memory space among expansion cards | |
CN104615572B (en) | Hot plug processing system and method | |
US4931923A (en) | Computer system for automatically reconfigurating memory space to avoid overlaps of memory reserved for expansion slots | |
US6297817B1 (en) | Computer system with multiple monitor control signal synchronization apparatus and method | |
EP1403814B1 (en) | Electronic apparatus, information processing apparatus, adapter apparatus, and information exchange system | |
CN115167629A (en) | Double-circuit server CPU mainboard | |
Anderson et al. | PCI system architecture | |
TW541462B (en) | Memory map adjustment to support the need of adapters with large memory requirements | |
US5928338A (en) | Method for providing temporary registers in a local bus device by reusing configuration bits otherwise unused after system reset | |
JPH1055331A (en) | Programmable read and write access signal and its method | |
CN1957334B (en) | Mechanism of sequestering memory for a bus device | |
CN100353347C (en) | Method for realizing PCI multi-function card | |
US6826628B2 (en) | PCI-PCMCIA smart card reader | |
CN100517289C (en) | Bus switching circuit | |
CN109144578B (en) | Display card resource allocation method and device based on Loongson computer | |
JPH088134B2 (en) | Common adapter card that plugs into computers with different bus architectures | |
CN112559402A (en) | PCI slave interface control circuit based on FPGA and FPGA | |
AU640850B2 (en) | A printed circuit board | |
TW552507B (en) | Bridge device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071205 Termination date: 20161125 |
|
CF01 | Termination of patent right due to non-payment of annual fee |