CN1503103A - Circuit and method for ID of specific IDE device - Google Patents
Circuit and method for ID of specific IDE device Download PDFInfo
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- CN1503103A CN1503103A CNA021520496A CN02152049A CN1503103A CN 1503103 A CN1503103 A CN 1503103A CN A021520496 A CNA021520496 A CN A021520496A CN 02152049 A CN02152049 A CN 02152049A CN 1503103 A CN1503103 A CN 1503103A
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Abstract
An ID circuit of an designated IDE device includes a host, multiple IDE devices, multiple indicating lamps and multiple controllers, among which, the host includes multiple ID indicating foot positions for designating ID values and an ID design foot position, each said lamp corresponds to one IDE device, the said multiple controllers are connected with the ID indicating foot positions of the host and different IDE device, different indication lamps. The method includes the following steps: firstly, the host designs ID indicating foot position value connected with each controller, then to designate the ID of the said IDE according to the said ID indicating foot position indirectly.
Description
[technical field]
The invention relates to circuit and the method for a kind of assigned I DE device ID, especially about a kind of network attached storage (Network Attached Storage, circuit and method of assigned I DE device ID NAS) of being used for.
[background technology]
Along with the progress of development of computer and science and technology, people are badly in need of from the various local effective resources that obtain.The development of cybertimes, multimedia in addition application, the feasible data information that operates on the different system platform is geometric series and increases rapidly.The storage networking framework at traditional with the server is center has seemed unable to do what one wishes in the face of data stream endlessly.People wish to find a kind of new data model storage, independently go out memory device, have good extendability, availability and reliability simultaneously, to satisfy the requirement of data storage from now on.The former development according to this demand this new types of data memory module of NAS.NAS adopts a plurality of hard disks (HDD) as its external memory usually.
Hard disk generally includes an access media, one group of W head, and one is used to rotate the motor and a circuit board of this access media, and wherein this circuit board is provided with the hard disk controller that a connector is used for hard disk is connected to NAS.Ide interface is one to connect the standard interface of hard disk to the NAS.The hard disk of all IDE of meeting standards promptly is called IDE hard disk (IDE_HDD).The hard disk that is applied to NAS at present is generally the IDE hard disk.In the IDE hard disk array system of a plurality of IDE hard disks of traditional tool, two hard disks are connected to a hard disk controller by same IDE channel, and a hard disk wherein is appointed as Primary Hard Drive by the control signal of computer system, and another then is the subordinate hard disk.
But two above IDE hard disk applications adopt the ID that the circuit of IDE hard disk array system and method can't identification id E hard disk when NAS.
And if adopt more IDE hard disk unit among the NAS, for example, if when being connected with 8 IDE hard disk units, then when it started simultaneously, instantaneous peak current will be up to 16A, and the common power supply can't bear power consumption like this, very easily burn, so a kind of start-up circuit and method of many IDE of delayed startup device need be provided,, guarantee the operate as normal of total system to reduce its power consumption when starting.The start-up circuit of many IDE of this delayed startup device and method are by distributing an ID numerical value for each IDE device, and delay time according to ID numerical value, thereby the IDE device is started successively, avoid the excessive power consumption that causes when starting simultaneously.
[summary of the invention]
Technical matters to be solved by this invention is to provide circuit and the method for a kind of assigned I DE device ID.
The technical solution adopted in the present invention is: circuit and method that a kind of assigned I DE device ID is provided, this circuit comprises a main frame, a plurality of IDE device, a plurality of pilot lamp and a plurality of controller, wherein this main frame comprises that the ID indication pin position and an ID of the ID numerical value of a plurality of IDE of being used to specify devices are provided with the pin position, corresponding this IDE device of each this pilot lamp, these a plurality of controllers all are provided with the pin position with the ID of this main frame and are connected, and the different I D of different with this respectively IDE devices, different pilot lamp and this main frame indication pin position is connected.This method may further comprise the steps: the ID indication pin place value that links to each other with each controller of this main frame setting at first, this main frame meets the ID of this IDE device of appointment according to this ID indication pin interdigit subsequently.
Compared with prior art, the present invention has the following advantages: the present invention is owing to adopt circuit and the method for assigned I DE device ID, make a plurality of IDE hard disk applications system when NAS can allow maintainer or the user ID of identification id E hard disk clearly, and owing to distribute an ID can for each IDE hard disk, thereby can make system can be in response to ID numerical value delayed startup IDE device, thereby the IDE device is started successively, avoid the excessive power consumption that causes when starting simultaneously.
[description of drawings]
Fig. 1 is the circuit block diagram of assigned I DE device ID of the present invention.
Fig. 2 is the physical circuit figure of the circuit of assigned I DE device ID of the present invention.
Fig. 3 is the method flow diagram of assigned I DE device ID of the present invention.
[embodiment]
See also Fig. 1, the IDE device that circuit adopted of assigned I DE device ID of the present invention is the IDE hard disk.Circuit of the present invention comprises a main frame 10,21,22,23,24, four pairs of IDE hard disks 31 and 32 of four controllers, 33 and 34,35 and 36,37 and 38 (per two is a pair of) and first and second power switch 41 of four couples that correspondingly is provided with and 42,43 and 44,45 and 46,47 and the 48 and four pairs of LED light 61 and 62,63 and 64,65 and 66,67 and 68.The a pair of IDE hard disk 31 of its middle controller 21 controls, 32, pair of LEDs pilot lamp 61,62 and first and second power switch 41,42, the a pair of IDE hard disk 33 of controller 22 controls, 34, pair of LEDs pilot lamp 63,64 and first and second power switch 43,44, the a pair of IDE hard disk 35 of controller 23 controls, 36, pair of LEDs pilot lamp 65,66 and first and second power switch 45,46, the a pair of IDE hard disk 37 of controller 24 controls, 38, pair of LEDs pilot lamp 67,68 and first and second power switch 47,48, this circuit also provides a power supply unit 50, and it can be IDE hard disk 31,32,33,34,35,36,37,38 startup provides electric energy.
See also Fig. 2, main frame 10 provides a plurality of pin position and controller 21,22,23,24 to carry out communication switching, wherein four couples of ID indication pin position MON and SON are used for specifying the ID numerical value of coupled controller 21,22,23,24 respectively, thereby controller 21,22,23,24 is specified the ID numerical value of coupled four pairs of IDE hard disks 31 and 32,33 and 34,35 and 36,37 and 38 respectively.One ID is provided with pin position DIDSET/ and links to each other with controller 21,22,23,24 simultaneously, when being low level as if it, represents that then main frame forces controller 21,22,23,24 to enter the state that obtains ID numerical value 10 this moments.
Seeing also Fig. 3, is the process flow diagram of specifying the method for IDE device ID.Step 70 is for starting main frame and controller, promptly start main frame 10 and controller 21,22,23,24, carry out next step 71 then, main frame is provided with the MON and the SON of each controller, be that main frame 10 is provided with controller 21 respectively, 22,23,24 MON and SON, this moment, main frame 10 indicated pin position MON and SON to give controller 21 respectively by four couples of ID, 22,23,24 transmit different MON value and SON value, enter step 72 subsequently, main frame 10 is arranged to low level with DIDSET/ from high level to being less than in 500 milliseconds, enter step 73 subsequently, judge whether DIDSET/ is low level, be that main frame 10 judges whether DIDSET/ is low level, if high level, then return step 73, if low level, then enter next step 74, ID according to MON and SON assigned I DE device, be MON and the SON of main frame 10 according to each set controller, Assign Controller 21,22,23,24 ID, controller 21 subsequently, 22,23,24 are provided with the hard disk 31 and 32 that is attached thereto according to the ID that controls oneself respectively, 33 and 34,35 and 36,37 and 38 ID numerical value, therefore main frame 10 can be according to MON and the indirect setting harddisk 31 of SON, 32,33,34,35,36,37,38 ID numerical value, see table (" 1 ", " 0 " represents MON respectively, the high-low level of SON, " PIC ID " is the ID of controller, " Device ID " is the ID of hard disk), enter step 75 at last, the flow process of assigned I DE device ID finishes.
| ??MON | ??SON | ????PIC?ID | ??Device?ID |
| ????0 | ????0 | ????0 | ????0，1 |
| ????0 | ????1 | ????1 | ????2，3 |
| ????1 | ????0 | ????2 | ????4，5 |
| ????1 | ????1 | ????3 | ????6，7 |
When main frame 10 indirect setting harddisks 31,32,33,34,35,36,37, after 38 the ID numerical value, according to different ID numerical value, give with the corresponding hard disk of this ID numerical value and arrange different time-delays, this hard disc spacer certain hour is started, hard disk 31,33,35,37 startup is by first power switch 41,43,45,47 controls, hard disk 32,34,36,38 startup is by second source switch 42,44,46,48 controls, when with the corresponding hard disk startup of this ID numerical value after, this ID numerical value will be shown in corresponding LED light, with hard disk and its ID numerical value of indication work this moment.
The first embodiment of the present invention adopts is that DIDSET/ triggers during for low level, and right the present invention triggers in the time of also can adopting DIDSET/ for high level.When for example main frame 10 DIDSET/ are set to high level, main frame 10 ability are according to the MON and the SON of each set controller, the ID of Assign Controller 21,22,23,24, controller 21,22,23,24 just is provided with the hard disk 31 and 32 that is attached thereto, 33 and 34,35 and 36,37 and 38 ID numerical value according to the ID that controls oneself respectively subsequently.
Claims (12)
1. the circuit of an assigned I DE device ID, it comprises a main frame, a plurality of controller and a plurality of IDE device, it is characterized in that: this circuit further comprises a plurality of pilot lamp, corresponding this IDE device of each pilot lamp, this main frame comprises that the ID indication pin position and an ID of the ID numerical value of a plurality of IDE of being used to specify devices are provided with the pin position, these a plurality of controllers all are provided with the pin position with the ID of this main frame and are connected, and the different I D of different with this respectively IDE devices, different pilot lamp and this main frame indication pin position is connected.
2. the circuit of assigned I DE device ID as claimed in claim 1 is characterized in that this IDE device is the IDE hard disk.
3. the circuit of assigned I DE device ID as claimed in claim 2 is characterized in that this pilot lamp shows the ID numerical value of IDE hard disk corresponding with it respectively.
4. the circuit of assigned I DE device ID as claimed in claim 3 is characterized in that this ID indication pin position has two.
5. the circuit of assigned I DE device ID as claimed in claim 4 is characterized in that this ID is provided with and represents when the pin position is set to low level can specify the ID of this IDE device according to this ID indication pin position this moment.
6. the circuit of assigned I DE device ID as claimed in claim 4 is characterized in that this ID is provided with and represents when the pin position is set to high level can specify the ID of this IDE device according to this ID indication pin position this moment.
7. the method for an assigned I DE device ID is characterized in that may further comprise the steps:
A., one main frame, a plurality of IDE device, a plurality of pilot lamp and a plurality of controller are provided, wherein this main frame comprises that the ID indication pin position and an ID of the ID numerical value of a plurality of IDE of being used to specify devices are provided with the pin position, corresponding this IDE device of each this pilot lamp, these a plurality of controllers all are provided with the pin position with the ID of this main frame and are connected, and the different I D of different with this respectively IDE devices, different pilot lamp and this main frame indication pin position is connected;
B. the ID that links to each other with each controller of this main frame setting indicates the numerical value of pin position;
C. this main frame meets the ID that specifies this IDE device according to this ID indication pin interdigit.
8. the method for assigned I DE device ID as claimed in claim 7 is characterized in that step c further comprises step:
A. this main frame is specified the ID numerical value of each controller according to the set ID that links to each other with each controller indication pin place value;
B. these a plurality of controllers are provided with the ID numerical value of the IDE device that is attached thereto respectively according to the ID that controls oneself.
9. the method for an assigned I DE device ID is characterized in that may further comprise the steps:
A., one main frame, a plurality of IDE device, a plurality of pilot lamp and a plurality of controller are provided, wherein this main frame comprises that the ID indication pin position and an ID of the ID numerical value of a plurality of IDE of being used to specify devices are provided with the pin position, corresponding this IDE device of each this pilot lamp, these a plurality of controllers all are provided with the pin position with the ID of this main frame and are connected, and the different I D of different with this respectively IDE devices, different pilot lamp and this main frame indication pin position is connected;
B. start this main frame and this controller;
C. the ID that links to each other with each controller of this main frame setting indicates the numerical value of pin position;
D. this main frame is provided with the pin position with ID and is arranged to second state from first state in a predetermined time interval;
E. this main frame judges whether ID is provided with the pin position is second state, if second state, then this main frame meets the ID that specifies this IDE device according to this ID indication pin interdigit, if first state then returns step e.
10. the method for assigned I DE device ID as claimed in claim 9 is characterized in that step
E comprises that further this main frame judges whether ID is provided with the pin position is second state, if second state, then this main frame is according to the set ID that links to each other with each controller indication pin place value, specify the ID numerical value of each controller, these a plurality of controllers are provided with the ID numerical value of the IDE device that is attached thereto respectively according to the ID that controls oneself subsequently, if first state then returns step e.
11. the method for assigned I DE device ID as claimed in claim 10, first state that it is characterized in that steps d and e is a high level, and second state is a low level.
12. the method for assigned I DE device ID as claimed in claim 10, first state that it is characterized in that steps d and e is a low level, and second state is a high level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02152049 CN1220928C (en) | 2002-11-23 | 2002-11-23 | Circuit and method for ID of specific IDE device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02152049 CN1220928C (en) | 2002-11-23 | 2002-11-23 | Circuit and method for ID of specific IDE device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1503103A true CN1503103A (en) | 2004-06-09 |
| CN1220928C CN1220928C (en) | 2005-09-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02152049 Expired - Fee Related CN1220928C (en) | 2002-11-23 | 2002-11-23 | Circuit and method for ID of specific IDE device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1220928C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101995930A (en) * | 2009-08-18 | 2011-03-30 | 索尼公司 | Power supply unit, processing system and distribution method of id identification number |
| CN103645981A (en) * | 2013-11-15 | 2014-03-19 | 华为技术有限公司 | Hard disk identification method and system |
-
2002
- 2002-11-23 CN CN 02152049 patent/CN1220928C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101995930A (en) * | 2009-08-18 | 2011-03-30 | 索尼公司 | Power supply unit, processing system and distribution method of id identification number |
| CN101995930B (en) * | 2009-08-18 | 2013-11-20 | 索尼公司 | Power supply unit, processing system and distribution method of id identification number |
| CN103645981A (en) * | 2013-11-15 | 2014-03-19 | 华为技术有限公司 | Hard disk identification method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1220928C (en) | 2005-09-28 |
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