CN1499634A - CMOS component and preparation method - Google Patents
CMOS component and preparation method Download PDFInfo
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- CN1499634A CN1499634A CNA021502072A CN02150207A CN1499634A CN 1499634 A CN1499634 A CN 1499634A CN A021502072 A CNA021502072 A CN A021502072A CN 02150207 A CN02150207 A CN 02150207A CN 1499634 A CN1499634 A CN 1499634A
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Abstract
The invention relates to CMOS component. Structure of the CMOS includes: setting up material layer of compressive stress or pulling stress on surface of PMOS transistor, and setting up material layer of pulling stress on surface of NMOS transistor. The invention also discloses the method for manufacturing the said CMOS.
Description
Technical field
The present invention relates to a kind of cmos element and manufacture method thereof, particularly a kind of method and structure thereof of utilizing local mechanical Stress Control (local mechanical-stress control is called for short LMC) to increase the usefulness of cmos element.
Background technology
In present semiconductor element, be to use silicon integral body (Si bulk) as substrate, and utilize and dwindle the purpose that component size reaches high speed operation and low power consumption.Yet component size dwindles near the limit of physics and the limit of cost at present.Therefore, other are different from the technology of the method for minification to need development, reach the purpose of high speed operation and low power consumption.
Therefore, the someone proposes to utilize at transistorized channel region the mode of Stress Control, overcomes the limit of element downsizing.The method is to change the Si spacing of lattice by applied stress, increases the mobility in electronics and hole.
Common method places Si-Fe layer (being in tensile stress) to go up the channel layer of the silicon layer (tensile-strained Si layer) of tensile stress as nmos pass transistor for using, and the germanium-silicon layer (compressive-strained Si-Ge layer) (being in compression stress) of use compressive tension is as the transistorized channel layer of PMOS.The Si layer by using tensile stress and the Si-Ge layer of compressive tension can increase the mobility in surface electronic and hole, and reach the purpose of high speed operation and the consume of low bear amount simultaneously as the channel layer of MOS transistor.
Yet, there are some problems in this technology, when the Si-Ge layer (p channel layer) of Si layer (n channel layer) that forms tensile stress simultaneously and compressive tension during as the channel layer of CMOS, it is very complicated that manufacture process can become, and to want selectivity to form NMOS channel layer and PMOS channel layer be suitable difficulty.And, when forming the Si-Ge layer by high-temperature heat treatment, the separation (segregation) of difference row (dislocation) or generation Ge can take place, and make the characteristic degradation of grid breakdown voltage.
In addition, have research and utilization to produce stress as the silicon nitride layer that contact hole etching stops layer recently, influence the transistor electric current of tending to act, this technology is called the local mechanical Stress Control.Yet when the mechanical stretching stress of silicon nitride layer increased, the electric current of tending to act of n channel layer can increase, but but caused the reduction of the electric current of tending to act of p channel layer.And, when silicon nitride layer.When stress became compression stress, its phenomenon was then opposite.Therefore, must make trade-offs the electric current that improves the n channel layer or the electric current of p channel layer.
Existing research is pointed out to utilize and is optionally implanted the Ge ion and improve the electric current of n channel layer and the electric current of p channel layer simultaneously to the above-mentioned silicon nitride layer, as A.Shimizu et al., " LocalMechanical-Stress Control (LMC): A New Technique for CMOS-PerformanceEnhancement ", IEDM Tech.Dig., p.247,2001.Below will cooperate Figure 1A to Figure 1B and Fig. 2 A to Fig. 2 B to describe this technology in detail.
Figure 1A and Figure 1B are the schematic diagrames of the method for the electric current of expression raising p channel layer and the current characteristics deterioration of avoiding the n channel layer.Shown in Figure 1A, deposition one deck has the silicon nitride layer 106 of high compression stress (highly compressive stress) in the substrate 100 that forms nmos pass transistor 102 and PMOS transistor 104, and the method for deposition is an electricity slurry enhanced chemical vapor deposition method (plasma-enhancedCVD).Then shown in Figure 1B, on PMOS transistor 104, cover photoresist layer 108, then the Ga ion is implanted in the silicon nitride layer 106, and transfers silicon nitride layer 106b to, thereby reduce the stress of the silicon nitride layer 106b of nmos pass transistor 102 tops, worsen with the current characteristics of avoiding the n channel layer.And the silicon nitride layer 106a that PMOS transistor 104 tops cover, because of having high compression stress, so can improve the electric current of p channel layer.
Fig. 2 A and Fig. 2 B are the schematic diagrames of the method for the electric current of expression raising n channel layer and the current characteristics deterioration of avoiding the p channel layer.Shown in Fig. 2 A, deposition one deck has the silicon nitride layer 206 of high tensile stress (highly tensile stress) in the substrate 200 that forms nmos pass transistor 202 and PMOS transistor 204, and the method for deposition is thermal chemical vapor deposition method (thermal CVD).Then shown in Figure 1B, on nmos pass transistor 202, cover photoresist layer 208, then the Ga ion is implanted in the silicon nitride layer 206, and transfers silicon nitride layer 206b to, stress so as to the silicon nitride layer 206b that reduces PMOS transistor 204 tops worsens with the current characteristics of avoiding the p channel layer.And the silicon nitride layer 206a that nmos pass transistor 202 tops cover, because of having high tensile stress, so can improve the electric current of n channel layer.
Though the above-mentioned method of utilizing silicon nitride layer generation stress to improve performance of transistors uses the method for Si-Ge resilient coating simple, but it can only be used to promote the electric current of tending to act of PMOS transistor or nmos pass transistor, and can't improve the electric current of tending to act of PMOS transistor or nmos pass transistor simultaneously.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of cmos element and manufacture method thereof, can promote the usefulness of PMOS transistor and nmos pass transistor simultaneously.
For realizing goal of the invention of the present invention, the invention provides a kind of cmos element, its structure comprises is located at PMOS transistor surface with compression or tensile stress material layer, and the tensile stress material layer is located at the nmos pass transistor surface.
The present invention also provides a kind of manufacture method of cmos element, and its method is summarized as follows.At first, provide substrate with first active region and second active region and form first conductive-type transistor and second conductive-type transistor respectively at first active region and second active region.Then, on first and second conductive-type transistors, form first stressor layers, wherein first conductive-type transistor is PMOS transistor and nmos pass transistor either-or, when first conductive-type transistor is the PMOS transistor, then first stressor layers is a compressive stress layers, when first conductive-type transistor is a nmos pass transistor, then first stressor layers is a tension stress layer.Afterwards, on first stressor layers, form a stress-buffer layer.Remove the stress-buffer layer and first stressor layers, the stress-buffer layer and first stressor layers are covered on first conductive-type transistor of first active region corresponding to second active region.Then on second conductive-type transistor and stress-buffer layer, form second stressor layers, wherein working as second conductive-type transistor is nmos pass transistor, then second stressor layers is a tension stress layer, and when second conductive-type transistor is the PMOS transistor, then second stressor layers is a compressive stress layers.Remove second stressor layers at last, and remove remaining stress-buffer layer corresponding to first active region.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, an embodiment cited below particularly, and conjunction with figs. is described in detail below:
Figure 1A and Figure 1B are the schematic diagrames of the method for the electric current of expression tradition raising p channel layer and the current characteristics deterioration of avoiding the n channel layer;
Fig. 2 A and Fig. 2 B are the schematic diagrames of the method for the electric current of expression tradition raising n channel layer and the current characteristics deterioration of avoiding the p channel layer;
Fig. 3 A to Fig. 3 G illustrates a kind of schematic diagram of manufacture method of cmos element according to an embodiment of the invention;
Fig. 4 illustrates the length of channel region and the definition of width.
Embodiment
The invention provides a kind of structure of cmos element, shown in Fig. 3 G, its structure comprises respectively to be located at PMOS transistor 304 and nmos pass transistor 302 among the n wellblock NW and p wellblock PW of substrate 300, and respectively compressive stressed materials layer 310a and tensile stress material layer 320a is located at PMOS transistor 304 surface and nmos pass transistor 302 surfaces.
It should be noted that the material that is covered in PMOS transistor 304 tops can be compressive stressed materials or tensile stress material, is to be example with compressive stressed materials layer 310a in this specification.
In addition, compressive stressed materials layer 310a and tensile stress material layer 320a are covered at least respectively on the source electrode and drain electrode of PMOS transistor 304 and nmos pass transistor 302, in the accompanying drawings and be to be that example is done explanation compressive stressed materials layer 310a and tensile stress material layer 320a are covered in whole PMOS transistor 304 surfaces and whole nmos pass transistor 302 surfaces respectively in the specification.
Roughly between 0.05 micron to 1 micron, passage length L (seeing Fig. 3 G and Fig. 4) is roughly between 20 nanometer to 60 nanometers for the channel width W (see figure 4) of above-mentioned PMOS transistor 304 and nmos pass transistor 302.Wherein, Fig. 4 is meant PMOS transistor 304 and nmos pass transistor 302 layouts.
The thickness of the above-mentioned PMOS transistor 304 and the grid oxic horizon 301 of nmos pass transistor 302 is roughly between 8 dusts and 15 dusts.
In addition, the operating voltage of PMOS transistor 304 and nmos pass transistor 302 is roughly between 0.5 volt to 1.2 volts.
Utilization influences the tension force of the channel layer of PMOS transistor 304 at PMOS transistor 304 surface coverage one deck compressive stressed materials layer 310a, to increase the hole carrier in the mobility of channel region.
And, influence the tension force of the channel layer of nmos pass transistor 302 simultaneously by at nmos pass transistor 302 surface coverage one deck tensile stress material layer 320a, to increase the electronics carrier in the mobility of channel region.
Fig. 3 A to Fig. 3 G is the schematic diagram that illustrates a kind of manufacture method of above-mentioned cmos element.
At first please refer to Fig. 3 A, a substrate 300 is provided, substrate 300 has active region AA1 and AA2.Wherein this active region AA1 and AA2 are used in the substrate 300 to form the isolated component structure and define, for example shallow trench isolation element STI.
Then, form first conductive-type transistor and second conductive-type transistor respectively at active region AA1 and AA2.Being referred to as with first conductivity type and second conductivity type at this, is to represent that both are opposite for conductivity, promptly are respectively p type and n type.Therefore, first conductive-type transistor and second conductive-type transistor can be respectively PMOS transistor and nmos pass transistor, and be perhaps opposite.Be to be example in this embodiment to form nmos pass transistor 302 in active region AA1 and to form PMOS transistor 304 in active region AA2.
Then please refer to Fig. 3 B, form the ground floor stressor layers on PMOS transistor 304 and nmos pass transistor 302, this stressor layers can be compressive stress layers or tension stress layer, is to be example to cover compressive stress layers 310 earlier at this embodiment.
The material of this compressive stress layers 310 can be the silicon nitride (SiN that is rich in silicon
X), x=0.6-1.0) or silicon oxynitride (SiON), its thickness is roughly between 100 dusts () and 500 dusts, its formation method can be sedimentation, brilliant method of heap of stone or electricity slurry sedimentation, by the condition that control forms, can adjust the stress intensity of formed rete, according to research, the factor of may command stress has gas ratio in temperature, pressure or the manufacture method, if electricity slurry sedimentation, then the factor of may command stress also comprises electricity slurry electric power (plasmapower).
With electricity slurry sedimentation is example, form the required temperature of compressive stress layers 310 roughly between 300 ℃ and 500 ℃, required pressure is roughly between 1.0 Bristols (torr) and 1.5 Bristols (torr), and required electricity slurry electric power is roughly between between 1000 watts (W) and 2000 watts.Is example with silicon nitride as the material of compressive stress layers 310, and gas can be NH in its manufacture method
3: SiH
4, ratio is roughly 4-10.
Then please refer to Fig. 3 C, on compressive stress layers 310, form one deck stress-buffer layer 312.The material of this stress-buffer layer 312 can be silica (SiO
2), thickness is roughly between 50 dusts and 500 dusts.
Then please refer to Fig. 3 D, form one deck photoresist layer 314 on stress-buffer layer 312, this photoresist layer 314 exposes the zone corresponding to nmos pass transistor 302.
Be mask with this photoresist layer 314 then, counter stress resilient coating 3 12 and compressive stress layers 310 are carried out etching, make it transfer stress-buffer layer 312a and the compressive stress layers 310a that exposes nmos pass transistor 302 to.At this moment, the stress-buffer layer 312a and the compressive stress layers 310a that stay roughly are covered on the PMOS transistor 304.Afterwards, remove photoresist layer 314.
Then please refer to Fig. 3 E, go up the stressor layers that forms the second layer in nmos pass transistor 302 and stress-buffer layer 312a.At this embodiment, this stressor layers is a tension stress layer 320.If above-mentioned ground floor stressor layers is a tension stress layer, then second layer stressor layers is a compressive stress layers
The material of this tension stress layer 320 can be the silicon nitride (SiN that is rich in nitrogen
X), x=1.0-0.3), be rich in the silicon nitride (SiN of silicon
XX=0.6-1.0) or silicon oxynitride (SiON), its formation method can be sedimentation, brilliant method of heap of stone or electricity slurry sedimentation, condition by control formation, can adjust the stress intensity of formed rete, according to research, the factor of may command stress has gas ratio in temperature, pressure or the manufacture method, if electricity slurry sedimentation, then the factor of may command stress also comprises electricity slurry electric power.
(Rapid Thermal deposition) is example with the Rapid Thermal sedimentation, forms the required temperature of tension stress layer 820 roughly between 300 ℃ and 800 ℃, and required pressure is roughly between 150 Bristols and 300 Bristols.Is example with silicon nitride as the material of tension stress layer 320, and gas can be NH in its manufacture method
3: SiH
4, ratio is roughly 50-400; Perhaps gas can be dichlorosilane (dichlorosilane, SiH in its manufacture method
2Cl
2, be called for short DCS): NH
3, ratio is roughly 0.1-1.
Then please refer to Fig. 3 F, form one deck photoresist layer 324 on tension stress layer 320, this photoresist layer 324 exposes the zone corresponding to PMOS transistor 304.
Be mask then, tension stress layer 320 is carried out etching, make it transfer the tension stress layer 320a that exposes corresponding to the zone of PMOS transistor 304 to this photoresist layer 324.Afterwards, remove photoresist layer 324 and stress-buffer layer 312a.Therefore, the PMOS transistor 304 that is positioned at active region AA2 is covered under the compressive stress layers 310a, and the nmos pass transistor 302 that is positioned at active region AA1 is covered under the tension stress layer 320a, shown in Fig. 3 G.
In sum, utilize method provided by the present invention, can in substrate, form the PMOS transistor and the nmos pass transistor of characteristic simultaneously with high speed operation and low-yield consume.
Claims (12)
1. cmos element is characterized in that it comprises:
One substrate;
An one PMOS transistor and a nmos pass transistor are located in this substrate; And
One tensile stress material layer is located on the source electrode and drain electrode of this PMOS transistor and this nmos pass transistor at least, and wherein the transistorized operating voltage of this nmos pass transistor and PMOS is between 0.5 volt to 12 volts.
2. cmos element as claimed in claim 1 is characterized in that, the channel width of described PMOS transistor and this nmos pass transistor between 0.05 micron to 1 micron, passage length between 0.5 micron between 10 nanometers.
3. the manufacture method of a cmos element is characterized in that, it comprises:
One substrate is provided, and this substrate has one first active region and one second active region;
Form one first conductive-type transistor and one second conductive-type transistor respectively at this first active region and this second active region;
On this first and second conductive-type transistor, form one first stressor layers, wherein this first conductive-type transistor is PMOS transistor and nmos pass transistor either-or, when this first conductive-type transistor is the PMOS transistor, then this first stressor layers is a compressive stress layers, when this first conductive-type transistor is a nmos pass transistor, then this first stressor layers is a tension stress layer;
On this first stressor layers, form a stress-buffer layer;
Remove this stress-buffer layer and this first stressor layers, this stress-buffer layer and this first stressor layers are covered on this plan one conductive-type transistor of this first active region corresponding to this second active region;
On this second conductive-type transistor and this stress-buffer layer, form one second stressor layers, wherein working as this second conductive-type transistor is nmos pass transistor, then this second stressor layers is a tension stress layer, when this second conductive-type transistor is the PMOS transistor, then this second stressor layers is a compressive stress layers;
Remove this second stressor layers corresponding to this first active region; And
Remove this stress-buffer layer.
4. the manufacture method of cmos element as claimed in claim 3 is characterized in that, the formation method of described compressive stress layers is to select in the group that unhindered settling method, brilliant method of heap of stone and electricity slurry sedimentation form.
5. the manufacture method of cmos element as claimed in claim 3, it is characterized in that, the formation method of described compressive stress layers is an electricity slurry sedimentation, utilize electricity slurry sedimentation to form the required temperature of this compressive stress layers between 300 ℃ and 500 ℃, pressure is between 1.0 Bristols and 1.5 Bristols, and electricity slurry electric power is between 1000 watts and 2000 watts.
6. the manufacture method of cmos element as claimed in claim 3 is characterized in that, the material of described compressive stress layers is the silicon nitride (SiN that selects free silicon oxynitride (SiON) and be rich in silicon
X, x=0.6-1.0) in the group that is formed.
7. the manufacture method of cmos element as claimed in claim 3 is characterized in that, the material of described compressive stress layers is the silicon nitride (SiN that is rich in silicon
X, x=0.6-1.0), form that gas is NH in the manufacture method of this compressive stress layers
3: SiH
4, ratio is 4-10.
8. the manufacture method of cmos element as claimed in claim 3 is characterized in that, the formation method of described tension stress layer is to select freely to build in the group that brilliant method, electricity slurry sedimentation and Rapid Thermal sedimentation formed.
9. the manufacture method of cmos element as claimed in claim 3, it is characterized in that, the formation method of described tension stress layer is the Rapid Thermal sedimentation, utilize the Rapid Thermal sedimentation to form the required temperature of this tension stress layer between 300 ℃ and 800 ℃, pressure is between 150 Bristols and 300 Bristols.
10. the manufacture method of cmos element as claimed in claim 3, the material that it is characterized in that described tension stress layer is the silicon nitride (SiN that selects free silicon oxynitride (SiON) and be rich in nitrogen
X, x=1.0-1.3) in the group that is formed.
11. the manufacture method of cmos element as claimed in claim 3 is characterized in that, the material of described tension stress layer is the silicon nitride (SiN that is rich in silicon
X, x=0.6-1.0), form that gas is NH in the manufacture method of this tension stress layer
3: SiH
4, ratio is 50-400.
12. the manufacture method of cmos element as claimed in claim 3 is characterized in that, the material of described tension stress layer is the silicon nitride (SiN that is rich in silicon
X, x=0.6-1.0), form that gas is DCS: NH in the manufacture method of this tension stress layer
3, ratio is 0.1-1.
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| CN 02150207 CN1245760C (en) | 2002-11-04 | 2002-11-04 | CMOS component and preparation method |
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| CN 02150207 CN1245760C (en) | 2002-11-04 | 2002-11-04 | CMOS component and preparation method |
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Cited By (12)
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| CN100353525C (en) * | 2004-12-31 | 2007-12-05 | 台湾积体电路制造股份有限公司 | Strained channel cmos device with fully silicided gate electrode and its forming method |
| CN100411175C (en) * | 2004-11-30 | 2008-08-13 | 国际商业机器公司 | Structure and method of applying stresses to PFET and NFET transistor channels for improved performance |
| CN100428491C (en) * | 2005-01-12 | 2008-10-22 | 国际商业机器公司 | Integrate circuit and method producing same |
| CN100527421C (en) * | 2006-04-28 | 2009-08-12 | 国际商业机器公司 | CMOS structures and methods using self-aligned dual stressed layers |
| CN100585833C (en) * | 2005-03-01 | 2010-01-27 | 国际商业机器公司 | Method and structure for forming self-aligned, dual stress liner for CMOS devices |
| US7781277B2 (en) | 2006-05-12 | 2010-08-24 | Freescale Semiconductor, Inc. | Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit |
| CN101375379B (en) * | 2005-12-14 | 2010-09-01 | 飞思卡尔半导体公司 | Semiconductor device having stressors and method for forming |
| US7803718B2 (en) | 2007-03-13 | 2010-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture |
| CN101233605B (en) * | 2005-07-27 | 2013-04-24 | 格罗方德半导体公司 | Methods for fabricating a stressed MOS device |
| US8527933B2 (en) | 2011-09-20 | 2013-09-03 | Freescale Semiconductor, Inc. | Layout technique for stress management cells |
| CN103367364A (en) * | 2012-03-27 | 2013-10-23 | 中国科学院微电子研究所 | CMOS and method for fabricating the same |
| CN112103190A (en) * | 2020-11-03 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Structure of semiconductor device and preparation method thereof |
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2002
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| CN100411175C (en) * | 2004-11-30 | 2008-08-13 | 国际商业机器公司 | Structure and method of applying stresses to PFET and NFET transistor channels for improved performance |
| CN100353525C (en) * | 2004-12-31 | 2007-12-05 | 台湾积体电路制造股份有限公司 | Strained channel cmos device with fully silicided gate electrode and its forming method |
| CN100428491C (en) * | 2005-01-12 | 2008-10-22 | 国际商业机器公司 | Integrate circuit and method producing same |
| CN100585833C (en) * | 2005-03-01 | 2010-01-27 | 国际商业机器公司 | Method and structure for forming self-aligned, dual stress liner for CMOS devices |
| CN101233605B (en) * | 2005-07-27 | 2013-04-24 | 格罗方德半导体公司 | Methods for fabricating a stressed MOS device |
| TWI413216B (en) * | 2005-07-27 | 2013-10-21 | Globalfoundries Us Inc | Methods for fabricating a stressed mos device |
| CN101375379B (en) * | 2005-12-14 | 2010-09-01 | 飞思卡尔半导体公司 | Semiconductor device having stressors and method for forming |
| CN100527421C (en) * | 2006-04-28 | 2009-08-12 | 国际商业机器公司 | CMOS structures and methods using self-aligned dual stressed layers |
| US7781277B2 (en) | 2006-05-12 | 2010-08-24 | Freescale Semiconductor, Inc. | Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit |
| CN101266969B (en) * | 2007-03-13 | 2011-06-08 | 台湾积体电路制造股份有限公司 | BiCMOS component |
| US7803718B2 (en) | 2007-03-13 | 2010-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture |
| US8527933B2 (en) | 2011-09-20 | 2013-09-03 | Freescale Semiconductor, Inc. | Layout technique for stress management cells |
| CN103367364A (en) * | 2012-03-27 | 2013-10-23 | 中国科学院微电子研究所 | CMOS and method for fabricating the same |
| CN103367364B (en) * | 2012-03-27 | 2015-12-09 | 中国科学院微电子研究所 | CMOS and method for fabricating the same |
| CN112103190A (en) * | 2020-11-03 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Structure of semiconductor device and preparation method thereof |
| CN112103190B (en) * | 2020-11-03 | 2021-02-19 | 晶芯成(北京)科技有限公司 | Structure of semiconductor device and preparation method thereof |
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