CN1495800A - Nonvolatile semiconductor storage capable of reducing storage unit data error read-out rate - Google Patents

Nonvolatile semiconductor storage capable of reducing storage unit data error read-out rate Download PDF

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Publication number
CN1495800A
CN1495800A CNA031787177A CN03178717A CN1495800A CN 1495800 A CN1495800 A CN 1495800A CN A031787177 A CNA031787177 A CN A031787177A CN 03178717 A CN03178717 A CN 03178717A CN 1495800 A CN1495800 A CN 1495800A
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voltage
node
channel mos
mos transistor
nonvolatile semiconductor
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三原雅章
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Renesas Technology Corp
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Renesas Technology Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

In a semiconductor device according to the invention, a transistor Tr1 operating as a current source supplying a memory cell with a current is configured to operate in a saturation range when a node N3 subjected to a decision as to whether a memory cell has a High or Low level has a voltage in a range of no more than a threshold voltage.

Description

Reduce the Nonvolatile semiconductor memory device of memory cell data mistake read rate
Technical field
The present invention relates to reduce the Nonvolatile semiconductor memory device of the data mistake read rate of storage unit.
Background technology
According to the storage data level, in the sensing circuit of transistor with threshold voltage variation, used so-called discharge-type sensing circuit and electric current and detected the type circuit as the Nonvolatile semiconductor memory device of storage unit.
Give one example, in the discharge-type sensing circuit, when reading the content of storage unit, be called L (low) when level is read when flowing through the reading of content of storage unit of electric current hardly.On the other hand, be called H (height) when level is read in the time of can flowing through the reading of content of the storage unit of Duoing than the electric current of transistorized saturation region, this transistor is the transistor (hereinafter referred to as current source transistor) that is connected with the node of judging H, L level, move as current source.As a result, the discharge-type sensing circuit can be judged H, the L level of storage unit.
But the current source transistor that uses in traditional discharge-type sensing circuit may not have been considered the appropriateness of its actuating range, thereby has the danger that data are misread out.Specifically, when the L level was read, traditional discharge-type sensing circuit had noise owing on the data line, or the charging distribution takes place, the voltage that may cause judging the node of H, L level descends, and the saturation current of the current ratio current source transistor that current source transistor provides is little.At this moment, current source transistor is in linear zone work, thereby the danger that has data to misread out.
Figure 11 is the structural drawing of traditional discharge-type sensing circuit.As shown in figure 11, traditional discharge-type sensing circuit, promptly Nonvolatile semiconductor memory device 106 comprises: the memory cell array 1 that contains a plurality of storage unit (not shown); When data were read, response clock signal CNT was electrically connected the N-channel MOS transistor NM1 of node N3 and node N4; Be arranged between power source voltage Vcc and the N-channel MOS transistor NM1, play the P channel MOS transistor Tr15 of electric current source transistor effect; As input, make the negative circuit of exporting after the voltage of signals level inversion of input 3 with the link node of P channel MOS transistor Tr15 and N-channel MOS transistor NM1.
Memory cell array 1 comprises word line, bit line, wordline decoder and the bit line decoder (not shown) that is used for selecting from a plurality of storage unit a storage unit.Threshold voltage with P channel MOS transistor Tr15 is made as 0.6V, and it is that example describes that the threshold voltage of negative circuit 3 is made as 1.5V.
N-channel MOS transistor NM1 is connected with memory cell array 1 via node N4.Provide the grid of the P channel MOS transistor Tr15 of persistent current to be connected with ground voltage GND usually.
In order not to be subject to The noise, node N3 designs enough shortly.And node N4 is connected between N-channel MOS transistor NM1 and the memory cell array 1, thereby long more a lot of than node N3 usually.Among node N3 and the node N4 stray capacitance C2 and C1 are arranged respectively, the relation of C1 greater than C2 arranged.In addition, power source voltage Vcc is 3V.
Figure 12 is that the k value that the electric current as expression P channel MOS transistor Tr15 flows through complexity is 1.2 μ A/V 2The time, the family curve T1a of the characteristic of expression P channel MOS transistor Tr15.The longitudinal axis is represented the current value that P channel MOS transistor Tr15 flows through.Transverse axis is represented the voltage of node N3.
From the family curve T1a of Figure 12 as can be known: the current value (saturation current) that P channel MOS transistor Tr15 flows through in the saturation region is 7.2 μ A.In addition, on family curve T1a, P channel MOS transistor Tr15 with than the little voltage of 0.6V in saturation region operation, with than the big voltage of 0.6V in linear zone work.
Below by Figure 11 and Figure 12 H, the action of Nonvolatile semiconductor memory device 106 when the L level is read are described.During sense data, the voltage of node N3 is not 3V.
When the H level is read, be that example describes with the maximum electric current of the storage unit of selecting a plurality of storage unit in memory cell array (hereinafter referred to as selected cell) by 10 μ A.Being judged to be of the H of output OUT, L level:, then be the H level if the threshold voltage of the voltage ratio negative circuit 3 of node N3 is little; If the threshold voltage of the voltage ratio negative circuit 3 of node N3 is big, then be the L level.
Therefore when data were read, the saturation current of P channel MOS transistor Tr15 was 7.2 μ A, and it is many to flow through the magnitude of current of select storage unit from transistor Tr 15.Thereby the voltage of judging the node 3 of H, L level drops to and is almost 0.
Thereby it is littler than the threshold voltage 1.5V of negative circuit that the voltage of node N3 becomes, and output OUT becomes the H level.
Suppose that node N4 has noise, or the charging distribution take place that even the threshold voltage 1.5V of the voltage ratio negative circuit 3 of node N3 is low, output OUT still is the H level, therefore can not misread out between node N3 and node N4.
When the L level was read, select storage unit passed through electric current hardly.Leakage current values with select storage unit is that 0.1 μ A is that example describes.
When data were read, select storage unit only flow through 0.1 μ A electric current, therefore, judged that the voltage of the node N3 of H, L level descends hardly, was about 3V.
At this moment, suppose that node N4 has noise, or the charging distribution has taken place between node N3 and the node N4.As a result, the voltage of node N3 descends, and P channel MOS transistor Tr15 transient flow has been crossed the electric current between 6 μ A and the 7.2 μ A, and this electric current makes P channel MOS transistor Tr15 in linear zone work.After this phenomenon took place, it is littler than the threshold voltage 1.5V of negative circuit 3 that the voltage of node N3 becomes, although thereby should read the L level data, export OUT and become the H level, misreading out of data taken place.
As mentioned above, in traditional Nonvolatile semiconductor memory device, owing to do not consider the suitable gate voltage level of current source transistor, result especially, the node voltage of judging H, L level is in the following scope of threshold voltage the time, and this current source triode has the tendency in linear zone work.Therefore, when the L level is read,, judge that the voltage of the node of voltage becomes below threshold voltage because charging distributes or the saturation current of the current ratio current source transistor that the noise of data line etc. caused pass through hour.The possibility of misreading out that this phenomenon makes traditional Nonvolatile semiconductor memory device carry out the data of storage unit increases.
Summary of the invention
The object of the present invention is to provide: when the L level is read, even be subjected to the influence of the noise to data line, the distribution of charging etc., cause current source transistor to provide saturation current following electric current, the Nonvolatile semiconductor memory device of misreading out of data can not take place yet.
The present invention includes a plurality of storage unit, data line, read amplifying circuit and the 1st voltage setting circuit.When data line is read in data, be electrically connected with a unit of from a plurality of storage unit, selecting.Read amplifying circuit detects data line when data are read electric current.Read amplifying circuit and be included in data provide electric current when reading to data line the 1st current source.The 1st current source comprises the 1st inner node that is connected with data line when data are read, is connected electrically to the 1st transistor between the 1st inner node and the supply voltage.Read amplifying circuit and also be included in data when reading, relatively the voltage of the 1st inner node and the 1st change-over circuit of the 1st threshold voltage.The 1st voltage setting circuit is set the 1st transistorized grid voltage, so that during the scope of the voltage of the 1st inner node below the 1st threshold voltage, the 1st transistor is in saturation region operation.
Thereby, the main advantage of the present invention is: form such structure, during the scope of the voltage of the inside node by differentiating H, L level below threshold voltage, in saturation region operation, can realize to reduce the Nonvolatile semiconductor memory device of mistake read rate of the data of storage unit as the transistor of the current source action of reading amplifying circuit.
Description of drawings
Fig. 1 is the structural drawing of the Nonvolatile semiconductor memory device of embodiments of the invention 1.
Fig. 2 is the figure of the characteristic of the P channel MOS transistor Tr1 that uses in the Nonvolatile semiconductor memory device of the present invention of expression.
Fig. 3 is the figure of the characteristic of the N-channel MOS transistor Tr 4 used in the Nonvolatile semiconductor memory device of the present invention of expression and P channel MOS transistor Tr5.
Fig. 4 is the figure of the characteristic of the P channel MOS transistor Tr2 that uses in the Nonvolatile semiconductor memory device of the present invention of expression and N-channel MOS transistor Tr 3.
Fig. 5 is the structural drawing of the Nonvolatile semiconductor memory device of embodiments of the invention 2.
Fig. 6 is the structural drawing of the Nonvolatile semiconductor memory device of embodiments of the invention 3.
Fig. 7 is the structural drawing of the Nonvolatile semiconductor memory device of embodiments of the invention 4.
Fig. 8 is the structural drawing of the Nonvolatile semiconductor memory device of embodiments of the invention 5.
Fig. 9 is the figure of the characteristic of the N-channel MOS transistor Tr 6 used in the Nonvolatile semiconductor memory device of the present invention of expression and P channel MOS transistor Tr8.
Figure 10 is the structural drawing of the Nonvolatile semiconductor memory device of embodiments of the invention 6.
Figure 11 is the structural drawing of traditional Nonvolatile semiconductor memory device.
Figure 12 is the figure of the characteristic of the P channel MOS transistor Tr15 that uses in the traditional Nonvolatile semiconductor memory device of expression.
Embodiment
Below, with reference to drawing embodiments of the invention are described.Same-sign is represented identical or suitable part among the figure.
Embodiment 1
With reference to Fig. 1, the Nonvolatile semiconductor memory device 100 of the embodiment of the invention 1 comprises the memory cell array 1 that contains a plurality of storage unit, reads amplifying circuit 10 and voltage setting circuit 20.
Memory cell array 1 comprises: P channel MOS transistor ATr0, ATr1; P channel MOS transistor YTr0, YTr1～YTr16; Non-volatile memory cells FM0, FM1～FM16; Word line WL0; Bit line BL0, BL1～BL16.Formation in this memory cell array 1 only is an example, and practical structure often is made of more P channel MOS transistor, non-volatile memory cells, word line and bit line.
The source electrode of P channel MOS transistor ATr0 and ATr1 is connected with node N4.The drain electrode of P channel MOS transistor ATr0 is connected with the source electrode of P channel MOS transistor YTr0, YTr1～YTr15 respectively.The drain electrode of P channel MOS transistor YTr0, YTr1～YTr16 is connected with bit line BL0, BL1～BL16 respectively.Bit line BL0, BL1～BL16 are connected with the drain electrode of non-volatile memory cells FM0, FM1～FM16 respectively.Word line WL0 is connected with the control grid of non-volatile memory cells FM0, FM1～FM16 respectively.The drain electrode of P channel MOS transistor ATr1 is connected with the source electrode of P channel MOS transistor YTr16.
P channel MOS transistor ATr0 and P channel MOS transistor YTr0, YTr1～YTr15 have following function: the non-volatile memory cells of the hope that the bit line of wishing among response clock selection signal AD0, bit line select signal YS0～YS15 and the word line selection signal WS0, selection and BL0, BL1～BL15 is connected.
Reading amplifying circuit 10 comprises: when data are read, and response clock signal CNT, the N-channel MOS transistor NM1 that node N3 and node N4 are electrically connected; Be arranged between power source voltage Vcc and the N-channel MOS transistor NM1, play the P channel MOS transistor Tr1 of electric current source transistor effect; With the link node of P channel MOS transistor Tr1 and N-channel MOS transistor NM1 as input, with the negative circuit 3 of the voltage level of input anti-phase back output.Threshold voltage with setting P channel MOS transistor Tr1 is 0.6V, and the threshold value of negative circuit 3 is that 1.5V is that example describes.
N-channel MOS transistor NM1 is connected with memory cell array 1 via node N4.When node N4 is equivalent to data and reads and a data line that is electrically connected in a plurality of storage unit.
Voltage setting circuit 20 comprises: P channel MOS transistor Tr2 that is connected in series between power source voltage Vcc and ground voltage GND and N-channel MOS transistor Tr 3; P channel MOS transistor Tr5 that between power source voltage Vcc and ground voltage GND, is connected in series and N-channel MOS transistor Tr 4.Voltage setting circuit 20 is set at the grid voltage of P channel MOS transistor Tr1 the value of hope in addition.
The grid of P channel MOS transistor Tr2 is connected with ground voltage GND.The grid of P channel MOS transistor Tr3 is connected with the link node N1 of the grid of N-channel MOS transistor Tr 4 with P channel MOS transistor Tr2 and N-channel MOS transistor Tr 3.The grid of P channel MOS transistor Tr5 is connected with the link node N2 of P channel MOS transistor Tr5 and N-channel MOS transistor Tr 4 and the grid of P channel MOS transistor Tr1.
In order not to be subject to The noise, node N2 and N3 are designed to enough weak points.And node N4 is connected with memory cell array 1, therefore usually than node N2,3 length a lot.Among node N3 and the node N4 stray capacitance C2 and C1 are arranged respectively, the relation of C1 greater than C2 arranged.In addition, power source voltage Vcc is 3V.
Below, the method for designing of determining the characteristics of transistor in P channel MOS transistor Tr1 and the voltage setting circuit 20 is described, so that the voltage of the node N3 that is connected with the P channel MOS transistor Tr1 that plays the current source effect, judge H, L level is when the following scope of threshold voltage of negative circuit 3, P channel MOS transistor Tr1 is in saturation region operation.
Being made as 0.6V with the threshold voltage with P channel MOS transistor Tr1, Tr2, Tr5 and N-channel MOS transistor Tr 3, Tr4 is example.
Even the voltage of node N3 is below the threshold voltage of negative circuit 3, P channel MOS transistor Tr1 in the required bottom line condition of saturation region operation is: the grid voltage of P channel MOS transistor Tr1 and the value of threshold voltage addition are bigger than the threshold voltage 1.5V of negative circuit 3.Therefore, the grid voltage of P channel MOS transistor Tr1 and the value of threshold voltage addition are designed to: increase 0.6V as tolerance limit on the threshold voltage 1.5V of negative circuit 3, become 2.1V.Promptly be designed to: if the voltage of node N3 is littler than 2.1V, then P channel MOS transistor Tr1 is in saturation region operation.
When the voltage of node N3 was 2.1V, the threshold voltage of P channel MOS transistor Tr1 was 0.6, and therefore, the voltage of node N2 becomes 1.5V.In the saturation region, the electric current I ds that flows to P channel MOS transistor Tr1 passes through
Ids＝k(Vgs-Vth) 2 ...(1)
Obtain.Ids is the current value that flows through in the saturation region.K is that the expression value is big more, can flow through just big more desired value of transistorized electric current.Vgs is the voltage between gate-to-source.Vth is a threshold voltage.
The electric current that flows through 7.2 μ A with P channel MOS transistor Tr1 when the saturation region operation is an example.In Ids=7.2, Vgs=-1.5, Vth=-0.6 difference substitution (1) formula, try to achieve k=8.9.Thereby can be as shown in Figure 2, decision selects that to have the k value be 8.9 μ A/V for use 2The P channel MOS transistor Tr1 of family curve T1 characteristic.
Among Fig. 2, transverse axis is represented the voltage of node N3.The longitudinal axis is represented the current value that P channel MOS transistor Tr1 flows through.Can know that from family curve if the voltage ratio 2.1V of node N3 is little, then P channel MOS transistor Tr1 is in saturation region operation.
Below, use the P channel MOS transistor Tr5 with the identical k value of P channel MOS transistor Tr1, so that it is equal to flow through the electric current of P channel MOS transistor Tr1 and P channel MOS transistor Tr5.Grid and the drain short circuit of P channel MOS transistor Tr5, so the family curve of P channel MOS transistor Tr5 is expressed as the family curve T5 of Fig. 3.
Among Fig. 3, transverse axis is represented the voltage of node N2.The longitudinal axis is represented the current value that N-channel MOS transistor Tr 4 and P channel MOS transistor Tr5 flow through.
The voltage of node N2 is 1.5V, determines the k value and the Vgs of N-channel MOS transistor Tr 4 with this, so that the intersection point of the family curve T4 of family curve T5 and N-channel MOS transistor Tr 4 is 1.5V.Here, be that the 1.2V of design is an example with the voltage of node N1.Therefore the voltage of node N2 is 1.5V, and can draw the current value that N-channel MOS transistor Tr 4 flows through in the saturation region from family curve T5 is 7.2 μ A.In Ids=7.2 μ A, Vgs=1.2V, Vth=0.6 difference substitution (1) formula, try to achieve k=20.Thereby can be as shown in Figure 3, decision selects that to have the k value be 20 μ A/V for use 2The N-channel MOS transistor Tr 4 of family curve T4 characteristic.
Below, use the N-channel MOS transistor Tr 3 with N-channel MOS transistor Tr 4 identical k values, so that it is equal to flow through the electric current of N-channel MOS transistor Tr 4 and N-channel MOS transistor Tr 3.The grid of P channel MOS transistor Tr2 is connected with ground voltage GND, so the voltage of node N1 is the 3V of power source voltage Vcc.Thereby the Vgs=3V of P channel MOS transistor Tr3.Thereby the family curve of P channel MOS transistor Tr3 is expressed as the family curve T3 of Fig. 4.
Among Fig. 4, transverse axis is represented the voltage of node N1.The longitudinal axis is represented the current value that P channel MOS transistor Tr2 and N-channel MOS transistor Tr 3 flow through.
The voltage of node N1 is the 1.2V of design, therefore can obtain the k value of P channel MOS transistor Tr2, so that the intersection point of the family curve T2 of family curve T3 and P channel MOS transistor Tr2 is 1.2V.When the voltage of node N1 is 1.2V, learn that by family curve T3 the electric current that flows to N-channel MOS transistor Tr 3 is 6.5 μ A.At linear zone, when the voltage of node N1 was 1.2V, the electric current that flows to P channel MOS transistor Tr2 can be used
Ids＝k((Vgs-Vth) 2-(Vgd-Vth) 2) ...(2)
Obtain.In Ids=6.5, Vgs=-3, Vth=-0.6, Vgd=-1.2 difference substitution (2) formula, try to achieve k=1.2.Thereby can be as shown in Figure 4, decision selects that to have the k value be 1.2 μ A/V for use 2The P channel MOS transistor Tr2 of family curve T2 characteristic.
Above method can be determined the characteristics of transistor in P channel MOS transistor Tr1 and the voltage setting circuit 20.
Below, by Fig. 1 and Fig. 2 H, the action of Nonvolatile semiconductor memory device 100 when the L level is read are described.During sense data, the voltage of node N3 is not 3V.
When the H level is read, same with traditional Nonvolatile semiconductor memory device 106, misreading out of data do not taken place, the therefore no longer detailed description of repetitive operation.
When the L level was read, select storage unit did not almost have electric current to flow through.Being made as 0.1 μ A with the leakage current values of select storage unit is that example describes.
When data were read, select storage unit only flow through the electric current of 0.1 μ A, so the voltage of node N3 descends hardly, was about 3V.At this moment, suppose that node N4 has noise, or the charging distribution takes place between node N3 and the node N4, the result, the voltage of node N3 descends, and the current direction node N3 littler than the saturation current 7.2 μ A of P channel MOS transistor Tr1 arranged.At this moment, the voltage of node N3 can be not little at the boundary voltage 2.1V of saturation region and linear zone compared with the P channel MOS transistor Tr1 of current source effect.Thereby the voltage of node N3 can be as traditional Nonvolatile semiconductor memory device 106, and is littler than the threshold voltage 1.5V of negative circuit, therefore misreading out of data can not taken place.
As described above, in the Nonvolatile semiconductor memory device 100 of embodiment 1, the grid voltage of current source transistor is set to suitable value, so that in the scope of node voltage below threshold voltage that is connected with the P channel MOS transistor Tr1 that plays the effect of electric current source transistor, judge H, L level the time, current source transistor is in saturation region operation.As a result, even on the data sense wire noise is arranged, or take place that charging distributes etc., produce the electric current littler than the saturation current of current source transistor, misreading out of select storage unit can not taken place.
Embodiment 2
With reference to Fig. 5, the Nonvolatile semiconductor memory device 101 of embodiments of the invention 2 compares with the Nonvolatile semiconductor memory device of embodiment 1 100, and following difference is arranged: memory cell array is split into a plurality of memory cell blocks; Also have voltage setting circuit 20a and 20b with voltage setting circuit 20 identical formations; Also have with read amplifying circuit 10 identical formations read amplifying circuit 10a and 10b.In addition formation is identical with Nonvolatile semiconductor memory device shown in Figure 1 100, no longer repeats detailed explanation.
Read amplifying circuit 10a and compare with reading amplifying circuit 10 with 10b, following difference is arranged: corresponding with output signal OUT is respectively output signal OUTa and OUTb; Corresponding with node N2 is respectively node N2a and N2b; Corresponding with node N4 is respectively node N4a and N4b.In addition formation no longer repeats detailed explanation with shown in Figure 1 to read amplifying circuit 10 identical.
A plurality of memory cell blocks have a plurality of storage unit respectively.In addition, memory cell array 1 comprises that a plurality of storage unit that are used in a plurality of memory cell blocks select word line, bit line, wordline decoder and the bit line decoder (not shown) of a storage unit.
The grid of P channel MOS transistor Tr5 in voltage setting circuit 20,20a and the 20b is via node N2, N2a and N2b, respectively with read amplifying circuit 10,10a and 10b in the grid of P channel MOS transistor Tr1 be connected. Read amplifying circuit 10,10a and 10b via node N4, N4a and N4b, be connected with a memory cell block in these a plurality of memory cell blocks respectively.When data are read, node N4, N4a and N4b respectively with these a plurality of memory cell blocks in a memory cell block in a plurality of storage unit in one be electrically connected.
In order not to be subject to The noise, node N2, N2a and N2b and node N3, N3a and N3b are designed to enough weak points.Node N4, N4a and N4b be owing to is connected with memory cell array 1, thereby much longer than node N2, N2a and N2b and node N3, N3a and N3b respectively usually.
Voltage setting circuit 20,20a and 20b set suitable value to the grid voltage of reading the P channel MOS transistor Tr1 in amplifying circuit 10,10a and the 10b respectively, even so that with read amplifying circuit 10,10a and 10b in play at least one node among that the P channel MOS transistor Tr1 of electric current source transistor effect is connected, as to judge H, L level node N3, N3a and the N3b voltage below threshold voltage, the P channel MOS transistor Tr1 that reads in amplifying circuit 10,10a and the 10b also can be similarly to Example 1 respectively in saturation region operation.
Below, the action of the Nonvolatile semiconductor memory device 101 when the L level is read is described.Read the data that amplifying circuit 10,10a and 10b read the select storage unit in the interior a plurality of storage unit of a corresponding memory cell block respectively.In the Nonvolatile semiconductor memory device 101, the action of data of reading select storage unit respectively is identical with the Nonvolatile semiconductor memory device 100 of embodiment 1, therefore no longer repeats detailed explanation.
As described above, in the Nonvolatile semiconductor memory device 101 of embodiment 2, the output destination of the data of the select storage unit in a plurality of storage unit of each memory cell block in a plurality of memory cell blocks of Nonvolatile semiconductor memory device 101 has a plurality of, therefore can read the data of a plurality of storage unit simultaneously.
In addition, in the Nonvolatile semiconductor memory device 101, respectively the grid voltage of current source transistor Tr1 is set suitable value, so that when the voltage of at least one node was in the following scope of the threshold voltage of negative circuit 3 among the node N3, the N3a that are connected with current source transistor Tr1 in reading amplifying circuit 10,10a and 10b, judge H, L level and the N3b, current source transistor Tr1 was respectively in saturation region operation.As a result, even on the data sense wire noise is arranged, or take place that charging distributes etc., produce the electric current littler than the saturation current of current source transistor, misreading out of select storage unit can not taken place.
Embodiment 3
With reference to Fig. 6, the Nonvolatile semiconductor memory device 102 of embodiments of the invention 3 compares with the Nonvolatile semiconductor memory device of embodiment 2 101, following difference is arranged: do not have voltage setting circuit 20a and 20b; Node N2 respectively with read amplifying circuit 10a and 10b in the grid of P channel MOS transistor Tr1 be connected.In addition formation is identical with Nonvolatile semiconductor memory device shown in Figure 5 101, no longer repeats detailed explanation.
The grid of the P channel MOS transistor Tr5 of voltage setting circuit 20 is via node N2, respectively with read amplifying circuit 10,10a and 10b in the grid of P channel MOS transistor Tr1 be connected.That is, voltage setting circuit 20 distributes voltage via node N2 to reading amplifying circuit 10,10a and 10b.Usually node N2 is long more a lot of than the node N2 of the Nonvolatile semiconductor memory device 101 of embodiment 2.
Voltage setting circuit 20 is set suitable value to the grid voltage of reading the P channel MOS transistor Tr1 in amplifying circuit 10,10a and the 10b respectively, even so that with read amplifying circuit 10,10a and 10b in current source transistor be the voltage of at least one node among that P channel MOS transistor Tr1 is connected, as to judge H, L level node N3, N3a and the N3b below the threshold voltage of negative circuit 3, the P channel MOS transistor Tr1 that reads in amplifying circuit 10,10a and the 10b also can be similarly to Example 1 respectively in saturation region operation.
The action of the Nonvolatile semiconductor memory device 102 when the L level is read is identical with the Nonvolatile semiconductor memory device 100 of embodiment 1, no longer repeats detailed explanation.
As described above, in the Nonvolatile semiconductor memory device 102 of embodiment 3, distribute voltage to a plurality of amplifying circuits of reading by node N2.As a result because the common wiring long enough of node N2, thereby with Nonvolatile semiconductor memory device 101 relatively, have the shortcoming of antinoise difference.
But, Nonvolatile semiconductor memory device 102 is compared with Nonvolatile semiconductor memory device 101, is to connect a plurality of amplifying circuits of reading respectively on a voltage setting circuit.Thereby Nonvolatile semiconductor memory device 102 is same with Nonvolatile semiconductor memory device 101, can read a plurality of data simultaneously.And the voltage setting circuit of Nonvolatile semiconductor memory device 102 is one.Therefore compare with the Nonvolatile semiconductor memory device 101 that possesses a plurality of voltage setting circuits, can realize dwindling of circuit area.
Embodiment 4
With reference to Fig. 7, the Nonvolatile semiconductor memory device 103 of embodiments of the invention 4 compares with the Nonvolatile semiconductor memory device of embodiment 3 102, and following difference is arranged: voltage setting circuit 24 replaces voltage setting circuits 20; Also be provided with voltage setting circuit 21, voltage setting circuit 21a, voltage setting circuit 21b, current source 25, current source 25a, current source 25b.In addition formation is identical with Nonvolatile semiconductor memory device shown in Figure 6 102, no longer repeats detailed explanation.
Voltage setting circuit 24 comprises P channel MOS transistor Tr2 and the N-channel MOS transistor Tr 3 that is connected in series between power source voltage Vcc and the ground voltage GND.The medium voltage that voltage setting circuit 24 generates between power source voltage Vcc and the ground voltage GND.
Current source 25,25a and 25b comprise N-channel MOS transistor Tr 4, N-channel MOS transistor Tr 4a and N-channel MOS transistor Tr 4b respectively. Current source 25,25a and 25b provide electric current to voltage setting circuit 21,21a and 21b respectively according to the medium voltage that voltage setting circuit 24 generates.
N-channel MOS transistor Tr 4, Tr4a and Tr4b move as current source.N-channel MOS transistor Tr 4, Tr4a and Tr4b are arranged at respectively between node N5, N5a and N5b and the ground voltage GND.
The grid of P channel MOS transistor Tr2 in the voltage setting circuit 24 is connected with ground voltage GND.The grid of N-channel MOS transistor Tr 3 is connected with the link node N1 of P channel MOS transistor Tr2 and N-channel MOS transistor Tr 3 and each grid of N-channel MOS transistor Tr 4, Tr4a and Tr4b respectively.
Voltage setting circuit 21,21a and 21b are provided with P channel MOS transistor Tr5 respectively between power source voltage Vcc and node N5, N5a and N5b.The grid of P channel MOS transistor Tr5 in voltage setting circuit 21,21a and the 21b is connected with the grid of P channel MOS transistor Tr1 in reading amplifying circuit 10,10a and 10b with the drain electrode of P channel MOS transistor Tr5 respectively.
The drain electrode of N-channel MOS transistor Tr 4, Tr4a and Tr4b in current source 25,25a and the 25b is via node N5, N5a and N5b, is connected with the drain electrode of P channel MOS transistor Tr5 in voltage setting circuit 21,21a and the 21b respectively.That is, the N-channel MOS transistor Tr 4, Tr4a and the Tr4b that play the effect of electric current source transistor are via node N5, N5a and N5b, and the P channel MOS transistor Tr5 in voltage setting circuit 21,21a and 21b provides electric current respectively.
Voltage setting circuit 21,21a and 21b set suitable value to the grid voltage of current source transistor respectively, even so that with read amplifying circuit 10,10a and 10b in play at least one node among that the P channel MOS transistor Tr1 of electric current source transistor effect is connected, as to judge H, L level node N3, N3a and the N3b voltage below the threshold voltage of negative circuit 3, P channel MOS transistor Tr1 is also respectively in saturation region operation.
The action of the Nonvolatile semiconductor memory device 103 when the L level is read is identical with the Nonvolatile semiconductor memory device 100 of embodiment 1, no longer repeats detailed explanation.
As described above, compare with Nonvolatile semiconductor memory device 102, in the Nonvolatile semiconductor memory device 103 of embodiment 4, comprise voltage setting circuit 21a and 21b, N-channel MOS transistor Tr 4a and Tr4b again, therefore had circuit area can become big shortcoming.
But, Nonvolatile semiconductor memory device 103 provides electric current to voltage setting circuit 21,21a and 21b via node N5, N5a and N5b respectively by current source 25,25a and 25b. Voltage setting circuit 21,21a and 21b to respectively read amplifying circuit 10,10a and 10b near node N2, N2a and N2b setting voltage respectively.Distribute the Nonvolatile semiconductor memory device 103 of current system to compare, have the advantage of the anti-noise sound intensity with the Nonvolatile semiconductor memory device 102 that distributes voltage system.
Embodiment 5
With reference to Fig. 8, the Nonvolatile semiconductor memory device 104 of embodiments of the invention 5 compares with the Nonvolatile semiconductor memory device of embodiment 1 100, and following difference is arranged: read amplifying circuit 11 replacements and read amplifying circuit 10; Also has negative circuit; Node N1 in the voltage setting circuit 20 is connected with negative circuit 3a.In addition formation is identical with Nonvolatile semiconductor memory device shown in Figure 1 100, no longer repeats detailed explanation.
Read amplifying circuit 11 and compare with reading amplifying circuit 10, difference is not contain negative circuit 3.In addition formation no longer repeats detailed explanation with shown in Figure 1 to read amplifying circuit 10 identical.
Negative circuit 3a comprises the P channel MOS transistor Tr8 that is connected in series between power source voltage Vcc and the ground voltage GND and N-channel MOS transistor Tr 7, Tr6.P channel MOS transistor Tr8 moves as current source.N-channel MOS transistor Tr 6 is identical with the characteristic of N-channel MOS transistor Tr 4.The threshold voltage of P channel MOS transistor Tr8 is 0.6V.
The grid of P channel MOS transistor Tr8 is connected with drain electrode with the grid of N-channel MOS transistor Tr 7 respectively with drain electrode.The grid of P channel MOS transistor Tr8 is connected with node N3 with the link node of the grid of N-channel MOS transistor Tr 7.The grid of N-channel MOS transistor Tr 6 is connected with node N1.The voltage of node N1, N2 is identical with embodiment 1, is respectively 1.2,1.5V.Power source voltage Vcc is 3V in addition.The logic threshold voltage of negative circuit 3a is 1.5V.
Below, the method for designing of the characteristic of determining the P channel MOS transistor Tr8 in the negative circuit 3a is described, so that data are when reading, even the voltage of the node N3 of Nonvolatile semiconductor memory device 104 is below the threshold voltage of negative circuit 3a, the P channel MOS transistor Tr8 that plays the effect of electric current source transistor is also in saturation region operation.
With reference to Fig. 9, N-channel MOS transistor Tr 6 is identical with the characteristic of N-channel MOS transistor Tr 4, and therefore, the k value of N-channel MOS transistor Tr 6 is the family curve T6 identical with the family curve T4 of Fig. 3 with family curve.Thereby the magnitude of current that N-channel MOS transistor Tr 6 can flow through in the saturation region is 7.2 μ A.
Among Fig. 9, transverse axis is represented the voltage of node N3.The longitudinal axis represents to flow through the current value of P channel MOS transistor Tr8 and N-channel MOS transistor Tr 6.
The logic threshold voltage of negative circuit 3a is 1.5V, and when the voltage that therefore designs node N3 was 1.5V, P channel MOS transistor Tr8 was in saturation region operation.Thereby, be set at 1.5V as if voltage, then the Vgs=-1.5V of P channel MOS transistor Tr8 with node N3.The possible magnitude of current that flows through N-channel MOS transistor Tr 6 is restricted to 7.2 μ A, therefore, in Ids=7.2, Vgs=-1.5, Vth=-0.6 difference substitution (1) formula, tries to achieve k=8.9.Thereby can be as shown in Figure 9, decision selects that to have the k value be 8.9 μ A/V for use 2The P channel MOS transistor Tr8 of family curve T8 characteristic.
Below by Fig. 8 and Fig. 9, the action of the Nonvolatile semiconductor memory device 104 when the L level is read is described.During sense data, the voltage of node N3 is not 3V.Select storage unit in the memory cell array 1 does not almost have electric current to flow through.It is that example describes that the current value that may flow through with select storage unit is made as 0.1 μ A.
When data were read, select storage unit only flow through the electric current of 0.1 μ A, so the voltage of node N3 descends hardly, was about 3V.At this moment, suppose that node N4 has noise, or the charging distribution takes place between node N3 and the node N4.As a result, the voltage of node N3 descends, and the current direction node N3 littler than the saturation current 7.2 μ A of P channel MOS transistor Tr8 arranged.At this moment, the voltage of node N3 can be not little at the boundary voltage 2.1V of saturation region and linear zone compared with the P channel MOS transistor Tr8 of current source effect.Thereby the voltage of node N3 can be as traditional Nonvolatile semiconductor memory device 106, and is littler than the threshold voltage 1.5V of negative circuit, therefore misreading out of data can not taken place.
As described above, in the Nonvolatile semiconductor memory device 104 of embodiment 5, in the time of in the scope of node voltage below the threshold voltage of negative circuit 3a that is connected with P channel MOS transistor Tr8 as current source transistor, judge H, L level, the P channel MOS transistor Tr8 that plays the effect of electric current source transistor is in saturation region operation.As a result, even on the data sense wire noise is arranged, or take place that charging distributes etc., produce the little electric current of saturation current compared with the P channel MOS transistor Tr8 of current source effect, misreading out of select storage unit can not taken place.
Embodiment 6
With reference to Figure 10, the Nonvolatile semiconductor memory device 105 of embodiments of the invention 6 compares with the Nonvolatile semiconductor memory device of embodiment 1 100, and following difference is arranged: read amplifying circuit 11 replacements and read amplifying circuit 10; Also have with the voltage setting circuit 20a of voltage setting circuit 20 identical formations, with read amplifying circuit 11 identical formations read amplifying circuit 11a, differential amplifier circuit 40 and non-volatile memory cells 31.In addition formation is identical with Nonvolatile semiconductor memory device shown in Figure 1 100, no longer repeats detailed explanation.
Voltage setting circuit 20a compares with voltage setting circuit 20, and corresponding with node N1 is node N1a, and corresponding with node N2 is node N2a.Read amplifying circuit 11a and compare with reading amplifying circuit 11, corresponding with node N3 is node N3a, and corresponding with node N4 is node N4a.
Differential amplifier circuit 40 comprises current source 26, be connected in series in P channel MOS transistor Tr10 and N-channel MOS transistor Tr 11 between power source voltage Vcc and the current source 26, be connected in series in P channel MOS transistor Tr12 and N-channel MOS transistor Tr 13 between power source voltage Vcc and the current source 26.If the voltage of node N3 and N3a is different, then the signal OUT of differential amplifier circuit 40 is the H level.
The grid of P channel MOS transistor Tr10 is connected with the link node of P channel MOS transistor Tr10 and N-channel MOS transistor Tr 11 and the grid of P channel MOS transistor Tr12.The grid of N-channel MOS transistor Tr 11 is connected with node N3.The grid of N-channel MOS transistor Tr 13 is connected with node N3a.The link node output signal OUT of P channel MOS transistor Tr12 and N-channel MOS transistor Tr 13.
In order not to be subjected to easy The noise, node N2 and node N2a, node N3 and node N3a and node N4a design enough shortly respectively.Node N4 is connected with memory cell array 1, and is therefore long a lot of than node N2 and node N2a, node N3 and node N3a and node N4a usually.
Determine the characteristic of non-volatile memory cells 31 and the voltage of Vcc2, so that non-volatile memory cells 31 as the current source action, makes this current source flow through and reads the interior identical current value 7.2 μ A of saturation current that play the P channel MOS transistor Tr1 of current source effect of amplifying circuit 11a.
The action of the Nonvolatile semiconductor memory device 105 when the following describes the L level and reading.During sense data, the voltage of node N3 and node N3a is not 3V.Select storage unit in the memory cell array 1 does not almost have electric current to flow through.The current value that may flow through with select storage unit is that 0.1 μ A is that example describes.
When data were read, select storage unit only flow through the electric current of 0.1 μ A, so the voltage of node N3 descends hardly, was about 3V.In addition, the current value that flows to node N4 is 0.1 μ A.And non-volatile memory cells 31 can flow through the electric current of 7.2 μ A, so the decline of the voltage of node N3a, for example becomes 1V.
Thereby the voltage of node N3 and node N4 has potential difference (PD), and output OUT is the H level.At this moment, outside noise is arranged on the node N4, or the charging distribution takes place between node N3 and the node N4, the voltage of node N3 descends, and the current direction node N3 littler than the saturation current 7.2 μ A of P channel MOS transistor Tr1 arranged.At this moment, similarly to Example 1, it is little at the boundary voltage 2.1V of saturation region and linear zone that the voltage of node N3 can not liken the P channel MOS transistor Tr1 that moves into current source to.Thereby the voltage of node N3a is 1V, therefore by the action of differential amplifier circuit 40, misreading out of data can not taken place.
As described above, the Nonvolatile semiconductor memory device 105 of embodiment 6 is when the L level is read, and has the structure of the potential difference (PD) of regulation at the voltage of node N3 and node N3a.In addition, in the Nonvolatile semiconductor memory device 105, grid voltage to current source transistor is set suitable value, so that in the scope of voltage below threshold voltage of the node that is connected with the P channel MOS transistor Tr1 that plays the effect of electric current source transistor, judge H, L level the time, current source transistor is in saturation region operation.As a result, even on the data sense wire noise is arranged, or take place that charging distributes etc., produce the electric current littler than the saturation current of current source transistor, misreading out of select storage unit can not taken place.

Claims (8)

1, a kind of Nonvolatile semiconductor memory device comprises:
A plurality of storage unit;
Data line, a unit of selecting when data are read and in described a plurality of storage unit is electrically connected;
Read amplifying circuit, when described data are read, detect the electric current of described data line,
The described amplifying circuit of reading is included in described data provide electric current when reading to described data line the 1st current source,
Described the 1st current source has the 1st inner node that is connected with described data line and is connected electrically to the 1st transistor between the described the 1st inner node and the supply voltage when described data are read,
The described amplifying circuit of reading also is included in the voltage of described data more described the 1st inner node when reading and the 1st change-over circuit of the 1st threshold voltage;
Described Nonvolatile semiconductor memory device also comprises the 1st voltage setting circuit of setting described the 1st transistorized grid voltage, so that during the scope of the voltage of described the 1st inner node below described the 1st threshold voltage, described the 1st transistor is in saturation region operation.
2, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:
Described the 1st transistor is the P channel MOS transistor,
Described the 1st threshold voltage of voltage ratio after described grid voltage adds the above the 1st transistorized threshold voltage is big.
3, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:
Described the 1st voltage setting circuit is a current mirror circuit.
4, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:
Described a plurality of storage unit is split into a plurality of,
Each described is disposed described data line, described amplifying circuit and described the 1st voltage setting circuit read respectively.
5, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:
Described a plurality of storage unit is split into a plurality of,
Each described is disposed described data line and the described amplifying circuit of reading respectively, and described the 1st voltage setting circuit is described a plurality of and has.
6, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that also comprising:
The intermediate potential generation circuit of the medium voltage between the 2nd voltage setting circuit, the 2nd current source, generation supply voltage and the ground voltage,
Described a plurality of storage unit is split into a plurality of,
Each described is disposed described data line and the described amplifying circuit of reading respectively,
Each described is disposed described the 2nd voltage setting circuit and described the 2nd current source respectively,
Described the 2nd voltage setting circuit is set the described the 1st transistorized grid voltage respectively, so that during the scope of the voltage that described each piece described read at least one node in the described the 1st inner node in the amplifying circuit below the 1st threshold voltage, the described the 1st of described each piece is read interior described the 1st transistor of amplifying circuit in saturation region operation
Described the 2nd current source provides the electric current of described medium voltage correspondence respectively to described a plurality of the 2nd voltage setting circuits.
7, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:
Described the 1st change-over circuit comprises: the 3rd current source is used for providing electric current to described data line when described data are read; Current limit circuit is accepted the electric current of described the 3rd current source, and electric current is restricted to the predetermined electric current amount;
Described the 3rd current source comprises the 2nd transistor that is connected electrically between the described the 1st inner node and described supply voltage,
During the scope of the voltage of described the 1st inner node below described the 1st threshold voltage, described the 2nd transistor is in saturation region operation.
8, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that also comprising:
The 4th current source provides the electric current with described the 1st transistor par when described data are read;
The comparing data line, when described data are read and described the 4th current source be electrically connected;
The 5th current source is electrically connected with described data line,
Described the 4th current source comprises the 2nd inner node that is connected with described comparing data line when described data are read and is connected electrically to the 3rd transistor between the described the 2nd inner node and the supply voltage,
Described Nonvolatile semiconductor memory device also comprises:
The 3rd voltage setting circuit is set the described the 3rd transistorized grid voltage, so that in the scope of the voltage of described the 2nd inner node below described the 1st threshold voltage the time, the transistor of described the 3rd voltage is in saturation region operation;
Differential amplifier circuit is used to detect the voltage difference of the described the 1st inner node and described the 2nd inner node,
Described the 5th current source goes out electric current with described the 3rd transistor par from described comparing data linear flow,
When described data were read, a unit of described selection was according to storing data, electric current that the electric current that provides than described the 1st transistor from described data line outflow is big or little electric current.
CNA031787177A 2002-07-15 2003-07-15 Nonvolatile semiconductor storage capable of reducing storage unit data error read-out rate Pending CN1495800A (en)

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CN101650971A (en) * 2008-08-12 2010-02-17 精工电子有限公司 Non-volatile semiconductor memory circuit

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US8693272B2 (en) * 2011-06-30 2014-04-08 Qualcomm Incorporated Sensing circuit
CN103366804B (en) 2012-03-30 2017-10-13 硅存储技术公司 The Nonvolatile memory devices of sense amplifier are injected with electric current
EP3107102A1 (en) * 2015-06-18 2016-12-21 EM Microelectronic-Marin SA Memory circuit
KR102511901B1 (en) * 2016-04-11 2023-03-20 에스케이하이닉스 주식회사 Nonvolatile memory device having wide operation range

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CN101650971A (en) * 2008-08-12 2010-02-17 精工电子有限公司 Non-volatile semiconductor memory circuit
CN101650971B (en) * 2008-08-12 2014-05-07 精工电子有限公司 Non-volatile semiconductor memory circuit

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