CN1492491A - Method for producing polycrystalline base plate with conductive salient block and its conductive salient block - Google Patents
Method for producing polycrystalline base plate with conductive salient block and its conductive salient block Download PDFInfo
- Publication number
- CN1492491A CN1492491A CNA021462941A CN02146294A CN1492491A CN 1492491 A CN1492491 A CN 1492491A CN A021462941 A CNA021462941 A CN A021462941A CN 02146294 A CN02146294 A CN 02146294A CN 1492491 A CN1492491 A CN 1492491A
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- Prior art keywords
- conductive
- substrate
- manufacture method
- copper
- covering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Electroplating Methods And Accessories (AREA)
Abstract
A compound crystal baseplate with conductive projectors and its manufacturing method includes: providing a compound with multiconducting points on the surface covered by a conductive film with a photoresist layer formed on it, patterning the photoresist layer to form multiple open-ends on the base surface exposing the multiple conducting points under it, plating copper to fill in the open-ends to form multiple copper projectors, removing the photoresist layer and the film, forming an anti-welding protection layer on the baseplate surface to expose the copper projectors to be dealt with anti-oxidation on the surface.
Description
Invention field
The invention relates to base plate for packaging, especially in regard to a kind of manufacture method that has brilliant substrate of covering of conductive projection and conductive projection thereof with the plating mode manufacturing.
Background of invention
Extensive use ball grid array (Ball Grid Array is hereinafter to be referred as BGA) is packaged in the encapsulation (packaging) of integrated circuit wafer set or graphical wafer etc. at present.Generally speaking, the BGA encapsulation is main to form most tin balls at the back side of a substrate, and arranges at substrate back in the grid array mode, as the pin between wafer and printed circuit board (PCB), substitutes conductive metal frames in the past.The advantage of BGA encapsulation is that under same size, number of pins can increase, and the pin between pin is apart from also strengthening.In addition, because the BGA encapsulation is shortened the conductive path between printed circuit board (PCB) and wafer, so its radiating effect and also lifting thereupon of conductivity.
Along with the package size is dwindled, and the trend that pin count increases day by day, (F1ip chip on BGA FCBGA) then becomes one of main technology packet to crystal covering type ball grid array package.Crystal covering type ball grid array package is that an integrated circuit chip back surface is connected with a substrate, and this substrate is connected with a printed circuit board (PCB) with ball grid array.Because crystal covering type ball grid array (FCBGA) therefore has the saving space in conjunction with covering brilliant and two kinds of encapsulation technologies of ball grid array, and can hold advantage such as more number of pins.
As shown in Figure 1, be traditional a kind of crystal covering type BGA Package method, earlier on wafer 102 surface junction, form conductive projection (solder bump), then again wafer is had the one side of soldering projection and engage with conductive projection on covering brilliant substrate 106, and formation conductive connecting pin 104.And wafer and cover slit between brilliant substrate then pours into packing material (underfill) 103, and makes it firm.And cover the another side of brilliant substrate 106, and then having solder sphere pin (solderball) 108, can engage with other printed circuit board (PCB).Its major defect is:
Being applied in the brilliant substrate of covering of such use, generally is the welded gasket (bump pad) on insulation or the inner substrate that is furnished with circuit, makes projection (Bump) by the paste solder printing technology, as conductive connecting pin.And this step is commonly referred to as preceding welding (Pre-soldering).The shortcoming of this kind tin cream projection printing is that processing procedure is quite numerous and diverse, must carry out tin cream projection printing process by the special-purpose board of printed circuit board (PCB), and form the projection of leypewter (Sn-Pb) or its similar alloy mostly.And the quality that engages between projection often is subjected to the property effect of tin or its alloy, engages reliability and is subjected to the projection property effect very big.
Summary of the invention
Main purpose of the present invention is to provide a kind of manufacture method of conductive projection, and the metal coupling on the brilliant substrate is covered in the manufacturing of utilization plating (plating) processing procedure, reaches the purpose of simplifying the lug manufacturing process on the base plate for packaging.
A further object of the present invention is to provide a kind of manufacturing to have the manufacture method of covering brilliant substrate of conductive projection, this conductive projection can form good tin one bronze medal of the reliability alloy-layer (IMC) that is situated between altogether when encapsulation engages, reach the purpose of simplifying the lug manufacturing process that covers brilliant substrate.
The object of the present invention is achieved like this: a kind of manufacture method by plating mode formation conductive projection, and comprise the following step: a substrate is provided, and its surface has the multi-conducting point; Cover conductive film in substrate surface; On conductive film, form photoresist layer; The patterning photoresist layer forms most openings on this substrate surface, and exposes the multi-conducting point under it; Carry out metal plating, filling up this majority opening, and form most metal couplings (bump); Remove this elder generation's resistance layer and this conductive film; Form anti-welding protective layer in this substrate surface, and expose this majority metal coupling.
By said method, with comparatively simple and easy, and the simple plating mode of step, deposition forms the metal coupling of conduction in the opening of definition, to replace general projection printing technology.
The present invention more provides a kind of conductive projection to cover the manufacture method of brilliant substrate, comprises the following step: provide one to cover brilliant substrate, its surface has the multi-conducting point; Cover conductive film in covering brilliant substrate surface; Form photoresist layer on the conductive film surface; This photoresist layer of patterning forming most openings in covering on the brilliant substrate surface, and exposes the multi-conducting point under it; Carry out copper and electroplate, form most copper bumps to fill up this majority opening; Remove photoresist layer and conductive film; Form anti-welding protective layer in this substrate surface, and expose this majority copper bump; The most copper bumps that expose are carried out surface anti-oxidation to be handled.
By said method, have the brilliant substrate of covering of conductive projection with the plating mode manufacturing, and during the welding of conductive projection and wafer projection, the welding that forms better tin one bronze medal of adhesion connects face, improves the reliability of encapsulation.
Describe in detail below in conjunction with the preferred embodiment conjunction with figs..
Description of drawings
Fig. 1 is the generalized section of traditional crystal covering type ball grid array package (FCBGA).
Fig. 2-Fig. 8 is a manufacturing process schematic side view of covering the conductive projection of brilliant substrate of the present invention.
Fig. 9 covers the generalized section that brilliant substrate engages with wafer for conductive projection of the present invention.
Embodiment
Consult Fig. 2-shown in Figure 8, the manufacturing process that covers the conductive projection of brilliant substrate of the present invention comprises the steps.
Consult shown in Figure 2ly, cover in the brilliant substrate 200, the binding circuit can be set, and conductiving point be set as external junction point, internal connection line road, and preferable conductiving point is a copper packing (copperpad) 202 on substrate 200 surfaces one.Then form a conductive film 204 on the surface of covering brilliant substrate 200, the preferably can be by electroplating (plat ing) mode, uniformly at the electroplating surface layer of copper metal that covers brilliant substrate 200 as conductive film.For example, under the situation of no additional electrodes (electrode), in containing the electrolytic solution of copper ion, form the copper film as conductive layer in covering brilliant substrate 200 surface depositions with electrodeless plating (electroless plating).Because electrodeless plating has good continuity and ladder coverage effect, therefore, formation uniform copper film on brilliant substrate 200 and conduction copper packing 202 surfaces can covered.But conductive film of the present invention is not limited only to above-mentioned metallic copper film.
Then consult shown in Figure 3ly, form photoresist layers 208 covering brilliant substrate 200 surfaces, and it is carried out a micro-photographing process,, and above copper packing 202, form opening 202a with patterning photoresist layer 208.
Then consult shown in Figure 4ly, the copper film by above-mentioned formation carries out metal plating (metal column plating), to fill up opening 202a as crystal seed layer.The preferably electroplates formation copper bump (copper bump) 210 with copper on copper packing 202.And preferable bump height approximates the height of photoresist layer, or as shown in Figure 4, a little more than photoresist layer 208.
Because electro-coppering has the good hole ability of filling out, can upwards fill up by opening 202a bottom and form the good copper bump of quality.And plating has the advantage that cost is low, equipment is simple and deposition velocity is fast, can replace the general brilliant substrate printed convex block processing procedure that covers.And the electro-coppering program generally is widely used in other processing procedure of printed circuit board (PCB), therefore need not additionally buy more equipment.
Consult shown in Figure 5ly, after electroplating deposition metal coupling 210 is finished, then remove photoresist layer 208.
Then consult shown in Figure 6ly, generally after removing photoresist layer, can proceed acid solution and clean, to remove photoresistance impurity.This moment is simultaneously by the acid solution manufacturing process for cleaning, utilize acid solution that the microetch effect (microetching) of copper metal is removed and cover the conductive copper films 204 that expose on brilliant substrate 200 surfaces, and the copper bump 210 that will expose simultaneously and the angle slynessization of copper packing 202, and the copper bump 210 of formation arc helps follow-up joint.
Then consult shown in Figure 7ly, this is covered brilliant substrate 200 carry out an anti-welding protection processing procedure.In preferred embodiment, anti-welding protection processing procedure can adopt scolding tin mask (solder mask) processing procedure of general printed circuit board (PCB), and this processing procedure is commonly referred to anti-welding record lacquer.Mainly by covering a macromolecular material thin layer covering on the brilliant substrate, be covered in the other parts on metal coupling 210 surfaces as the roasting type epoxy resin (epoxy resin) of heat or light sensation formula acrylate (Acrylates).This anti-welding protective layer 212 can be avoided the short circuit that produces because of the scolding tin overflow in the successive process, and avoids covering brilliant substrate surface and destroyed by external environment.
Then consult shown in Figure 8ly,, can further carry out the anti-oxidation processing on metal coupling 210 surfaces for fear of the conductive projection 210 surperficial oxidated destructions of exposing.In preferred embodiment, can directly utilize the hot-air scolding tin coating technique (hot air solder leveling.HASL) in the printed circuit board (PCB) processing procedure, this processing procedure generally is used for the copper wire surface anti-oxidation of printed circuit board (PCB) to be handled, be to cover brilliant substrate to be dipped in the scolding tin that dissolves, after finishing coating, then remove unnecessary scolding tin, and form the anti-oxidation scolding tin coating 214 of suitable thickness in metal coupling 210 surfaces with the hot-air that blows at a high speed.Also can utilize general OSP processing procedure, promptly utilize chemistry to immerse, form the oxidation-resistant film of suitable thickness on metal coupling 210 surfaces.
By said method, can form metal coupling covering on the brilliant substrate by plating mode, as forming copper bump in the electro-coppering mode.
Consult shown in Figure 9ly, illustrate that the formed copper bump of method of the present invention covers the generalized section that brilliant substrate engages with a wafer.Wafer 300 is provided with engagement protrusion 306, and with its with general connection process with after metal coupling 206 (being copper packing 202, copper conductive film 204 and the combination of electro-coppering projection 206) on covering brilliant substrate 200 engages, at wafer 300 and cover between the brilliant substrate 200 and insert packing material 310, engage effect to fix it.Reason owing to copper character, copper bump 206 can't as the Solder Bumps that forms of printing process general, form frit reaction with the projection 306 on the wafer, yet coat the area increase owing to electroplate the contact of the copper bump that forms, make to engage tin one bronze medal that the back the forms alloy that is situated between altogether, it engages effect and more is better than traditional Solder Bumps.
In sum, one of major advantage of the inventive method is: form metal coupling by plating mode covering on the brilliant substrate, its processing procedure is simple, and control is better than general projection printing process easily.
Two of the advantage of the inventive method is: utilize plating mode to form copper bump covering on the brilliant substrate, it has bigger bonding area, therefore the Solder Bumps on copper bump and the wafer can form the stable tin one bronze medal alloy that is situated between altogether, and more traditional tin one nickel of the interface alloy that is situated between altogether is better.
Three of the advantage of wood inventive method is: whole fabrication steps need not be introduced extra process work bench, only need utilize general printed circuit board (PCB) manufacturing process and general electroplating device and micro-photographing process commonly used to finish, its manufacturing process is more simple, has more competitiveness for the production of covering brilliant substrate.
Though the present invention discloses as above with preferred embodiment, so it is not in order to qualification the present invention, any those who are familiar with this art, and without departing from the spirit and scope of the present invention, a little change and the retouching done all belongs within protection scope of the present invention.
Claims (10)
1, a kind of manufacture method of covering brilliant substrate with conductive projection, it is characterized in that: it comprises the following step:
(1) provide one to cover brilliant substrate, its surface has the multi-conducting point;
(2) cover a conductive film and cover the surface of brilliant substrate in this;
(3) form a photoresist layer in the surface of this conductive film;
(4) this photoresist layer of patterning covers the most openings of formation on the brilliant substrate surface in this, exposes the multi-conducting point under it;
(5) electroplate,, form the multi-conducting projection to fill up this majority opening;
(6) remove this photoresist layer and this conductive film;
(7) form an anti-welding protective layer in this substrate surface, and expose this multi-conducting projection.
2, the manufacture method of covering brilliant substrate with conductive projection according to claim 1 is characterized in that: this plating is electroplated for copper, to form the copper bump of conduction.
3, the manufacture method of covering brilliant substrate with conductive projection according to claim 1 is characterized in that: after forming this anti-welding protective layer, also comprise the multi-conducting projection that this is exposed and carry out the surface anti-oxidation processing.
4, the manufacture method of covering brilliant substrate with conductive projection according to claim 3 is characterized in that: it is to carry out the coating of hot-air scolding tin in the surface of this conductive projection that this surface anti-oxidation is handled, to form anti-oxidation coating.
5, the manufacture method of covering brilliant substrate with conductive projection according to claim 1, it is characterized in that: covering this conductive film is with electrodeless plating, forms the copper film and is covered in the surface that this covers brilliant substrate.
6, a kind of manufacture method of conductive projection, it is characterized in that: it comprises the following step:
(1) provide a substrate, its surface has the multi-conducting point;
(2) cover a conductive film in this substrate surface;
(3) form a photoresist layer in this substrate surface;
(4) this photoresist layer of patterning forms most openings on this substrate surface, expose the multi-conducting point under it;
(5) carry out metal plating,, form most metal couplings to fill up this majority opening;
(6) remove this photoresist layer and this conductive film;
(7) form an anti-welding protective layer in this substrate surface, and expose this majority metal coupling;
7, the manufacture method of conductive projection according to claim 6 is characterized in that: also comprise these most metal couplings that expose are carried out the step that surface anti-oxidation is handled.
8, the manufacture method of conductive projection according to claim 7 is characterized in that: it is to carry out the coating of hot-air scolding tin in this conductive projection surface that this surface anti-oxidation is handled, to form anti-oxidation coating.
9, the manufacture method of conductive projection according to claim 6 is characterized in that: this metal plating is that copper is electroplated, and this conductive projection is a copper bump.
10, the manufacture method of conductive projection according to claim 6 is characterized in that: covering this conductive film is to form metallic film with electrodeless plating to be covered in this substrate surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021462941A CN1492491A (en) | 2002-10-21 | 2002-10-21 | Method for producing polycrystalline base plate with conductive salient block and its conductive salient block |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021462941A CN1492491A (en) | 2002-10-21 | 2002-10-21 | Method for producing polycrystalline base plate with conductive salient block and its conductive salient block |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1492491A true CN1492491A (en) | 2004-04-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021462941A Pending CN1492491A (en) | 2002-10-21 | 2002-10-21 | Method for producing polycrystalline base plate with conductive salient block and its conductive salient block |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853841A (en) * | 2008-11-28 | 2010-10-06 | 三洋电机株式会社 | Device mounting board and method of manufacturing the board, semiconductor module and method of manufacturing the module |
| CN102340935A (en) * | 2010-07-19 | 2012-02-01 | 北大方正集团有限公司 | Circuit board and method and system for manufacturing circuit board bumps |
| CN102548243A (en) * | 2010-12-08 | 2012-07-04 | 北大方正集团有限公司 | Method and system for manufacturing bumps on circuit boards and circuit board utilizing same |
| CN102648670A (en) * | 2009-11-30 | 2012-08-22 | Lg伊诺特有限公司 | Printed circuit board and method of manufacturing the same |
| CN104538380A (en) * | 2014-12-10 | 2015-04-22 | 华进半导体封装先导技术研发中心有限公司 | Small-spacing PoP monomer |
-
2002
- 2002-10-21 CN CNA021462941A patent/CN1492491A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853841A (en) * | 2008-11-28 | 2010-10-06 | 三洋电机株式会社 | Device mounting board and method of manufacturing the board, semiconductor module and method of manufacturing the module |
| CN102648670A (en) * | 2009-11-30 | 2012-08-22 | Lg伊诺特有限公司 | Printed circuit board and method of manufacturing the same |
| CN102340935A (en) * | 2010-07-19 | 2012-02-01 | 北大方正集团有限公司 | Circuit board and method and system for manufacturing circuit board bumps |
| CN102548243A (en) * | 2010-12-08 | 2012-07-04 | 北大方正集团有限公司 | Method and system for manufacturing bumps on circuit boards and circuit board utilizing same |
| CN102548243B (en) * | 2010-12-08 | 2015-12-16 | 北大方正集团有限公司 | Make the method for circuit board salient point, system and circuit board |
| CN104538380A (en) * | 2014-12-10 | 2015-04-22 | 华进半导体封装先导技术研发中心有限公司 | Small-spacing PoP monomer |
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