CN1489216A - Electro-erasable programmable logic element - Google Patents
Electro-erasable programmable logic element Download PDFInfo
- Publication number
- CN1489216A CN1489216A CNA021468079A CN02146807A CN1489216A CN 1489216 A CN1489216 A CN 1489216A CN A021468079 A CNA021468079 A CN A021468079A CN 02146807 A CN02146807 A CN 02146807A CN 1489216 A CN1489216 A CN 1489216A
- Authority
- CN
- China
- Prior art keywords
- doped region
- pmos transistor
- electro
- erasable programmable
- programmable logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007667 floating Methods 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000001808 coupling effect Effects 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims 1
- 239000002784 hot electron Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000005040 ion trap Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Landscapes
- Non-Volatile Memory (AREA)
Abstract
The logic element comprises N type trap formed on P type semiconductor substrate, a first PMOS transistor and a second PMOS transistor. The first PMOS transistor includes a floating grid, first P+ doping area as drain electrode, and P- doping area surrounding a N+ doping area for erasing the first PMOS transistor. The second PMOS transistor formed on N type semiconductor substrate passing through the first P+ doping area is connected to the first PMOS transistor. The said first P+ doping area is also as source electrode of the second PMOS transistor. The second PMOS transistor includes a selection grid and a second P+ doping area as drain electrode of the second PMOS transistor. Using channel hot electron carries out writing operation, and using cavity passing through valence band and conduction band carries out erasing operation.
Description
Technical field
The present invention relates to a kind of semiconductor storage and method of operation thereof, relate in particular to a kind of single level polysilicon (single-poly) electro-erasable programmable logic element, plurality of advantages such as it has low power consumption, high density, high write/erase efficient, can repeat to write.Single level polysilicon EEPLD of the present invention is especially compatible in standard CMOS process and logic process, and is applicable to one chip (system-on-a-chip, SOC) field integrated.
Background technology
Electro-erasable programmable read-only memory (Electrically Erasable Programmable Read OnlyMemory, EEPROM) or quickflashing EEPROM (flash EEPROM), it has to cut off the electricity supply still can possess the advantage of memory content, and has a function that repeatable read is gone into data, add transmission fast, so application is very extensive.In many information, communication and consumption electronic products, all nonvolatile memory is treated as necessary element.And along with small size portable type electronic product personal digital assistant (personal digital assistant for example, PDA) or the demand order of mobile phone benefit increase, (system-on-a-chip, demand SOC) also promotes thereupon to include the embedded chip (embedded chip) of EEPROM and logical circuit or system combination chip simultaneously.For this reason, EEPROM certainly will write efficient, low cost and highdensity direction towards CMOS process compatible, low power consumption, height in the future to be developed, and just can meet the demand of product in the future.
Fig. 1 is the generalized section of existing EEPROM unit 10.As shown in Figure 1, existing EEPROM unit 10 includes a NMOS structure 28 and a PMOS structure 30, and both separate by an insulation field oxide 24.NMOS structure 28 is formed on the P type substrate 12, includes one first floating grid (floating gate), 32, one N
+A source doping region 14 and a N
+Drain doping region 16.PMOS structure 30 is formed on the N type ion trap 18, includes one second floating grid 34, a P
+A source doping region 20 and a P
+Drain doping region 22.In addition, at next-door neighbour P
+Source doping region 20 1 sides are injected with a heavy doping (heavily doped) N type raceway groove Resistance (channel stop region) 38, and this N type raceway groove Resistance 38 is positioned at the below of second floating grid 34.First floating grid 32 and second floating grid 34 also are connected by a floating grid lead 36, make first floating grid 32 and second floating grid 34 keep same potential.When first floating grid 32 produces corresponding current potential corresponding to a control-grid voltage, second floating grid 34 will have the current potential identical with first floating grid 32 owing to the connection of floating grid lead 36, and use attraction via P
+The accelerated electron that lean district produced of source doping region 20 and N type raceway groove Resistance 38 and with electron confinement in second floating grid 34.
Existing EEPROM unit 10 has following shortcoming.At first, existing EEPROM unit 10 is made of a PMOS transistor 30 and a nmos pass transistor 28, and shared chip unit are is bigger; Secondly, existing EEPROM unit 10 needs extra N type raceway groove Resistance 38; Moreover existing EEPROM unit 10 must be electrically connected first floating grid 32 and second floating grid 34 with floating grid lead 36; In addition, needing field oxide 24 between NMOS structure 28 and PMOS structure 30 isolates.As from the foregoing, existing EEPROM unit 10 chip occupying area are excessive, add complex structure, increase technology cost and degree of difficulty.
Summary of the invention
In view of the above, main purpose of the present invention is to provide the single level polysilicon EEPLD structure of a kind of high density and low power consumption.
Another object of the present invention is to provide a kind of power saving high-density single layer polysilicon EEPLD structure and method of operation thereof, its manufacture method can be compatible with the traditional cmos logic process simultaneously.
In a preferred embodiment of the invention, disclose a kind of electro-erasable programmable logic element, included a N type trap, be formed on the P type semiconductor substrate; One the one PMOS transistor is formed on this N type trap, and wherein a PMOS transistor includes a floating grid, one the one P
+Doped region is as a PMOS transistor drain, and a P
-Doped region surrounds a N
+Doped region is in order to wipe a PMOS transistor; One the 2nd PMOS transistor is formed on this N type semiconductor substrate and via a shared P
+Doped region is serially connected with a PMOS transistor, wherein a P
+Doped region is also as the transistorized source electrode of the 2nd PMOS, and the 2nd PMOS transistor includes a selection grid and one the 2nd P
+Doped region is as the 2nd PMOS transistor drain.Electro-erasable programmable logic element of the present invention utilizes channel hot electron to write, and carries out erasing move and with valence band conduction band is worn the tunnel hole.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the generalized section of existing EEPROM unit;
Fig. 2 (a) looks schematic diagram on the part of electro-erasable programmable logic element of the present invention;
Fig. 2 (b) is the generalized section of Fig. 2 (a) electro-erasable programmable logic element along tangent line AA ';
Fig. 3 carries out the schematic diagram of write operation for electro-erasable programmable logic element of the present invention;
Fig. 4 is that the PMOS transistor drains to N type trap bias voltage (V in difference
d=V
1-V
5) curve chart of gate voltage to gate current of floating under the condition;
Fig. 5 carries out the schematic diagram of erase operation for electro-erasable programmable logic element of the present invention; And
Fig. 6 carries out the schematic diagram of read operation for electro-erasable programmable logic element of the present invention.
Description of reference numerals in the accompanying drawing is as follows:
10 EEPROM unit, 12 P type substrates
14 N
+Source doping region 16 N
+Drain doping region
18 N type ion traps, 20 P
+Source doping region
22 P
+Drain doping region 24 field oxides
28 nmos pass transistors, 30 PMOS transistors
32 first floating grids, 34 second floating grids
36 floating grid leads, 38 N type raceway groove Resistance
100 electro-erasable programmable logic elements, 101 PMOS transistors
102 PMOS transistors, 110 N type traps
122 floating grids 124 are selected grid
132 P
+Doped region 134 N
+Doped region
136 P
+ Doped region 162 dielectric layers
122a floating grid oxide layer 124a gate oxide
140 P
-Doped region 142 P
+Doped region
144 N
+Doped region
Embodiment
See also Fig. 2 (a) and Fig. 2 (b), wherein Fig. 2 (a) looks schematic diagram on the part of electro-erasable programmable logic element of the present invention (EEPLD) 100, and Fig. 2 (b) is Fig. 2 (a) electro-erasable programmable logic element 100 generalized sections along tangent line AA '.Shown in Fig. 2 (a), electro-erasable programmable logic element 100 includes a PMOS transistor 101 and a PMOS transistor 102 is serially connected with PMOS transistor 101 via a shared doped region.PMOS transistor 101 and PMOS transistor 102 are formed on the N type trap 110.PMOS transistor 101 is floating grid transistors, and it includes a floating grid 122, a P
+A doped region 132 and a N
+Doped region 134.N
+ Doped region 134 is in order to wipe the information that is stored in floating grid 122, and it is formed at a P
-In the doped region 140.P
- Doped region 140 is overlapped with floating grid 122, and its formation can be adopted the angle of inclination ion implantation or drive in mode such as method with thermal diffusion.Floating grid of the present invention 122 is formed by single level polysilicon, and its top does not need yet, and is formed with control electrode.In addition, P
-One P is still arranged in the doped region 140
+Assorted district 142, its be formed at P equally
-N in the doped region 140
+ Doped region 134 separates with a field oxide 150 or shallow trench isolation layer.As previously mentioned, PMOS transistor 101 and PMOS transistor 102 shared P
+ Doped region 132, and use the transistor that forms two serial connections.PMOS transistor 102 includes one and selects grid 124, the P shared with PMOS transistor 101
+A doped region 132 and a P
+Doped region 136.In addition, at N
+ Doped region 134 and P
+Can select to form a metal silicide layer (not shown) on the doped region 142.
In Fig. 2 (b), PMOS transistor 101 includes a floating grid oxide layer 122a in addition and is located at floating grid 122 belows.PMOS transistor 102 includes gate oxide 124a in addition.P
+ Doped region 136 is electrically connected with a bit line via the contact plunger that is formed in the dielectric layer 162, and using provides electro-erasable programmable logic element 100 1 bit line signals.Because electro-erasable programmable logic element 100 of the present invention operates under the low-voltage, floating grid oxide layer 122a and gate oxide 124a can be identical with the thickness of grid oxide layer in the logical circuit, or optionally increase thickness.Whichsoever, electro-erasable programmable logic element 100 structures of the present invention are all compatible in the standard CMOS semiconductor technology.
See also Fig. 3, the schematic diagram that Fig. 3 carries out write operation for electro-erasable programmable logic element 100 of the present invention.As shown in Figure 3, when carrying out write operation, the P of PMOS transistor 102
+ Drain doping region 136 applies a bit-line voltage V
1=0V selects grid 124 to impose a word line voltage V
2, its voltage should be lower than bit-line voltage V
1At least one start voltage value size, for example V
2=-2V makes to be positioned at the P raceway groove unlatching of selecting grid 124 belows, and then makes P
+ Doped region 132 and P
+Drain doping region 136 is a same potential, that is 0V.N type trap 110 applies a trap voltage V
5=5V.The floating grid 122 of floating grid transistor 101 is a floating state, N
+ Doped region 134 and P
+ Source doping region 142 applies an erasing voltage V respectively
3=5V and source electrode line voltage V
4=5V makes P
- Doped region 140 and N type trap 110 same potential.Under above-mentioned operating condition, because floating grid 122 can obtain a low-voltage by capacitance coupling effect, 3～4V for example, and the P type raceway groove of floating grid 122 belows is opened, hot electron is produced by the collision of channel hole, and quicken to cross floating grid oxide layer 122a through the electric field in lean district, be trapped in the floating grid 122.
See also Fig. 4, Fig. 4 is that PMOS transistor 101 drains to N type trap 110 bias voltage (V in difference
d=V
1-V
5) curve chart of gate voltage to gate current of floating under the condition.As shown in Figure 4, at bias voltage V
dFor under-5V the condition, floating grid 122 by capacitance coupling effect obtain approximately-1～-the 2V low-voltage, at this moment, the raceway groove of PMOS transistor 101 is just opened, and grid current is near maximum.In other words, under operator scheme of the present invention, grid current is to the ratio (I of drain current
g/ I
d) bigger, therefore when carrying out programming operation, can obtain preferred usefulness.
See also Fig. 5, Fig. 5 carries out the schematic diagram of erase operation for electro-erasable programmable logic element 100 of the present invention.As shown in Figure 5, when carrying out erase operation, the P of PMOS transistor 102
+ Drain doping region 136 applies a bit-line voltage V
1=0V selects grid 124 to impose a word line voltage V
2=0V makes to be positioned at and selects the P raceway groove of grid 124 belows not open.N type trap 110 applies a trap voltage V
5=0V.The floating grid 122 of floating grid transistor 101 is a floating state, N
+ Doped region 134 and P
+ Source doping region 142 applies an erasing voltage V respectively
3=5V and source electrode line voltage V
4=-3V makes N
+ Doped region 134 and P
+ Source doping region 142 is for bias voltage and produce a lean district.Under above-mentioned operating condition, because the electron hole pair that is produced in the lean district, wherein tunnel (Band-to-Band tunneling) mechanism can be worn to conduction band via valence band in the hole, overcomes the potential barrier of floating grid oxide layer 122a, enters floating grid 122 and the electronics neutralization that is trapped in the floating grid 122.
See also Fig. 6, Fig. 6 carries out the schematic diagram of read operation for electro-erasable programmable logic element 100 of the present invention.As shown in Figure 6, when carrying out read operation, the P of PMOS transistor 102
+ Drain doping region 136 applies a bit-line voltage V
1=V
DD-V
x, V wherein
xBe one greater than the bit line of 0V cross-pressure, select grid 124 to impose a word line voltage V source electrode line
2=0V makes to be positioned at the P raceway groove unlatching of selecting grid 124 belows.N type trap 110 applies a trap voltage V
5=V
DDThe floating grid 122 of floating grid transistor 101 is a floating state, N
+ Doped region 134 and P
+ Source doping region 142 applies a voltage V respectively
3=V
DDAnd source electrode line voltage V
4=V
DD
According to the above, compared with prior art, electro-erasable programmable logic element of the present invention can be operated under low-voltage, and because design of the present invention makes PMOS transistor 101 when raceway groove is just opened, gate current I
gNear maximum, under operator scheme of the present invention, gate current is to the ratio (I of drain current
g/ I
d) bigger, therefore have the advantage that power saving economizes energy, and when programming, can obtain preferred usefulness, and save the time of programming.In addition, utilize the design wipe doped region 134, make memory can effectively utilize band and band is worn the tunnel hole carry out erase operation.And, because the present invention uses two PMOS transistor series connections, significantly reduce the usable floor area of chip, make the present invention can apply to the high-density storage field.Moreover the present invention is simple in structure, can be compatible with the traditional cmos logic process, more reduced cost of manufacture, and therefore be applicable to one chip (system-on-a-chip, SOC) field integrated.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (9)
1. electro-erasable programmable logic element comprises:
One P type semiconductor substrate;
One N type trap is formed on this P type semiconductor substrate;
One the one PMOS transistor is formed on this N type trap, and wherein a PMOS transistor includes a floating grid, one the one P
+Doped region is as a PMOS transistor drain, and a P
-Doped region surrounds a N
+Doped region is in order to wipe a PMOS transistor; And
One the 2nd PMOS transistor is formed on this N type trap and via a shared P
+Doped region is serially connected with a PMOS transistor, wherein a P
+Doped region is also as the transistorized source electrode of the 2nd PMOS, and the 2nd PMOS transistor comprises that one selects grid and one the 2nd P
+Doped region is as the 2nd PMOS transistor drain.
2. electro-erasable programmable logic element as claimed in claim 1, wherein a PMOS transistor includes one the 3rd P in addition
+Doped region, itself and this N
+Doped region all is formed at this P
-In the doped region, and the 3rd P
+Doped region and this N
+Doped region is not overlapping.
3. electro-erasable programmable logic element as claimed in claim 2, wherein the 3rd P
+Doped region and this N
+Doped region is isolated mutually with an insulating barrier.
4. electro-erasable programmable logic element as claimed in claim 1, wherein a P
+Doped region, this N
+Doped region and the 2nd P
+Can be covered with a metal silicide layer on the doped region.
5. electro-erasable programmable logic element as claimed in claim 1 is wherein at a predetermined drain bias V
dDown, this floating grid can obtain a low-voltage by a capacitance coupling effect, causes the transistorized P type of PMOS raceway groove to be opened, and produces one near peaked grid current, to carry out write operation.
6. electro-erasable programmable logic element as claimed in claim 5, wherein this predetermined bias is about 5V.
7. electro-erasable programmable logic element as claimed in claim 1, wherein this floating grid top there is no a control grid is set.
8. electro-erasable programmable logic element as claimed in claim 1, wherein this floating grid is constituted by a single level polysilicon.
9. electro-erasable programmable logic element as claimed in claim 1, wherein the 2nd P
+Doped region is electrically connected a bit line, so that this electro-erasable programmable logic element one bit line signal to be provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02146807.9A CN1222041C (en) | 2002-10-11 | 2002-10-11 | Electro-erasable programmable logic element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02146807.9A CN1222041C (en) | 2002-10-11 | 2002-10-11 | Electro-erasable programmable logic element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1489216A true CN1489216A (en) | 2004-04-14 |
| CN1222041C CN1222041C (en) | 2005-10-05 |
Family
ID=34148666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02146807.9A Expired - Fee Related CN1222041C (en) | 2002-10-11 | 2002-10-11 | Electro-erasable programmable logic element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1222041C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100490152C (en) * | 2004-12-13 | 2009-05-20 | 力旺电子股份有限公司 | Non-volatile memory cell and related operation method |
| CN101807580B (en) * | 2006-04-21 | 2012-02-08 | 英特赛尔美国股份有限公司 | Multiple time programmable non-volatile memory device with thick gate oxide |
-
2002
- 2002-10-11 CN CN02146807.9A patent/CN1222041C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100490152C (en) * | 2004-12-13 | 2009-05-20 | 力旺电子股份有限公司 | Non-volatile memory cell and related operation method |
| CN101807580B (en) * | 2006-04-21 | 2012-02-08 | 英特赛尔美国股份有限公司 | Multiple time programmable non-volatile memory device with thick gate oxide |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1222041C (en) | 2005-10-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5300802A (en) | Semiconductor integrated circuit device having single-element type non-volatile memory elements | |
| KR100219331B1 (en) | Non-volatile semiconductor memory device and method for eraser and production thereof | |
| US6580135B2 (en) | Silicon nitride read only memory structure and method of programming and erasure | |
| CN1967878A (en) | Operation mehtod of single-poly non-volatile memory device | |
| US20040256657A1 (en) | [flash memory cell structure and method of manufacturing and operating the memory cell] | |
| CN1790717A (en) | Non-volatile memory cell | |
| US6801456B1 (en) | Method for programming, erasing and reading a flash memory cell | |
| KR100364040B1 (en) | A semiconductor memory device and a method of making thereof | |
| US20020113272A1 (en) | Embedded type flash memory structure and method for operating the same | |
| CN1992345A (en) | Flash memory cell including dual tunnel oxide, and manufacturing method thereof | |
| US6914826B2 (en) | Flash memory structure and operating method thereof | |
| CN100568508C (en) | Symmetrical and self aligned non-volatile memory architecture | |
| US7894257B1 (en) | Low voltage low cost non-volatile memory | |
| US8592889B1 (en) | Memory structure | |
| JP3474614B2 (en) | Nonvolatile semiconductor memory device and method of operating the same | |
| CN1222041C (en) | Electro-erasable programmable logic element | |
| US5998830A (en) | Flash memory cell | |
| JP4071120B2 (en) | Flash memory, flash memory cell structure and array structure | |
| US7102188B1 (en) | High reliability electrically erasable and programmable read-only memory (EEPROM) | |
| CN1157793C (en) | Embedded flash memory and its operating method | |
| US6642571B2 (en) | Nonvolatile semiconductor memory | |
| CN100521214C (en) | Nonvolatile memory | |
| US6887756B2 (en) | Method of forming flash memory with protruded floating gate | |
| US8390052B2 (en) | Nonvolatile semiconductor memory device | |
| CN1229869C (en) | Single layer multisilicon crystal electro erasible programmable read-only storage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |