CN1485896A - Process for preparing metallic interconnection wire - Google Patents
Process for preparing metallic interconnection wire Download PDFInfo
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- CN1485896A CN1485896A CNA021440786A CN02144078A CN1485896A CN 1485896 A CN1485896 A CN 1485896A CN A021440786 A CNA021440786 A CN A021440786A CN 02144078 A CN02144078 A CN 02144078A CN 1485896 A CN1485896 A CN 1485896A
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Abstract
The invention discloses a metal inner-wire making method, applied to a semiconductor substrate whose surface contains a low-dielectric constant dielectric layer. The method includes the steps: making a depositing process to develop a nonnitrogenous antireflection layer, using the mixed gas of the silicic and oxygenous gas and the hydrogen as the reaction gas; using an optical-resistant layer pattern as mask to etch the antireflection layer; and using the optical resistant layer and the antireflection layer pattern as mask to etch the dielectric layer, synchronously or then, adding a hydrogen electric-plasm process to obtain an interlayer window or groove.
Description
Technical field
The present invention relates to a kind of manufacturing technology of semiconductor integration integrated circuits, and particularly relate to a kind of manufacture method of metal interconnecting.
Background technology
The manufacture process of semiconductor integrated circuit is extremely complicated process, and purpose is various electronic components and circuit that particular electrical circuit is required, dwindles being produced in the small size substrate.Wherein, each element must electrically connect by suitable internal connecting line (interconnect), can bring into play desired function.The metallization manufacture process (metallization) of general so-called integrated circuit, except making each layer conductor pattern, and by interlayer hole (contact/via) structure, with as between element contact zone and the lead, or the passage of getting in touch between the multi-layer conductor leads.In recent years, development for the downsizing of co-operating member size, organic polymer material with low-k (low-k), be used to gradually as surplus genus interlayer dielectric layer (inter-metal dielectric), postpone with parasitic capacitance and the RC that reduces element, thus the operating efficiency of raising integrated circuit.The material that is used as metal intermetallic dielectric layer in the prior art includes: electric slurry oxide silicon (PE-OX; Plasma enhanced oxide), electricity slurry tetraethoxy silex glass (PE-TEOS; Plasmaenhanced tetraethyl orthosilicate glass), the dielectric material of spin-on glasses, low-k is (as the Fo of Dow-Coring company production
x-15) etc.The development of deep-sub-micrometer manufacture process more highlights the importance of some particular semiconductor process technology, seeks manufacture process as little shadow and dry-etching.The development of high-accuracy type exposure instrument and high photosensitive material has made time micron image on the photoresist layer easily obtain, moreover the equipment of advanced dry-etching and technology are applied to also make in the manufacturing of ultra-large type integrated circuit (IC) wafer time micron image on the photoresist layer can accurately depict etched material under it.Yet the size that will more dwindle semiconductor wafer also must be researched and developed other special manufacture process or structures except the innovation of above-mentioned advanced manufacture process technology.
Along with the semiconductor fabrication technical development, the size of live width and contact hole is more and more little, and little shadow aspect must add dielectric reflection layer (dielectric anti-reflection coating for reaching requirement, DARC) and reduce photoresistance thickness, to reach its required resolution.General dielectric reflection layer is principal component with silicon, adjusts nitrogenous, potassium composition, can be silica (SiO
x), silicon oxynitride (SiON), carbon doped silicon oxide (SiOC) etc.The etching aspect is because no suitable mode promotes the etching selectivity between photoresist layer and anti-reflecting layer, and photoresistance thickness reduces, and the depth-to-width ratio on the manufacture process is more and more big, so cause serious and etched layer of problem such as striped (striated) generation of critical dimension (critical dimension) loss.In the etching program of general ic manufacturing process, because the etching selectivity of photoresist layer and etched interlayer is little, therefore the photoresist layer that is used for being used as mask also can sustain damage in etching process and reduce thickness, and causes not good photoresist layer and the etching selectivity between anti-reflecting layer and etching to stop.
As shown in Figure 1, generally have now on the dielectric layer 12 of substrate or semiconductor element 10, low-k, when forming the anti-reflecting layer 14 in little shadow and the etch process, normally with monosilane (SiH
4) with carbon dioxide as precursors; and optionally with helium as carrier gas; and deposition obtains the anti-reflecting layer 14 of high carbon content; yet when with photoresist layer 16 patterns during as the anti-reflecting layer 14 of this high carbon content of mask etching and etching dielectric layer 12; the problem that regular meeting has etching to stop; particularly when the comparatively sparse estranged formula interlayer hole etching of pattern density (iso via etch), and cause the difficulty of interlayer hole opening.The problems referred to above are needed badly effectively and are improved one's methods.
Summary of the invention
In view of this, technical problem to be solved by this invention is to provide a kind of manufacture method of metal interconnecting, said method is to add hydrogen in the precursors of anti-reflecting layer, hydrogen is combined with too much carbon, and the concentration of minimizing silicon one carbon bond knot, and in etching dielectric layer or afterwards, add the electricity slurry handling procedure of hydrogen, the problem that makes the interlayer hole etching program not have low pattern density interdependence takes place, that is to say, when the comparatively sparse estranged formula interlayer hole etching of pattern density, the infull problem of interlayer hole opening can not take place again.In addition, also can avoid capacitance delays effect as Kevin's formula interlayer hole (Kelvin iso via).
For realizing above-mentioned purpose, the present invention proposes a kind of manufacture method of metal interconnecting, be applicable to the semiconductor substrate, include a dielectric layer with low dielectric constant on its surface, the method comprises the following steps: to implement a deposition program on this dielectric layer with low dielectric constant surface, to form a no nitrogen anti-reflecting layer, wherein above-mentioned deposition program is to adopt silicon-containing gas and oxygen-containing gas, and the mist that adds hydrogen is as reacting gas; Be somebody's turn to do no nitrogen anti-reflecting layer with a photoresist layer pattern as the mask etching; And with this photoresist layer and this no nitrogen anti-reflecting layer pattern as this dielectric layer with low dielectric constant of mask etching, to obtain an interlayer hole or groove, wherein in above-mentioned processing procedure or add the electricity slurry handling procedure of a hydrogen afterwards.
For allow above-mentioned and other purposes of the present invention, feature, and advantage can become apparent, some preferred embodiments cited below particularly, and cooperate its respective drawings are described in detail below:
Description of drawings
Fig. 1 is a profile, in order to the explanation prior art.
Fig. 2 A-Fig. 2 E is in the method according to the etching advanced low-k materials of the embodiment of the invention, does the manufacturing process profile of interlayer hole earlier.
Fig. 3 A-Fig. 3 E is in the method according to the etching advanced low-k materials of the embodiment of the invention, does the manufacturing process profile of groove earlier.
Embodiment
Present embodiment is that the method according to this invention is applied on the copper metal interconnecting manufacture process of mosaic texture, general dual-damascene copper manufacture process roughly can reduce three kinds: the manufacture process of 1) being groove (Trench first) earlier, 2) do the manufacture process of interlayer hole (via first) earlier, and 3) aim at (self-aligned) manufacture process automatically.For simplicity, below be that example describes only with the manufacture process of doing interlayer hole earlier, also can be applicable to other manufacture processes but be familiar with this skill personage.
Please refer to Fig. 2 A, it shows the initial step of present embodiment.The part of label 100, may comprise several layers of metal interconnecting and a plurality of electrical interconnective semiconductor element of, as MOS electric crystal, resistance, logic element etc., for the purpose of simplicity of illustration, the semiconductor-based end and the integrated circuit component of metal intermetallic dielectric layer below 102 only represented with label 100.
Metal intermetallic dielectric layer 102 is represented the dielectric material of a low dielectric layer constant, carbon dope or mix silica (SiOC:H) the class dielectric material of hydrogen normally, for example the hydrogen doping oxide layer (HSQ, hydrogensilses-quioxane), methyl doping oxide layer (MSQ; Methyl silsesquioxane), hydrogen doping poly oxide layer (H-PSSQ; Hydrio polysilsesquioxane), methyl doping poly oxide layer (M-PSSQ; Methyl polysilsesquioxane), phenyl doping poly oxide layer (P-PSSQ; Phenylpolysilsesquioxane), mix fluorine Parylene ether (FLARE; Allied Signal or MicrowaveMaterials produce), aromatic hydrocarbons (SiLK; Dow Chemical produces), xerogel (Xerogel), ultramicropore glass (Nanoglass), and polyarylene ether-2 (PAE-2) etc.The dielectric constant of above-mentioned material is generally about 3, but scope can be between 1-4.This dielectric layer can chemical vapor deposition (CVD), or is deposited in the substrate in the mode of spin coating (spin coating), forms as shown in FIG. dielectric film through overcuring (curing) then.
Next, the present invention utilizes a deposition program, forms a no nitrogen anti-reflecting layer 104 on the metal intermetallic dielectric layer of above-mentioned low-k, and above-mentioned deposition program is to adopt silicon-containing gas and oxygen-containing gas, and the mist that adds hydrogen is as reacting gas.The gas flow of above-mentioned hydrogen between the 000sccm, is good with 500sccm between 10-10.Above-mentioned silicon-containing gas includes, but is not limited to, for example monosilane (SiH
4), disilane (Si
2H
6), trimethyl silane (trimethylsilane) or tetramethylsilane (tetramethylsilane), be good with monosilane.The gas flow of above-mentioned silicon-containing gas between the 000sccm, is good with 400sccm between 10-10.Above-mentioned oxygen-containing gas includes, but is not limited to, for example carbon dioxide (CO
2), carbon monoxide (CO), oxygen (O
2), water (H
2O), hydrogen peroxide (H
2O
2), be good with carbon dioxide.The gas flow of above-mentioned oxygen-containing gas between the 000sccm, is good with 1,000 between 10-10.Above-mentioned deposition program also can utilize helium or argon as carrier gas.According to the inventive method, this deposition program can be generally chemistry, vapour deposition process is implemented, wherein should the processing time between 1-1, between 000 second; Operating pressure is good with 5Torr between 0.1MTorr-100Torr; Operand power between the 000Watt, is good with 600Watt between 10-10; Frequency of operation is good with 13.56MHz between 10KHz-14GHz; Operating temperature between 000 ℃, is good with 350 ℃ between 10-1.Above-mentioned deposition program is by adding hydrogen, hydrogen is combined with too much carbon, and reduce the concentration that silicon-carbon bond is tied.
Please refer to Fig. 2 B, next, form a photoresist layer 106 with rotating coating and cover on no nitrogen anti-reflecting layer 104 surfaces, and define etched pattern with a little shadow image forming program.Afterwards, utilize above-mentioned photoresist layer 106 patterns to be used as mask again, etching does not have nitrogen anti-reflecting layer 104, to form required etched pattern.
Please refer to Fig. 2 C, utilize above-mentioned photoresist layer 106 and do not have nitrogen anti-reflecting layer 104 patterns and be used as mask, etching dielectric layer with low dielectric constant 102 is to form an interlayer hole A.In carrying out etched process or afterwards, can implement the electricity slurry handling procedure of a hydrogen, can prevent that etching from interrupting, thereby avoid capacitance resistance late effect (RC delay).
Remove after the photoresist layer 106,, form a groove, carry out comprehensive deposition, form a metal barrier layer 108 with a bottom and a side ancient piece of jade, round, flat and with a hole in its centre at intraconnections interlayer hole and groove with little shadow and engraving method next according to the inserted manufacture process of tradition.This barrier layer 108 can help the attached work of follow-up metal and prevent its diffusion, and for copper, suitable diffusion barrier layer material comprises: tantalum (Ta), and tantalum nitride (TaN), tungsten nitride (WN), or the titanium nitride of using always in the existing manufacture process (TiN) etc.Then, with chemical vapour deposition technique (CVD), physical vapour deposition (PVD), method (PVD), or electroplating deposition method (Electroplating) deposited copper metal level 110 on barrier layer 108, and make it fill up aforesaid intraconnections groove.The preferably can utilize ionized metal electricity slurry (IMP) crystal seed layer of the about 300-1500 dust of deposition one bed thickness in substrate earlier, and then finishes the deposition of copper conductive layer with galvanoplastic.Usually barrier layer can be finished in the different cavity of multi-cavity reative cell (cluster chamber) in regular turn with the deposition program of crystal seed layer and vacuum breaker not, so as to the reliability and the production capacity of raising manufacture process.
After finishing the deposition of barrier layer 108 and copper metal layer 110, carry out planarization, copper metal layer beyond intraconnections interlayer hole and the groove 110 and barrier layer 108 are removed, can obtain 2E and scheme shown structure with chemical mechanical milling method.The process of grinding comprises: the formality of the grinding of copper metal, the grinding of barrier layer and last one oxide cmp (oxide buffing), wherein each stage is to use different grinding milks.
Embodiment 2: the manufacture process of doing groove earlier
Please refer to Fig. 3 A, it shows the initial step of present embodiment.The part of label 200, may comprise multiple layer metal intraconnections and a plurality of electrical interconnective semiconductor element of, as MOS electric crystal, resistance, logic element etc., for the purpose of simplicity of illustration, the semiconductor-based end and the integrated circuit component of metal intermetallic dielectric layer below 202 only represented with label 200.
Metal intermetallic dielectric layer 202 is represented the dielectric material of a low dielectric layer constant, normally silica hydrocarbon (SiOC:H) class dielectric material, for example Yun doping oxide layer (HSQ, hydrogen silses-quioxane), methyl doping oxide layer (MSQ; Methyl silsesquioxane), hydrogen doping poly oxide layer (H-PSSQ; Hvdrio polysilsesquioxane), methyl doping poly oxide layer (M-PSSQ; Methylpolysilsesquioxane), phenyl doping poly oxide layer (P-PSSQ; Phenyl polysilsesquioxane), mix fluorine Parylene ether (FLARE; Allied Signal or Microwave Materials produce), aromatic hydrocarbons (SiLK; Dow Chemical produces), xerogel (Xerogel), ultramicropore glass (Nanoglass), and polyarylene ether-2 (PAE-2) etc.The dielectric constant of above-mentioned material is generally about 3, but scope can be between 1-4.This dielectric layer can chemical vapor deposition (CVD), or is deposited in the substrate in the mode of spin coating (spin coating), forms as shown in FIG. dielectric film through overcuring (curing) then.
Next, the present invention utilizes a deposition program, forms a no nitrogen anti-reflecting layer 204 on the metal intermetallic dielectric layer of above-mentioned low-k, and above-mentioned deposition program is to adopt silicon-containing gas and oxygen-containing gas, and the mist that adds hydrogen is as reacting gas.The gas flow of above-mentioned hydrogen between the 000sccm, is good with 500sccm between 10-10.Above-mentioned silicon-containing gas includes, but is not limited to, for example monosilane (SiH
4), second silicon a heatable brick bed (Si
2H
6), trimethyl silane (trimethylsilane) or tetramethylsilane (tetramethylsilane), be good with monosilane.The gas flow of above-mentioned silicon-containing gas between the 000sccm, is good with 400sccm between 10-10.Above-mentioned oxygen-containing gas includes, but is not limited to, for example carbon dioxide (CO
2), carbon monoxide (CO), oxygen (O
2), water (H
2O), hydrogen peroxide (H
2O
2), be good with carbon dioxide.The gas flow of above-mentioned oxygen-containing gas between the 000sccm, is good with 1,000 between 10-10.Above-mentioned deposition program also can utilize helium or argon as carrier gas.According to the inventive method, this deposition program generally chemical vapour deposition technique is implemented, wherein should the processing time between 1-1, between 000 second; Operating pressure is good with 5Torr between 0.1MTorr-100Torr; Operand power between the 000watt, is good with 600Watt between 10-10; Frequency of operation is good with 13.56MHz between 10KHZ-14GHz; Operating temperature between 000 ℃, is good with 350 ℃ between 10-1.Above-mentioned deposition program is by adding hydrogen, hydrogen is combined with too much carbon, and reduce the concentration that silicon-carbon bond is tied.
Please refer to Fig. 3 B, next, form a photoresist layer 206 with rotating coating and cover on no nitrogen anti-reflecting layer 204 surfaces, and define etched pattern with a little shadow image forming program.Afterwards, utilize above-mentioned photoresist layer 206 patterns to be used as mask again, etching does not have nitrogen anti-reflecting layer 204, to form required etched pattern.
Please refer to Fig. 3 C, utilize above-mentioned photoresist layer 206 and do not have nitrogen anti-reflecting layer 204 patterns and be used as mask, etching dielectric layer with low dielectric constant 202 is to form a groove B.In carrying out etched process or afterwards, can implement the electricity slurry handling procedure of a hydrogen, can prevent that etching from interrupting, thereby avoid capacitance resistance late effect (RC delay).
Remove after the photoresist layer 206,, form an interlayer hole, carry out comprehensive deposition, form a metal barrier layer 208 with bottom and sidewall at intraconnections interlayer hole and groove with little shadow and etching program next according to the inserted manufacture process of tradition.This barrier layer 208 can help the attached work of follow-up metal and prevent its diffusion, and for copper, suitable diffusion barrier layer material comprises: tantalum (Ta), and tantalum nitride (TaN), tungsten nitride (WN), or the titanium nitride of using always in the existing manufacture process (TiN) etc.Then, with chemical vapour deposition technique (CVD), physical vaporous deposition (PVD), or electroplating deposition method (Electroplating) deposited copper metal level 210 on barrier layer 208, and make it fill up aforesaid intraconnections groove.The preferably can utilize ionized metal electricity slurry (IMP) crystal seed layer of the about 300-1500 dust of deposition one bed thickness in substrate earlier, and then finishes the deposition of copper conductive layer with galvanoplastic.Usually barrier layer can be finished in the different cavity of multi-cavity reative cell (cluster chamber) in regular turn with the deposition program of crystal seed layer and vacuum breaker not, so as to the reliability and the production capacity of raising manufacture process.
After finishing the deposition of barrier layer 208 and copper metal layer 210, carry out planarization, copper metal layer beyond intraconnections interlayer hole and the groove 210 and barrier layer 208 are removed, can obtain the structure shown in Fig. 3 E with chemical mechanical milling method.The process of grinding comprises: the formality of the grinding of copper metal, the grinding of barrier layer and last one oxide cmp (oxide buffing), wherein each stage is to use different grinding milks.
The result
Among the above embodiment 1 and 2 no nitrogen anti-reflecting layer 104 and 204 fens other FTIR spectral results as can be known, silico-carbo/silicon-oxygen ratio is positioned near the person of 1250cm-1 all should be less than 18%.Therefore, the deposition program of interpolation hydrogen reduces the concentration of silico-carbo bond really.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when the scope with the claim of present patent application.
Claims (11)
1. the manufacture method of a metal interconnecting is applicable to the semiconductor substrate, includes a dielectric layer with low dielectric constant on its surface, and the method comprises the following steps:
(a) form a no nitrogen anti-reflecting layer on this dielectric layer with low dielectric constant surface;
(b) be somebody's turn to do no nitrogen anti-reflecting layer with a photoresist layer pattern as the mask etching; And
(c) with this photoresist layer and this no nitrogen anti-reflecting layer pattern as this dielectric layer with low dielectric constant of mask etching, to obtain an opening.
2. the manufacture method of metal interconnecting as claimed in claim 1 is characterized in that, forming no nitrogen anti-reflecting layer in the described step (a) is to adopt silicon-containing gas and oxygen-containing gas, and the mist that adds hydrogen is as formation that reacting gas deposits.
3. the manufacture method of metal interconnecting as claimed in claim 2 is characterized in that, described silicon-containing gas comprises monosilane SiH
4, disilane Si
2H
6, trimethyl silane or tetramethylsilane.
4. the manufacture method of metal interconnecting as claimed in claim 3 is characterized in that, described silicon-containing gas comprises monosilane.
5. the manufacture method of metal interconnecting as claimed in claim 3 is characterized in that, described oxygen-containing gas comprises carbon dioxide, carbon monoxide, oxygen, water, hydrogen peroxide.
6. the manufacture method of metal interconnecting as claimed in claim 5 is characterized in that, described oxygen-containing gas comprises carbon dioxide.
7. the manufacture method of metal interconnecting as claimed in claim 3 is characterized in that, described deposition comprises that more a helium or argon gas are as carrier gas.
8. the manufacture method of metal interconnecting as claimed in claim 1 is characterized in that, adds the electricity slurry handling procedure of a hydrogen in the processing procedure of described step (c).
9. the manufacture method of metal interconnecting as claimed in claim 1 is characterized in that, more comprises step (d) this opening of electricity slurry routine processes with a hydrogen after the described step (c).
L0. the manufacture method of metal interconnecting as claimed in claim 1 is characterized in that, the opening of described step (c) is an interlayer hole.
11. the manufacture method of metal interconnecting as claimed in claim 1 is characterized in that, the opening of described step (c) is a groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02144078 CN1243378C (en) | 2002-09-29 | 2002-09-29 | Process for preparing metallic interconnection wire |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02144078 CN1243378C (en) | 2002-09-29 | 2002-09-29 | Process for preparing metallic interconnection wire |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1485896A true CN1485896A (en) | 2004-03-31 |
| CN1243378C CN1243378C (en) | 2006-02-22 |
Family
ID=34148388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02144078 Expired - Lifetime CN1243378C (en) | 2002-09-29 | 2002-09-29 | Process for preparing metallic interconnection wire |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7557025B2 (en) | 2005-11-04 | 2009-07-07 | United Microelectronics Corp. | Method of etching a dielectric layer to form a contact hole and a via hole and damascene method |
| CN102185045A (en) * | 2011-04-06 | 2011-09-14 | 晶能光电（江西）有限公司 | Method for treating surface of SiO2 layer in manufacturing process of semiconductor luminescent device |
| CN102386126A (en) * | 2010-09-03 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing structure of semiconductor device for forming structure of dual damascene |
| CN103021839A (en) * | 2012-11-28 | 2013-04-03 | 上海华力微电子有限公司 | Method for improving adhesive force of nitrogen-free medium antireflection coating film and photoresist |
-
2002
- 2002-09-29 CN CN 02144078 patent/CN1243378C/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7557025B2 (en) | 2005-11-04 | 2009-07-07 | United Microelectronics Corp. | Method of etching a dielectric layer to form a contact hole and a via hole and damascene method |
| CN102386126A (en) * | 2010-09-03 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing structure of semiconductor device for forming structure of dual damascene |
| CN102386126B (en) * | 2010-09-03 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing structure of semiconductor device for forming structure of dual damascene |
| CN102185045A (en) * | 2011-04-06 | 2011-09-14 | 晶能光电（江西）有限公司 | Method for treating surface of SiO2 layer in manufacturing process of semiconductor luminescent device |
| CN103021839A (en) * | 2012-11-28 | 2013-04-03 | 上海华力微电子有限公司 | Method for improving adhesive force of nitrogen-free medium antireflection coating film and photoresist |
| CN103021839B (en) * | 2012-11-28 | 2015-06-17 | 上海华力微电子有限公司 | Method for improving adhesive force of nitrogen-free medium antireflection coating film and photoresist |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1243378C (en) | 2006-02-22 |
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