CN1484295A - Method for mfg. channel capacitor of mixing analogue unit - Google Patents
Method for mfg. channel capacitor of mixing analogue unit Download PDFInfo
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- CN1484295A CN1484295A CNA021427046A CN02142704A CN1484295A CN 1484295 A CN1484295 A CN 1484295A CN A021427046 A CNA021427046 A CN A021427046A CN 02142704 A CN02142704 A CN 02142704A CN 1484295 A CN1484295 A CN 1484295A
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Abstract
This invention discloses a method for manufacturing a channel capacitor of a mixed analog component, when forming a shallow ditch isolated zone in a semiconductor base for isolating component active zone, TiN layer dielectric layer and upper electrode metal layer of the lower layer electrode are formed orderly in multiple shallow channels to be combined to process channel capacitors to replace known cubic structure condensers for adding surface area of the capacitor.
Description
Technical field
The present invention relates to a kind of manufacturing method of semiconductor module, particularly about the manufacture method of the ditching type capacitor of a kind of hybrid analog-digital simulation assembly (Mixed Mode Analog Device).
Background technology
The hybrid analog-digital simulation assembly is meant in the logic region of semiconductor chip, have simultaneously as the digital assembly of amplifier, analog-digital converter etc. and as the circuit of the simulated assembly of positive inverter, adder etc., and be metal-oxide-semiconductor (MOS) (MOS) and the capacitor that includes constituent components in this hybrid analog-digital simulation circuit.
The method of the known capacitor of making the hybrid analog-digital simulation assembly in the deep-sub-micrometer semiconductor manufacturing process as shown in Figure 1, at first, in semiconductor substrate 10, be formed with basic modules such as shallow trench isolation regions (STI) 12, transistor grid structure 14, lightly-doped source/drain region 16, grid gap wall 18 and heavy-doped source/drain region 20 in regular turn; After each basic module on the semiconductor-based end 10 is all finished, aim at the manufacturing process of metal silicide voluntarily, be formed with metal silicide 32 on this grid structure 14, source/drain region 20 and part surface, deposition one chemical gaseous phase insulating barrier 22 on this semiconductor-based end 10 continues, form a metal level 24, a dielectric layer 26 and a metal level 28 afterwards more thereon in regular turn, to finish a MIM (Metal InsulatorMetal) capacitor 30 structures.
Owing to the capacitance of capacitor is that surface area along with electrode increases, and because of its dielectric material has higher dielectric constant, or because of the thickness of dielectric layer reduces, and then form the higher dielectric layer of a kind of dielectricity.But, do not causing that the minimizing of medium thickness is limited to easily under the prerequisite that dielectric lost efficacy, therefore the method for known increase capacitance concentrates on the surface area that increases electrode mostly, or uses the dielectric layer of a high dielectric constant.
In order to increase the surface area of electrode, known is to have stereochemical structure by one, and as cylindrical-shaped structure, or other increases height and is hemispherical grain (the Hemi Spherical Grain of material with the polysilicon, HSG) structure increases the effective area of lower electrode.Yet the lower electrode of above-mentioned cylindric or hemispherical polysilicon shape graininess stereochemical structure all has the degree of difficulty on some degree on making; And these known technologies all can cause the increase of lower electrode height and the height of peripheral circuit that very big difference is arranged, the gap of this kind kenel height (topology) makes the complexity of follow-up manufacture process raise many, especially the control of the manufacturing process in the middle of little shadow (Photolithography photolithography, photolithography) manufacturing process will become and be difficult to control.
Therefore, the present invention is at above-mentioned puzzlement, proposes a kind of manufacture method of ditching type capacitor of hybrid analog-digital simulation assembly, to overcome the disappearance that known increase because of electrode surface area causes kenel difference in height distance.
Summary of the invention
Main purpose of the present invention is the manufacture method at the ditching type capacitor that a kind of hybrid analog-digital simulation assembly is provided, and it is to form capacitor in the MIM mode in shallow trench, to increase the surface area of electrode for capacitors.
Another object of the present invention is the manufacture method at the ditching type capacitor that a kind of hybrid analog-digital simulation assembly is provided, it is to utilize ditching type capacitor to replace the stereochemical structure capacitor, so can effectively reduce the difference of lower electrode height and peripheral circuit height, make the gap of its no kenel height, to reduce the control complexity of follow-up manufacturing process.
A further object of the present invention is the manufacture method at the ditching type capacitor that a kind of hybrid analog-digital simulation assembly that improves assembly manufacturing process and complexity thereof is provided.
For reaching above-mentioned purpose, the present invention forms one first shallow trench isolation regions and second shallow trench isolation regions in the semiconductor substrate, and is to have formed basic modules such as grid structure, source/drain region between this first shallow trench isolation regions; Forming one first patterning photoresist layer on this semiconductor-based end on this semiconductor-based end, only expose this second shallow trench isolation regions, and remove the oxide in it and only stay several shallow trench; In the semiconductor-based end around the shallow trench, utilize implanting ions to form a conductive layer, then remove this first patterning photoresist layer; Continuing forms the titanium nitride layer of metal silicide and lower floor's electrode on grid structure, source/drain region and shallow trench surface, and forms a dielectric layer and a top electrode metal level on titanium nitride layer; Utilize one second patterning photoresist layer to be shielding again, remove top electrode metal level, dielectric layer and the titanium nitride layer that expose this first shallow trench isolation regions top, make this top electrode metal level, dielectric layer and the titanium nitride layer that are arranged in these irrigation canals and ditches form a ditching type capacitor.
Below illustrate in detail by the specific embodiment conjunction with figs., when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.
Description of drawings
Fig. 1 is the known semiconductor structure schematic diagram that is manufactured with MIM capacitor.
Fig. 2 (a) is that the present invention is in each step structure cutaway view of making the hybrid analog-digital simulation assembly to Fig. 2 (f).
Fig. 3 is the structure vertical view of the ditching type capacitor of the present invention after finishing.
Embodiment
Knownly utilize lower electrode cylindric or hemispherical polysilicon shape graininess stereochemical structure to increase the surface area of electrode, except the manufacturing process difficulty, it is many to cause the complexity of follow-up manufacturing process to raise, and manufacturing process control is become be difficult to control.And the present invention utilizes ditching type capacitor to replace the stereochemical structure capacitor, to improve known disappearance, make its can increase electrode surface area the time, reduce the control complexity of follow-up manufacturing process simultaneously.
Fig. 2 (a) is that a preferred embodiment of the present invention is at each step structure cutaway view of making the hybrid analog-digital simulation assembly to Fig. 2 (f), as shown in the figure, the main manufacture method of the present invention is to include the following step: shown in Fig. 2 (a), semiconductor substrate 40 is provided earlier, be formed with first shallow trench isolation regions (shallow trench isolation in it, STI) 42 and second shallow trench isolation regions 44, wherein second shallow trench isolation regions 44 is for reserving as the usefulness that forms ditching type capacitor.Form a transistor grid structure 46 prior to 42 of first shallow trench isolation regions at the semiconductor-based end 40, it is to comprise the polysilicon layer 462 on a upper strata and the grid oxic horizon 464 of lower floor; Be shielding with grid structure 46 then, the implanting ions first time of a low concentration is carried out in semiconductor substrate 40, to form lightly-doped source/drain region 48; Again in the other grid gap wall 50 that forms of two sidewalls of grid structure 46.
Then, after this lightly-doped source/drain region 48 forms, carry out high-temperature activation earlier and handle, with the silicon crystal lattice on this surface, semiconductor-based ends 40 of reforming.After finishing, be shielding with grid structure 46 with grid gap wall 50 again, the implanting ions second time of a high concentration carried out in semiconductor substrate 40, so that form heavy-doped source/drain region 52; Then carry out a Rapid Thermal temper, become original crystalline state so that the amorphous silicon phenomenon tempering that produces is implanted because of ion in surface, the semiconductor-based ends 40, the basic module at the semiconductor-based end 40 is so far finished.
Then shown in Fig. 2 (b), form one first patterning photoresist layer 54 on this semiconductor-based end 40, only expose second shallow trench isolation regions 44 that desire forms capacitor, with this first patterning photoresist layer 54 is shielding, removes dielectric oxide layer in this second shallow trench isolation regions 44 and lining oxide layer and only stays several shallow trench 56; Then carry out an implanting ions step, in the semiconductor-based end 40 around the shallow trench 56, form a conductive layer 58, can remove this first patterning photoresist layer 54 after finishing.
Then, aim at the step of metal silicide voluntarily, on this semiconductor-based end 40, deposit a titanium coating (not shown) earlier, and then form the titanium nitride layer then synchronously on this titanium coating, through overheated temper, make and produce titanium silicide 60 on grid structure 46 and the source/drain region 52, shown in Fig. 2 (c), also form metal silicide 60 simultaneously in the shallow trench 56 in this moment second shallow trench isolation regions 44, and have titanium nitride layer 62 be covered in metal silicide 60 on.Titanium nitride layer 62 is covered in and helps metal silicide 60 stable formation when high tempering on the titanium coating, and also can be used as the usefulness of lower electrode.
Shown in Fig. 2 (d), after the titanium nitride layer 62 of aiming at titanium silicide 60 and lower electrode voluntarily forms, can on titanium nitride layer 62, successively form a dielectric layer 64 and a top electrode metal level 66.Wherein, the material of this dielectric layer 64 is to be silica, silica/silicon nitride, tantalum oxide or other dielectric material; And the material of this top electrode metal level 66 is to be titanium nitride, aluminium, copper, tungsten or other connatural metal material.
Form one second patterning photoresist layer 68 again on this semiconductor-based end 40, shown in Fig. 2 (e), with expose this first shallow trench isolation regions 42 of not belonging to capacitor ranges and on basic module; With the second patterning photoresist layer 68 is shielding, this top electrode metal level 66 and the dielectric layer 64 that utilize the dry ecthing mode to remove to expose, and utilize the wet etching mode to remove the titanium nitride layer 62 of lower electrode and the titanium coating that unreacted becomes titanium silicide 60, this second patterning photoresist layer 68 is removed in etching more at last, make this top electrode metal level 66, dielectric layer 64 and the titanium nitride layer 62 that are arranged in these irrigation canals and ditches shallow 56 form a ditching type capacitor, this ditching type capacitor promptly is formed in the shallow trench in the MIM mode.
In addition, as shown in Figure 3, titanium silicide 60 and conductive layer 58 in this ditching type capacitor periphery are the usefulness that can be used for the lower electrode and the external circuit of capacitor.
The present invention is the manufacture method that proposes a kind of ditching type capacitor of the hybrid analog-digital simulation assembly that improves assembly manufacturing process and complexity thereof, it is to form ditching type capacitor in the MIM mode in shallow trench, replace the stereochemical structure capacitor with ditching type capacitor, so can effectively reduce the difference of lower electrode height and peripheral circuit height, make the gap of its no kenel height, to reduce the control complexity of follow-up manufacturing process, and can effectively increase simultaneously the surface area of electrode for capacitors, to increase the capacitance of ditching type capacitor.
Above-described embodiment only is for technological thought of the present invention and characteristics are described, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when can not with qualification claim of the present invention, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim of the present invention.
Claims (11)
1, a kind of manufacture method of ditching type capacitor of hybrid analog-digital simulation assembly is characterized in that comprising the following steps:
In the semiconductor substrate, be formed with first shallow trench isolation regions and one second shallow trench isolation regions in order to isolated master, passive component, and be to have formed grid structure, the source/basic assemblies of semiconductor such as drain zone between this first shallow trench isolation regions;
Forming one first patterning photoresist layer on this semiconductor-based end, only expose this second shallow trench isolation regions, is shielding with this first patterning photoresist layer, removes the oxide in this second shallow trench isolation regions and only stays several shallow trench;
Carry out an implanting ions step, in the semiconductor-based end around this shallow trench, form a conductive layer, remove this first patterning photoresist layer after finishing;
Aiming at the step of metal silicide voluntarily, is to be formed with metal silicide in this grid structure, source/drain zone and this shallow trench surface, and on it and be coated with the titanium nitride layer, and this titanium nitride layer is as lower electrode;
On this titanium nitride layer, form a dielectric layer and a top electrode metal level in regular turn;
Form one second patterning photoresist layer on this semiconductor-based end, with expose this first shallow trench isolation regions and on basic module; And
With this second patterning photoresist layer is shielding, removes this top electrode metal level, dielectric layer and the titanium nitride layer that expose, makes this top electrode metal level, dielectric layer and the titanium nitride layer that are arranged in these irrigation canals and ditches form a ditching type capacitor.
2, manufacture method according to claim 1 is characterized in that the method that forms the basic assembly of this semiconductor in this semiconductor-based end more comprises the following steps:
On this semiconductor-based end, form a grid structure, comprise the polysilicon layer of a grid oxic horizon and top thereof;
With this grid structure is shielding, carries out the implanting ions of a low concentration, forms lightly-doped source/drain zone in this semiconductor-based end;
Be formed with grid gap wall in this grid structure sidewall;
Carrying out high-temperature activation handles;
With this grid structure and grid gap wall is shielding, a high concentration ion cloth is carried out at this semiconductor-based end plant, to form heavy-doped source/drain zone; And this is carried out the semiconductor-based end carry out hot temper.
3, manufacture method according to claim 1 is characterized in that the oxide in this second shallow trench isolation regions is to comprise a dielectric layer and a lining oxide layer.
4, manufacture method according to claim 1 is characterized in that forming this step of aiming at metal silicide voluntarily and more comprises:
On this semiconductor-based end, form earlier a metal level and titanium nitride layer in regular turn; And
Carry out a hot temper, make with this grid structure, source/drain zone and this shallow trench surface this metal level of contacted part to be transformed into metal silicide.
5, manufacture method according to claim 4 is characterized in that being shielding with this second patterning photoresist layer simultaneously, removes the metal level that unreacted becomes this metal silicide.
6, manufacture method according to claim 5 is characterized in that it is to utilize the wet etching mode to remove it that this unreacted becomes this metal level of metal silicide.
7, manufacture method according to claim 1, the material that it is characterized in that this dielectric layer are to be silica, silica/silicon nitride, tantalum oxide or other dielectric material.
8, manufacture method according to claim 1, the material that it is characterized in that this top electrode metal level are to be titanium nitride, aluminium, copper, tungsten or other connatural metal material.
9, manufacture method according to claim 1 is characterized in that removing this top electrode metal level and utilizes the dry ecthing mode to finish.
10, manufacture method according to claim 1 is characterized in that removing this dielectric layer and utilizes the dry ecthing mode to finish.
11, manufacture method according to claim 1 is characterized in that removing this bottom electrode titanium nitride layer and utilizes the wet etching mode to finish.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021427046A CN1484295A (en) | 2002-09-18 | 2002-09-18 | Method for mfg. channel capacitor of mixing analogue unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021427046A CN1484295A (en) | 2002-09-18 | 2002-09-18 | Method for mfg. channel capacitor of mixing analogue unit |
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| CN1484295A true CN1484295A (en) | 2004-03-24 |
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| CNA021427046A Pending CN1484295A (en) | 2002-09-18 | 2002-09-18 | Method for mfg. channel capacitor of mixing analogue unit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376755A (en) * | 2010-08-23 | 2012-03-14 | Nxp股份有限公司 | Tantalum-based electrode stack |
| CN102709311A (en) * | 2011-02-17 | 2012-10-03 | 美士美积体产品公司 | Deep trench capacitor with conformally-deposited conductive layers having compressive stress |
| CN102723262A (en) * | 2012-06-26 | 2012-10-10 | 上海宏力半导体制造有限公司 | Semiconductor capacitor formation method |
| CN102931239A (en) * | 2011-08-10 | 2013-02-13 | 无锡华润上华科技有限公司 | Semiconductor device and manufacturing method thereof |
| CN106469716A (en) * | 2016-11-25 | 2017-03-01 | 南通沃特光电科技有限公司 | A kind of vertical-type capacitor arrangement |
| CN106952895A (en) * | 2017-02-22 | 2017-07-14 | 南通沃特光电科技有限公司 | A kind of manufacture method of MIM capacitor structure |
| CN110534505A (en) * | 2019-08-29 | 2019-12-03 | 华中科技大学 | A kind of three-dimensional ferroelectric capacitor device, preparation method and ferroelectric memory |
-
2002
- 2002-09-18 CN CNA021427046A patent/CN1484295A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376755A (en) * | 2010-08-23 | 2012-03-14 | Nxp股份有限公司 | Tantalum-based electrode stack |
| CN102709311A (en) * | 2011-02-17 | 2012-10-03 | 美士美积体产品公司 | Deep trench capacitor with conformally-deposited conductive layers having compressive stress |
| CN102709311B (en) * | 2011-02-17 | 2016-11-02 | 马克西姆综合产品公司 | Deep-trench capacitor with the conformal deposit conductive layer with compression stress |
| CN102931239A (en) * | 2011-08-10 | 2013-02-13 | 无锡华润上华科技有限公司 | Semiconductor device and manufacturing method thereof |
| CN102931239B (en) * | 2011-08-10 | 2016-12-21 | 无锡华润上华科技有限公司 | Semiconductor device and manufacture method thereof |
| CN102723262A (en) * | 2012-06-26 | 2012-10-10 | 上海宏力半导体制造有限公司 | Semiconductor capacitor formation method |
| CN102723262B (en) * | 2012-06-26 | 2016-09-07 | 上海华虹宏力半导体制造有限公司 | The forming method of semiconductor capacitor |
| CN106469716A (en) * | 2016-11-25 | 2017-03-01 | 南通沃特光电科技有限公司 | A kind of vertical-type capacitor arrangement |
| CN106469716B (en) * | 2016-11-25 | 2019-02-05 | 南通壹选工业设计有限公司 | A kind of vertical-type capacitor arrangement |
| CN106952895A (en) * | 2017-02-22 | 2017-07-14 | 南通沃特光电科技有限公司 | A kind of manufacture method of MIM capacitor structure |
| CN106952895B (en) * | 2017-02-22 | 2019-05-10 | 新昌县诺趣智能科技有限公司 | A kind of manufacturing method of MIM capacitor structure |
| CN110534505A (en) * | 2019-08-29 | 2019-12-03 | 华中科技大学 | A kind of three-dimensional ferroelectric capacitor device, preparation method and ferroelectric memory |
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