CN1484294A - Method for eliminating signal crosstalk resulted from coupling capacitance of conductive line in deep submicvometer technology - Google Patents
Method for eliminating signal crosstalk resulted from coupling capacitance of conductive line in deep submicvometer technology Download PDFInfo
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- CN1484294A CN1484294A CNA021424896A CN02142489A CN1484294A CN 1484294 A CN1484294 A CN 1484294A CN A021424896 A CNA021424896 A CN A021424896A CN 02142489 A CN02142489 A CN 02142489A CN 1484294 A CN1484294 A CN 1484294A
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Abstract
This invention relates to a method for eliminating signal crosstalk resulted by linking coupling condensers in deep micrometer technology including the following steps: detailed wiring, preparing for processing technology of super large scale IC, extraction of parasitic parameters, analyzing influence of coupling condenser to chips, generation of standard delay documents for generating time window document of smallest and largest source resistance not containing signal up and down, examination of coupling condenser crosstalk to generate restored documents, selection of restoration way: determining restoring manually or returning to global wiring, restoration: restoring link crosstalked by coupling condenser, outputting data form of the mask to process.
Description
Technical field
The invention provides a kind of method of eliminating the signal cross-talk that the line coupling capacitance causes, be meant a kind of method of eliminating the signal cross-talk that the line coupling capacitance causes in the deep submicron process especially.
Background technology
CPU is the english abbreviation of central processing unit (Central Processing Unit).Be the core apparatus of computer and all kinds of modern electronic equipments, undertake the execution various command, finish the task of various mathematics and logical operation.Make a general survey of all kinds of cpu chips, the universal cpu chip is being led the trend of technical development.All kinds of technology of raising chip performance all at first are applied in the universal cpu chip and promote.The dominant frequency of PentiumIV is the key character of CPU industry at a high speed near 3000MHz in the Pentium of Intel Company (pentium) series.
As everyone knows, developed countries such as the U.S. call semi-conductor industry " strategic industry " because semi-conductor industry has influence on the technological precedence status of many related industries (as computer, telecommunications, household electrical appliances) and the technical advantage that national security is relied on.Although today, the gross output value of global semiconductor had only 200,000,000,000 dollars, only be 5% of the whole electronics industry output value.But semi-conductive 200,000,000,000 dollars of 4,000,000,000,000 dollars of controlling whole electronics industry.And the great demand of high-performance cpu chip is just promoting semiconductor process techniques continuous progress to sub-micro from the sub-micron to the deep-submicron.Therefore the cpu chip technology has the fundamental position of core in information industry.
In the economic competition and inter-industry competition of following message area, whether grasp core technology, will be decision key of success place.Especially development of Internet makes government, enterprise and the public's routine work more and more depend on network.Therefore the fail safe of guarantee information system has been an outstanding key issue.And a large amount of vital data of computer system and information all are stored in server end.Can think that the fail safe that ensures server end is the most key.This is embodied in following two aspects with regard to the fail safe that requires us must develop CPU: can not leave the back door of unknowable secure context and can add the security control of resisting attack.Thereby guarantee the safety of server.Just increase with 15% speed current demand every year to integrated circuit (IC) chip.Integrated circuit output reached 2,400,000,000 in 1999, and sales volume is near 10,000,000,000 yuan.And the development trend of international integrated circuit technology in 1997 to 2009 can be summarized two features: lines are more and more little, from 0.25u to 0.09u (IBM has succeeded in developing the circuit of 0.09u technology); Scale is more and more big, from 5,000,000 to 1,500 ten thousand (oneself succeeds in developing 600,000,000 transistor circuits Fujitsu).This has just caused because the crosstalk signal that the coupling capacitance between line produces.As shown in Figure 1:
Crosstalking between sort signal is different and different with line thickness: 0.25u begins to occur, and 0.18u is comparatively serious, and＜0.18u is then very serious.This problem is not if solve, and its consequence is very fearful: even processing technology is flawless, the design rule perfection meets, and analog simulation is correct, and the chip of producing still can't be worked.Visible function is undesired, can not touch inoperable reason.Therefore, the problem that solves the signal cross-talk that coupling capacitance causes has become one of the most popular technology of development High Speed ICs chip.The whole world each big IC R﹠D firm such as Intel etc. have all proposed own ways of addressing this issue but have kept secret.Each big eda software company of the whole world has developed the instrument (Envisia of placement-and-routing with signal integrity as benefit China (Cadence) company
TMPlaceand Route With Signal Integrity) is called SE_SI (Silicon Ensemble Place andRoute-Envisia
TMPlace and Route with Signal Integrity), but the algorithm of the signal cross-talk that SE_SI causes coupling capacitance is compared too pessimistic with the crossfire value of reality, and reason is that this algorithm all stacks up the coupling capacitance of all invasion lines (aggressive net) in the one-period and does harm in the killed line (victim net).In fact, the coupling capacitance of some invasion can be done harm to killed line, and the coupling capacitance of some invasion is then to the not influence of killed line.The notion of " time window " that proposes in the Celtic program that Here it is (Timing window).Each line calculates their signals in the same clock cycle by static timing analyzer (Pearl) and rises the earliest time of (or decline) and time the latest, the minimum slope of signal rising (or decline), the greatest gradient of signal rising (or decline), the minimum source resistance of signal rising (or decline), the maximum source resistance of signal rising (or decline).When having only " time window " and phase place overlapping when the invasion line opposite, just understand the changing function that may make the line of being injured with " time window " of the line of being injured.Released physical synthesis instrument PKS (Envisia afterwards again
TMPhysicallyKnowledgeable Synthesis).Formed SE-PKS and repaired the flow process that coupling capacitance causes signal cross-talk, as shown in Figure 2.On March 9th, 2002, Cadence releases the PKS of 5.0 up-to-date versions again.It is bundled among the PKS its flow process with coupling capacitance fully to the recovery of signal cross-talk
Fig. 4
The layout data of wiring proposes whole coupling capacitances, the standard parasitic parameter swap file of direct-to-ground capacitance and resistance;
Step 3, the standard delay file produces: do not contain signal rising or the minimum source resistance that descends and " time window " file of maximum source resistance in order to produce;
Step 4, coupling capacitance are crosstalked and are checked and produce the reparation file;
Step 5, repair mode is selected: according to the quantity of repairing the contained line that must repair in the file, determine to repair still to turn back in the global routing by hand to repair;
Step 6 is repaired: in global routing, the line that crosstalked by coupling capacitance is repaired;
Step 7, the data format of output mask: after having removed crosstalking that coupling capacitance causes fully, with the layout data of chip carry out Design Rule Checking and domain to the conforming inspection of logic diagram errorless after, output mask data format carries out processing technology.
The generation step of wherein said standard delay file comprises step and the signal rising of all lines or the minimum source resistance value that descends that is generated " time window " by the standard delay file, and the signal of line rises or the maximum source resistance value that descends all is changed to " 0 ".
The generation of described reparation file, the attribute that comprises direct these lines of definition are that the spacing with other line will be broadened, and are added in the net table that has the geometric position that generates behind the detailed routing.
Describedly in global routing, the line that the coupling capacitance cross-interference issue is arranged is repaired, comprised timing optimization and area-optimized.
Description of drawings
For further specifying technology contents of the present invention, below in conjunction with drawings and Examples the present invention is done a detailed description, wherein:
Fig. 1 is the structural representation of crosstalking that coupling capacitance produces;
Fig. 2 is the existing flow chart that coupling capacitance causes signal cross-talk of repairing;
Fig. 3 is that existing another repaired the flow chart that coupling capacitance causes signal cross-talk;
Fig. 4 is the flow chart that reparation coupling capacitance of the present invention causes signal cross-talk.
Embodiment
See also shown in Figure 4, in order to overcome the SE-PKS that goes up surface analysis and in PKS 5.0, to repair coupling capacitance and cause three shortcomings in the signal cross-talk method.Our invention has proposed the purpose that flow process shown in Figure 4 reaches our invention.
Step 1 (S10): detailed routing, very lagre scale integrated circuit (VLSIC) is before manufacture craft, the good mask of etching must be arranged, the quantity of mask is by providing by sequential passed examination, detailed routing data that the post-simulation function is qualified, the layout data that detailed routing is finished, extract the band coupling capacitance, the standard parasitic parameter swap file (SPEF) of direct-to-ground capacitance and resistance;
Step 2 (S20): parasitic parameter extracts, in order to analyze the influence of coupling capacitance to chip, the layout data of detailed routing must be proposed to comprise whole coupling capacitances, the standard parasitic parameter swap file (SPEF) of direct-to-ground capacitance and resistance utilizes static timing analyzer (Pearl) to convert parasitic parameter file (SPEF) to standard delay file (SDF).This file has filtered the signal resistance of each root line automatically, has quite increased the driving force of each root line.Because the invasion line is more in the same clock cycle than the line of being injured, like this, crosstalking that the line of being injured is subjected to is more than the actual line of being injured, thereby fluctuation and the systematic error having avoided extracting precision because of parasitic parameter have filtered the line that should repair;
Step 3 (S30): standard delay file (SDF) produces, generate " time window " (Timing Window) with the standard delay file, what is called " time window " is meant with minimum slope minimum source resistance and the maximum source resistance with maximum oblique, signal rising (or descend) of static timing analyzer (Pearl) with the earliest time of the signal rising (or decline) of each bar line in the same clock cycle and time, signal rising (or decline) the latest and all calculates, generates one " time window " (Timing Window) file; Generating the purpose of standard delay file (SDF), is the minimum of signal, maximum source resistance to be changed to " 0 " automatically so that improve the precision of repairing;
Step 4 (S40): the generation of repairing file, after " time window " (Timing Window) file is produced by standard delay file (SDF), need to repair in conjunction with calculating which line of being injured in relevant noise storehouse, chip design data and " time window " file with the Celtic program, generate and repair file;
Step 5 (S50): repair mode is selected, and,, directly generates the GDSII file and does DRC, LVS, day ray examination after then can repairing by hand as if＜10 according to the line number of repairing needs reparation in the file.Can throw sheet after qualified; Repair and to need line number＞10 of repairing in the file, then will repair the line in the file and the spacing of other lines and give the attribute of widening, and join in the net table that has the geometric position that generates behind the detailed routing, have and widen and the net table of other line thereby obtain new, the band line geometric position, that will repair apart from attribute;
Step 6 (S60): repair, in global routing (Globle Route), the line that crosstalked by coupling capacitance is repaired, newly-generated net table is dropped in the program of " global routing ", so-called " global routing " (Globle Route) i.e. be " detailed routing " planning wiring before.It carries out after layout.Because when wiring planning just can consider which line must draw back and other line between distance, in case planning connect up finish after, program itself also can be optimized by the time-constrain of whole system.Therefore, after overall situation planning wiring is finished, neither can increase the time of delay of chip.(because the line number that will repair is more much smaller than total line number, chip for 1,000,000 scales, nearly 3000 of the line number of repairing, and its total line number is more than 1,000 ten thousand) can not spend many times to repair line, program running can be finished in maximum one day.Pressing the flow process of SE-PKS or PKS 5.0, is to go to read one to repair file in the detailed routing program, goes to adjust the distance of many lines like this in a design of the intact line of cloth again, tends to increase the time of delay of chip and very time-consuming.
Step 7 (S70): the data format (GDSII) of output mask, after having removed crosstalking that coupling capacitance causes fully, with the layout data of chip carry out design planning inspection (DRC) and domain to the conforming inspection of logic diagram (LVS) errorless after, output mask data format (GDSII) carries out processes;
After global routing finished, flow process was got back in the detailed routing routinely again; Repeat Fig. 4 flow process, can obtain to eliminate the signal cross-talk that coupling capacitance causes.In our experience, as long as a global routing repairs, one time repaired by hand can enter data format (GDSII) program of output mask.
Effect of the present invention
The present invention has designed two 32 CPU.Estimate according to Chevron Research Company (CRC) overseas: the chip that 0.18u technology is about 700,000 will be repaired the signal cross-talk that coupling capacitance causes needs the operating frequency of 2-3 time-of-week and chip to descend approximately.And we have only used 2-3 days time, reparation is over because the signal cross-talk that coupling capacitance produces, chip is once thrown the sheet success, the operating frequency of emulation and function and the actual operating frequency of measuring and function are in full accord, this just explanation, though be the technology of 0.18u, 620,000 scales there is no signal cross-talk.Illustrate that the present invention has received expected effect.
Claims (4)
1. a method of eliminating the signal cross-talk that the line coupling capacitance causes in the deep submicron process is characterized in that, this method comprises the steps:
Step 1, detailed routing: for the manufacture craft of making very lagre scale integrated circuit (VLSIC) is prepared;
Step 2, parasitic parameter are extracted: in order to analyze the influence of coupling capacitance to chip, the layout data of detailed routing is proposed whole coupling capacitances, the standard parasitic parameter swap file of direct-to-ground capacitance and resistance;
Step 3, the standard delay file produces: do not contain signal rising or the minimum source resistance that descends and " time window " file of maximum source resistance in order to produce;
Step 4, coupling capacitance are crosstalked and are checked and produce the reparation file;
Step 5, repair mode is selected: according to the quantity of repairing the contained line that must repair in the file, determine to repair still to turn back in the global routing by hand to repair;
Step 6 is repaired: in global routing, the line that crosstalked by coupling capacitance is repaired;
Step 7, the data format of output mask: after having removed crosstalking that coupling capacitance causes fully, with the layout data of chip carry out Design Rule Checking and domain to the conforming inspection of logic diagram errorless after, output mask data format carries out processing technology.
2. the method for the signal cross-talk that the line coupling capacitance causes in the elimination deep submicron process according to claim 1, it is characterized in that, the generation step of wherein said standard delay file comprises the step that is generated " time window " by the standard delay file, rise or the minimum source resistance value that descends with the signal of all lines, the signal of line rises or the maximum source resistance value that descends all is changed to " 0 ".
3. the method for the signal cross-talk that the line coupling capacitance causes in the elimination deep submicron process according to claim 1, it is characterized in that, the generation of described reparation file, the attribute that comprises direct these lines of definition is that the spacing with other line will be broadened, and is added in the net table that has the geometric position that generates behind the detailed routing.
4. the method for the signal cross-talk that the line coupling capacitance causes in the elimination deep submicron process according to claim 1 is characterized in that, describedly in global routing the line that the coupling capacitance cross-interference issue is arranged is repaired, and comprises timing optimization and area-optimized.
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| CN 02142489 CN1234162C (en) | 2002-09-20 | 2002-09-20 | Method for eliminating signal crosstalk resulted from coupling capacitance of conductive line in deep submicvometer technology |
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| CN 02142489 CN1234162C (en) | 2002-09-20 | 2002-09-20 | Method for eliminating signal crosstalk resulted from coupling capacitance of conductive line in deep submicvometer technology |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986315A (en) * | 2010-11-19 | 2011-03-16 | 杭州开鼎科技有限公司 | Method for physically implementing special integrated circuit chip under deep sub-micron |
| CN102521468A (en) * | 2011-12-30 | 2012-06-27 | 中国科学院微电子研究所 | Method for extracting parasitic parameters of interconnection lines and device |
| CN113030609A (en) * | 2021-02-25 | 2021-06-25 | 长鑫存储技术有限公司 | Crosstalk effect testing method, circuit and device |
| US11860222B2 (en) | 2021-02-25 | 2024-01-02 | Changxin Memory Technologies, Inc. | Method, circuit and apparatus for testing crosstalk effect |
-
2002
- 2002-09-20 CN CN 02142489 patent/CN1234162C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986315A (en) * | 2010-11-19 | 2011-03-16 | 杭州开鼎科技有限公司 | Method for physically implementing special integrated circuit chip under deep sub-micron |
| CN102521468A (en) * | 2011-12-30 | 2012-06-27 | 中国科学院微电子研究所 | Method for extracting parasitic parameters of interconnection lines and device |
| CN113030609A (en) * | 2021-02-25 | 2021-06-25 | 长鑫存储技术有限公司 | Crosstalk effect testing method, circuit and device |
| WO2022179036A1 (en) * | 2021-02-25 | 2022-09-01 | 长鑫存储技术有限公司 | Crosstalk effect test method, circuit and apparatus |
| CN113030609B (en) * | 2021-02-25 | 2023-03-14 | 长鑫存储技术有限公司 | Crosstalk effect testing method, circuit and device |
| US11860222B2 (en) | 2021-02-25 | 2024-01-02 | Changxin Memory Technologies, Inc. | Method, circuit and apparatus for testing crosstalk effect |
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| Publication number | Publication date |
|---|---|
| CN1234162C (en) | 2005-12-28 |
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