CN1481008A - Embeded reliability analysis system applied to production of semiconductor products - Google Patents
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- CN1481008A CN1481008A CNA021368481A CN02136848A CN1481008A CN 1481008 A CN1481008 A CN 1481008A CN A021368481 A CNA021368481 A CN A021368481A CN 02136848 A CN02136848 A CN 02136848A CN 1481008 A CN1481008 A CN 1481008A
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Abstract
The system is applicable to reliability analysis in wafer level. Using reliability analysis system and relevant conception integrates reliability information of all machines, flows and each batch of wafer in product developments, procedures and tests into a database, which is sorted then. Thus, when there is any change happened in any machine, flow and batch of wafer, the possible fault and solution can be determined from comparison with the database. Moreover, based on the integrated database (including qualified rate and reliability), reliability change of final product can be determined from any change from machines, flows and batches of wafer. The invention can be used to evaluate development of new manufacturing flow, lifetime of new product and solution scheme etc.
Description
Technical field
The present invention relates to use implanted reliability analysis system (building-in-reliability diagnosissystem, BIRDS), relate in particular to and use the in-building type reliability analysis system in the reliability analysis of wafer level (wafer-level) in production of semiconductor products.
Background technology
In the known technology, be mostly after wafer completion, crystal grain (chip) cutting are finished with the individual die encapsulation, the just reliability analysis of the semiconductor element that carries out and QC test.This is encapsulation level reliability (package-level reliability, test analysis PLR) general title.And because encapsulation level reliability analysis is used widely, not only Xiang Guan technology and product are ripe, test the gained data and analyze the also existing enough public credibility of gained result.
But encapsulation level reliability analysis has a unavoidable shortcoming: what relevant testing procedure was suitable takes time, easily the several months long.Therefore, along with commodity lifetime of semiconductor product shortens fast, the just predicament in the face of facing a difficult choice of the use of encapsulation level reliability analysis: if the several months consuming time encapsulates the reliability that the level reliability analysis is determined certain product, this product has often been missed market opportunity; If not making complete encapsulation level reliability analysis just allows certain launch to strive for timeliness, can not determine the reliability of this product again.
Simultaneously, along with the complexity day by day of semiconductor product, the board of the required step of carrying out of encapsulation level reliability analysis, required use and the number of required specimen all significantly increase.Owing in the known technology,,, do not have the QC and the reliability of all departments of integration (step/board/sample) with the QC and splendidization of reliability of this step/board/sample though individual steps, indivedual board and individual samples all have the special messenger to be responsible for.Therefore, the reliability of encapsulation level reliability analysis often can not splendidization (because may cancel out each other between the different departments), and Different Individual can not be shared each other experience and information.
In recent years, at encapsulation level reliability analysis shortcoming of a specified duration excessively consuming time, develop gradually such as companies such as moral continent instruments and the faster wafer level of test speed (wafer-level) reliability analysis.By in each die process on wafer or form and just to carry out reliability test after good, to be testedly (survey as the wafer pin, CP), can reduce the needed time of reliability test significantly by just cutting the practice of encapsulation after the checking.Certainly, the two step of wafer level reliability analysis and encapsulation level reliability analysis is different.
But, the practical application of known wafer level reliability analysis, still can meet with following two shortcomings: the first, known wafer level reliability analysis also can't effectively integrate the QC and the reliability of each step/board/sample, therefore often can not be with whole QC and reliability optimization; The second, some wafer level reliability analysis lacks experimental data and rationale, proves that itself and encapsulation level reliability analysis are equivalences.
In sum, the known technology relevant with reliability with the QC of manufacture of semiconductor all has the shortcoming of can not ignore that waits to solve.
Summary of the invention
Main purpose of the present invention provides the yield and the reliability that can effectively integrate each step/board/sample, and then with whole QC and reliability method for optimizing.
Another main purpose of the present invention provides data can prove the two method of equivalence and corresponding relation whether of wafer level reliability analysis and encapsulation level reliability analysis.
Essential characteristic of the present invention is to use the implanted reliability analysis that just is suggested in recent years, integrates each level reliability analysis.Particularly use database (database) and the analysis tool that is based upon various reliability analysis test datas, effectively bring into play the reliability analysis of various levels.Because the implanted reliability analysis system is a known technology, will seldom introduce at this, relevant details can be consulted at least: W.K.T.Kary Chien ﹠amp; Charles H.J.Huang, " Practical Building-In Reliability (BIR) Approaches forSemiconductor Manufacturing ", IEEE Transactions on Reliability, vol.51, no 3, and September 2002.
Application of the present invention at least also can have following several characteristic:
(1) utilize BIRDS, can grasp the relation of any parameter and final result, no matter this parameter is the parameter of final measurement/final products, or the parameter of middle measurements/intermediate products.Therefore, by reference BIRDS, can the product design stage just effectively assess each details with to the influence of final products reliability/quality, and need not wait until measurement and the correction of just carrying out reliability after product forms.
(2) any problem relevant with reliability can be recalled previously data by BIRDS, finds basic reason effectively according to experience and by inference engine.
(3) because BIRDS is the system of a conformability, can set up the database that comprises all and reliability related item under the prior art.New technology development, processing procedure optimization, processing procedure monitoring, reliability monitoring are improved with yield, important reference frame can be provided.
Description of drawings
Figure 1A to Figure 1B is the cross sectional representation of the principal character of known technology;
Fig. 1 C to Fig. 1 D is the cross sectional representation of principal character of the present invention;
Fig. 2 is the basic flow sheet of a preferred embodiment of the present invention;
Fig. 3 A to Fig. 3 C is the basic comprising figure of another preferred embodiment of the present invention; And
Fig. 4 A to Fig. 4 D shows known semiconductor fabrication schedule and the basic procedure of using semiconductor fabrication process of the present invention respectively.
Embodiment
At first, Figure 1A and Figure 1B show a big essential characteristic of known technology: only carry out the measurement of reliability (or QC) respectively and obtain relevant information 13 in each machine 11 and each step 12, but different machines 11 and different step 12 are not shared information 13 each other, and reciprocation arranged also between different platform, but these often are left in the basket, but these data there is no purposive being recorded, and are to have different systems scatteredly.
Relatively, Fig. 1 C and Fig. 1 D show of the present invention one big essential characteristic: all other information 13 immediately are integrated into a database 14, and use known implanted reliability analysis 15, modes such as matching computer chemical industry tool and statistics, obtain whole reliability analysis result, and be fed back to the carrying out of each machine 11 and each step 12.So do, the present invention not only can be before each step 11 and each machine 12 operate, and just considering may influence the factor of reliability and adjust; Can be in service at each step 12 and each machine 11, just immediately according to the contrast anticipation result's of measurement data and database 14 reliability and revise; More can integrate each machine 11 and each step 12 and not adjust, with the optimization reliability of pursuit final products or whole production line.
According to above-mentioned basic conception, a preferred embodiment of the present invention is a kind of method of using the in-building type reliability analysis system in production of semiconductor products.As shown in Figure 2, comprise following basic step at least:
Shown in the first background square 21, prepare a plurality of machines and a plurality of wafer.At this arbitrary machine is to be used at least one wafer is carried out at least one reliability analysis program, and arbitrary wafer is handled by a machine at least.
Shown in the second background square 22, prepare an in-building type reliability analysis system.This in-building type reliability analysis system comprises database (Database), assessment assembly (Assessment assembly), baseline assembly (Baseline assembly), control assembly (Control assembly) and development assembly (Developmentassembly), search assembly (Search assembly) at least, inquiry assembly (Query assembly) is with analysis assembly (Analysis assembly).
As adjust shown in the square 23, with reference to the in-building type reliability analysis system, adjust the parameter of these machines and these reliability analysis programs.
Measure shown in the square 24 as reliability, use these machines that these wafers are carried out these reliability analysis programs, and write down individual information more than arbitrary reliability analysis program, arbitrary machine and the arbitrary wafer simultaneously.At this, these information have more comprised the problem that the reliability analysis program is found or taken place except the measurement result of running parameter and arbitrary wafer of the operating parameters that comprises arbitrary reliability analysis program at least, arbitrary machine, and the mode of dealing with problems.
Shown in feedback square 25, analyze and integrate these information to the in-building type reliability analysis system, use the production reliability of acquisition semiconductor product and the processing procedure reliability of semiconductor product manufacture process, and upgrade the in-building type reliability analysis system.
At this, it must be emphasized that present embodiment does not limit the details of institute's use reliability routine analyzer, present embodiment can be applied in the traditional encapsulation level reliability analysis program or the wafer level reliability analysis program of recent products.The employed reliability analysis program of present embodiment can be one of following (but being not limited thereto) at least: processing procedure checking (Process Qualification) relative program, Product Validation (Product Qualification) relative program, processing procedure assessment (Process Evaluation) relative program, product assessment (ProductEvaluation) relative program, processing procedure monitoring (Process Monitor) relative program, regular product surveillance (Routine Product Monitor) relative program, online processing procedure assessment and monitoring (In-Line ProcessEvaluation ﹠amp; Monitor) relative program.
Processing procedure checking (Process Qualification) and monitoring (Monitor) relative program can be one of following (but being not limited thereto) at least: hot carrier injects test (Hot Carrier Injection Test), dielectric medium collapse time test (Time Dependent Dielectric Breakdown Test), breakdown voltage test (VoltageRamp Test), bias voltage temperature test (Bias Temperature Test), electron transfer test (Electromigration test), ion mobility test (Ion Mobile Test), stress migration test (Stress Migration Test), the electricity slurry causes to damage tests (Plasma Induced Damage Test).
Wafer level reliability control (Wafer-Level-Reliability Control) and monitoring (Monitor) and online processing procedure assessment and monitoring (In-Line Process Evaluation ﹠amp; Moni tor) relative program can be one of following (but being not limited thereto) at least: hot carrier injects test (Hot Carrier Injection Test), breakdown voltage test (Voltage Ramp Test), constant temperature electron transfer (Isothermal ElectromigrationTest).
The Product Validation relative program can be one of following (but being not limited thereto) at least: high temperature service life test (HighTemperature Operating Life Test), low temperature life test (Low Temperature OperatingLife Test), decreasing failure rate test (Early Failure Rate Test), accelerated ageing test (HighlyAccelerated Stress Test), pre-condition test (Pre-conditioning Test), pressure cooker test (Pressure Cooker Test), constant temperature and humidity test (Temperature ﹠amp; Humidity With BiasTest), thermal shock test (Thermal Shock Test), variations in temperature loop test (Temperature CyclingTest), high-temperature storage test (High Temperature Storage Test), low temperature stress test (LowTemperature Stress Test), quicken soft error rate test (Accelcrated Soft Error RateTest), electrostatic discharge testing (Electrostatic Discharge Test), bolt-lock test (Latch UpTest), system soft mistake rate test (System Soft Error Rate Test).
In addition, because the implanted reliability analysis that present embodiment is quoted is a kind of mode that can be fit to instant (in-time) reaction.Measure in the square 24 in reliability, present embodiment one side often carries out the reliability analysis program, and one side is analyzed corresponding information and integrate.Further, because conventional package level reliability analysis program often can not simultaneously be produced a planar survey, have only wafer level reliability analysis program recently often can simultaneously produce a planar survey, so present embodiment is specially adapted to the wafer level reliability analysis.
At this, because the in-building type reliability analysis is the notion that newly is suggested in recent years, be the notion of known technology and just almost specifically not used, at this, the details at the in-building type reliability analysis is not made an explanation, and just summary is described present embodiment and is used some principal characters of the reliability analysis system that is based upon the in-building type reliability analysis as follows:
(1) do not measure final products passively, but directly measure and most parameters of controlling the final products manufacture process.The flow process parameter of for example running parameter of each machine, or each step is with the precognition production reliability.
Most data of a plurality of the flow processs (sub-flow) (or saying a plurality of steps) of carrying out before and after in (2) the vertical integration entire flow (flow) are used and are overcome in the known technology shortcoming that the indivedual brilliant pipe/reliability relevent informations of homogeneous flow process not can't the systematization interchange.
(3) Horizontal Integration is with a plurality of data of a plurality of unit (as most machines) that carry out respectively simultaneously in flow process, uses the shortcoming that the indivedual QCs/reliability relevent information that overcomes different units in the known technology can't systematization exchanges.
(4), assess the influence of the variation in the reliability in arbitrary source and arbitrary source to integral body by continuing record and analyze many data that relatively come from a plurality of sources.
(5) set up the relation of reliability and other parameter by the method for data analysis.Can applicable data analysis have shellfish formula theorem (Bayesian Approach) at least at this, control chart (Statistical ControlChart), factor analysis (Factor Analysis), analysis of variance (Analysis of Variances), multi-variables analysis (Multivariate Analysis), discriminant analysis (Discriminant Analysis), principal component analysis (Principal component analysis), experimental design/reaction curved surface (Designs ofExperiments/Response Surface Method), regression analysis (Regression Analysis), decision tree (Decision Tree), enlightening Klatt program (Dirichlet Process), mixed integer programming (Mixed Integer Programming), linear and Non-Linear Programming (Linear/Non-linearProgramming), queuing theory (Queuing Theory), random process (Stochastic Process), MRP (Resources Planning), and other possible parameter has the processing procedure monitoring parameter at least, yield, specific wafer acceptance test (Wafer Acceptance Test) parameter, machine parameter on the line, the wafer pin is surveyed (Chip Probing) parameter, final (Final Test) parameter that detects, the reliability test parameter.
(6) reliability of setting up by data analysis and the relation of other parameter comprise the relation of the reliability of the parameter value of arbitrary this parameter and final products.Therefore, in the time of can finding that in processing procedure carries out this parameter value is unusual, just can predict the possible shortcoming and the reliability of final products, and then make amendment according to this.
(7) by the data analysis mode, the variation that concerns between reliability and some special parameter under the more different process technique provides the approach of calculating the reliability of new process technique from the reliability of existing process technique.For example according to mature 0.30,025,0.20 the test data of the electron transfer test of micron system and 0.18 micron system and dielectric medium collapse test etc., calculate the parameter of different processing procedures and the relation of finished product, and then just calculate parameter and finished product relation in developing 0.15 and 0.13 micron system and 0.18 micron system.
Certainly, in order to integrate mutually with other technology and other computer software, present embodiment can allow the data format of implanted reliability analysis system compatible with other common DAS, for example Excel, JMP, MATLAB and SAS.
In addition, in order to allow any user can obtain any previous foundation and these machines, these wafers message relevant with these reliability analysis programs, present embodiment also provides search assembly and inquiry assembly, provides the user from the database active searching and obtain the pipeline of required message.Certainly, search the artificial intelligence of Search engine that assembly uses, preferably have the function of study, can be according to the keyword use of all previous inquiry and the relation of final Query Result, revise and search the rule of using, and set up different users's individualized search rule.
In addition, diagram and form that present embodiment can also use the implanted reliability analysis system to be produced, for example pictorial statement (Graphical report) and daily work report, weekly, initiatively provide product design personnel and research staff in product reality before production line is produced, just can consider the reference message of reliability factor, for example the relation of the reliability of the relation of the reliability of different parameters value and final products, different parameters value and complete processing procedure, present measurement result and the relation of estimating reliability.Certainly, in the output of this diagram with form, it can be output termly, it also can be the output that requires of answering product design personnel and research staff etc., and also can be when actual measured results surpasses a scheduled volume with the difference of estimating measurement result, test result report and failure analysis report are provided on one's own initiative at any time, instant reliability information is provided.
Further, because the implanted reliability analysis system can write down the details of any test program and the situation of any machine, present embodiment can also utilize the in-building type reliability analysis system to carry out the scheduling (job schedule) of these machines.Present embodiment can be according to registered job schedule, the test that the proactive notification operator will carry out; Can according to registered job schedule and the various test related data that stored (as consuming time what etc.), when judge has machine to have enough neutral gears to test; Can also provide the message relevant according to stored various test related data, remind the operator when this carries out those preparations with any test.The relation of these tests and machine also provides the important message of garbled data in the future.For example, when a mechanical disorder, the user can comply with this identification number, filters out the reliability test data by this machine output wafer, uses and understands the reliability issues that this fault may cause.
In addition, present embodiment can use this in-building type reliability analysis system that the fool proof function is provided.The data that stored by reference in-building type reliability analysis system, if the operating personnel of certain machine or certain step are when transferring the parameter of machine and reliability analysis program, the parameter value that sets has format error or with the standard value accepted of database obvious deviation is arranged, and just initiatively gives a warning.
Another preferred embodiment of the present invention is a kind of system that uses the in-building type reliability analysis in production of semiconductor products.As shown in Figure 3A, have at least: implanted reliability analysis assembly 31, crash handling assembly 32, the report assembly 33 that lost efficacy, scheduling assembly 34, Product Validation/monitoring/assessment (Product Qualification) report assembly 35, processing procedure checking/monitoring/assessment (Process Qualification) are reported assembly 36, wafer level reliability control/online processing procedure assessment/monitoring (Wafer Level reliability Control) assembly 37, report assembly 38 and are analyzed assembly 39.
In-building type reliability analysis assembly 31 exchanges most data with most machines, most product and most fabrication steps simultaneously, and uses known in-building type reliability analysis to handle these data and produce most relevent informations that operate.
Product Validation/assessment/monitoring report assembly 35 produces the most product quality messages relevant with these products by in-building type reliability analysis assembly 31 and these running relevent informations.Processing procedure checking/assessment/monitoring report assembly 36 produces and the relevant most processing procedure performance messages of these processing procedure checkings by in-building type reliability analysis assembly 31 and these running relevent informations.Wafer level reliability control/online processing procedure assessment/monitoring assembly 37 operates relevent information by in-building type reliability analysis assembly 31 and these, generation and these products, most reliability messages that these machines are relevant with these fabrication steps.
At this, because the major function of product/monitoring/assessment report assembly 35, processing procedure checking/monitoring/assessment report assembly 36 and wafer level reliability control/online processing procedure assessment/monitoring assembly 37 is to produce these product quality messages, these processing procedure performance messages, these reliability messages, therefore report that assembly 38 can only produce comprehensive report according to these messages, analyze assembly 39 and also can only carry out the aggregate data analysis according to these.
In the same manner, because scheduling assembly 24 has received all running relevent informations that in-building type reliability analysis assembly 21 is produced, shown in Fig. 3 B, present embodiment can allow Product Validation/monitoring/assessment report assembly 35 be connected with implanted reliability analysis assembly 31 by scheduling assembly 34; Can allow processing procedure/monitoring/assessment report assembly 36 be to be connected with implanted reliability analysis assembly 31 by scheduling assembly 34; Can allow wafer level reliability control/online processing procedure assessment/monitoring assembly 37 be connected with implanted reliability analysis assembly 31, also can allow analysis assembly 39 be connected with crash handling assembly 32 by the report assembly 33 that lost efficacy by scheduling assembly 34.Certainly, only a kind of possibility framework shown in Fig. 3 B, present embodiment does not limit implanted reliability analysis assembly 31 and must be simultaneously be connected by, processing procedure checking/monitoring/assessment report assembly 36 and wafer level reliability control/online processing procedure assessment/monitoring assembly 37 by scheduling assembly 34 and Product Validation/monitoring/assessment report assembly 35, but can individually receive by ordering assembly 34.
In addition, for the function of feedback is provided, shown in Fig. 3 C, implanted reliability analysis assembly 31 can receive comprehensive report, and the integration comprehensive report operates relevent information to these; Implanted reliability analysis assembly 31 also can receive the aggregate data analysis, and the analysis of integration aggregate data operates relevent information to these; And implanted reliability analysis assembly 31 also can receive the report of losing efficacy, and integration inefficacy report analysis operates relevent information to these.Certainly, only a kind of possibility framework shown in Fig. 3 C, present embodiment does not limit implanted reliability analysis assembly 31 must receive comprehensive report, running relevent information and the report of losing efficacy simultaneously, but can individually receive.
Moreover wafer level reliability control/online processing procedure assessment/monitoring assembly 37 can carry out the wafer level reliability analysis, and present embodiment does not limit these details.But in order to bring into play the performance of implanted reliability analysis, present embodiment be fit to be applied in can at-once monitor the wafer level reliability analysis.For instance, the wafer level reliability various reliability analysis programs that control/online processing procedure assessment/monitoring assembly 37 can carry out can be to be selected from following various test: hot carrier injects test, electron transfer test, breakdown voltage test.
Next, emphasize to use the influence of the present invention to the production of semiconductor products program for the sake of simplicity, Fig. 4 A to Fig. 4 D shows known semiconductor fabrication schedule and the basic procedure of using semiconductor fabrication process of the present invention respectively.
Shown in Fig. 4 A and Fig. 4 B, the known semiconductor fabrication schedule can be divided into four big step squares (research and development design procedure square 41, manufacturing step square 42, test square 43 and reliability analysis square 44) and two big relevent information squares (manufacturing step related data square 45 and output related data square 46) usually.
Research and development design procedure square 41 is meant all actions before formally producing, adjustment test of product specification exploitation for example to be manufactured a product, test to be manufactured a product and pending manufacturing step or the like.
Manufacturing step related data square 45 be meant everything in the manufacturing step square 42 carrying out, carry out these actions machine, carry out operating personnel of these actions or the like, all data that when carrying out manufacturing step square 42, produced.
Output related data square 46 be meant the test square 43 in everything carrying out, carry out these actions machine, carry out operating personnel of these actions or the like, testing all data that square 43 is produced.
Shown in Fig. 4 C and Fig. 4 D, use semiconductor fabrication process of the present invention except having three known big step squares (research and development design procedure square 41, manufacturing step square 42 and test square 43) and two big relevent information squares (manufacturing step related data square 45 and output related data square square 46), also additionally have reliability monitoring time square 48 and reliability control time square 49 on implanted reliability analysis square 47 and the line.At this, implanted reliability analysis square 47 has replaced the reliability analysis square 44 of known technology, and reliability monitoring time square 48 can be the wafer level reliability analysis at least on the line.
Implanted reliability analysis square 47 is in order to the square of execution implanted reliability analysis, compares with the reliability analysis square 44 of known technology, has following feature at least:
(1) implanted reliability analysis square 47 can receive manufacturing step related data square 45 and output related data square 46, and carries out the implanted reliability analysis according to these data.
(2) implanted reliability analysis square 47 can be respectively with manufacturing step square 42 and test square 43 the two carry out interactive systematically, for example exchanges data, the instant correction and instant status report or the like.
(3) implanted reliability analysis square 47 can will operate result transmission systematically to researching and developing design procedure square 41.By this, make the running of research and development design procedure square 41 can introduce the consideration of reliability.
(4) implanted reliability analysis square 47 can carry out following action at least: the assessment of processing procedure reliability, wafer level reliability analysis, production reliability assessment, data analysis, scheduling, form generation, failure analysis and failure analysis report.
At this, reliability is monitored time square 48 as the interface of implanted reliability analysis square 47 with manufacturing step square 42 on the line, and reliability control time square 49 is the interface as implanted reliability analysis square 47 and manufacturing step square 42.
Apparently, the pass in the known technology between the middle different step square (41/42/43/44) is an one-way road, carries out square earlier and can't predict the content of carrying out square subsequently, and the content of carrying out square subsequently can not be fed back to carries out square earlier.And the different messages square (45/46) of being correlated with is not separate, and can't be fed back to the relevant square (41/42/43/44) of each message.
Relatively, the present invention can allow the pass between the different step square (41/42/43/44) be back and forth two-way, carries out square earlier and can predict the content of carrying out square subsequently, and the content of carrying out square subsequently also can be fed back to carries out square earlier.And the different messages square (45/46) of being correlated with not only can be integrated mutually by implanted reliability analysis square 47, also can be fed back to the relevant square (41/42/43/44) of each message by implanted reliability analysis square 47.
At last, must be emphatically above-mentioned each present embodiment various may change, various may functions and various formation all be separate, unless special plaintext restriction is arranged in the above-mentioned explanation, can look actual needs when using each present embodiment and select needed variation, function and formation.
The above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the following claim.
Claims (28)
1. method of using the implanted reliability analysis system in production of semiconductor products comprises:
Preparing a plurality of machines and a plurality of wafer, be to be used at least one this wafer is carried out at least one reliability analysis program at this arbitrary this machine, and arbitrary this wafer is handled by this machine at least in regular turn;
Prepare an implanted reliability analysis system, this implanted reliability analysis system comprises a database, an assessment assembly, a baseline assembly, a control assembly and a development assembly, at least and searches assembly, an analysis assembly and an inquiry assembly;
With reference to this implanted reliability analysis system, adjust the parameter of those machines and those reliability analysis programs;
Use those machines that those wafers are carried out those reliability analysis programs, and writing down a plurality of information of arbitrary this reliability analysis program, arbitrary this machine and arbitrary this wafer simultaneously, those information comprise the measurement result of the running parameter of the operating parameters of arbitrary this reliability analysis program, arbitrary this machine, arbitrary this wafer, the problem of appearance and the mode of dealing with problems at least; And analyze and integrate those information to this implanted reliability analysis system, use the production reliability that obtains this semiconductor product and the processing procedure reliability of this semiconductor product manufacture process, and upgrade this implanted reliability analysis system.
2. application implanted reliability analysis system as claimed in claim 1 is characterized in that in the method for production of semiconductor products those reliability analysis programs belong to a wafer level reliability analysis.
3. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that it is one of following that arbitrary this reliability analysis program system is selected from: hot carrier injects test, the test of dielectric medium collapse time, the breakdown voltage test, the bias voltage temperature test, the electron transfer test, the ion mobility test, stress migration test, the electricity slurry causes to damage to be tested, hot carrier injects test, the breakdown voltage test, the constant temperature electron transfer, the high temperature service life test, the low temperature life test, the decreasing failure rate test, the accelerated ageing test, pre-condition test, the pressure cooker test, the constant temperature and humidity test, thermal shock test, the variations in temperature loop test, the high-temperature storage test, the low temperature stress test, the test of acceleration soft error rate, electrostatic discharge testing, the bolt-lock test, the test of system soft mistake rate.
4. application implanted reliability analysis system as claimed in claim 1 is characterized in that in the method for production of semiconductor products one side is carried out arbitrary this reliability analysis program, and one side is analyzed corresponding at least one information and integrate.
5. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that, this implanted reliability analysis system is for using the system of known implanted reliability analysis, and the big feature of one is not measure final products passively but most parameters of direct measurement and control final products manufacture process.
6. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that, this implanted reliability analysis system is for using the system of known implanted reliability analysis, the big feature of one is most data of a plurality of the flow processs of carrying out before and after in vertical integration one entire flow, uses to overcome in the known technology shortcoming that the indivedual QCs/reliability relevent information of homogeneous flow process not can't systematization be integrated.
7. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that, this implanted reliability analysis system is for using the system of known implanted reliability analysis, the big feature of one is a Horizontal Integration with most data of the most unit that carry out respectively simultaneously in the flow process, uses the shortcoming that the indivedual QCs/reliability relevent information that overcomes different units in the known technology can't systematization exchanges.
8. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that, one big feature of this implanted reliability analysis system is by continuing record and analyze a majority data that relatively come from a plurality of sources, uses the influence of the variation in the reliability in arbitrary this source of assessment and arbitrary this source to integral body.
9. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that, this implanted reliability analysis system system sets up the relation of reliability and other parameter by the method for data analysis, can applicable statistical method have shellfish formula theorem at least at this, control chart, factor analysis, analysis of variance, multi-variables analysis, discriminant analysis, principal component analysis, experimental design/reaction curved surface, regression analysis, decision tree, enlightening Klatt program, mixed integer programming, linear and Non-Linear Programming, queuing theory, random process, MRP etc., and other possible parameter has the processing procedure monitoring parameter at least, yield, specific wafer acceptance test parameter, machine parameter on the line, the wafer pin is surveyed parameter, final detected parameters, the reliability test parameter.
10. application implanted reliability analysis system as claimed in claim 9 is in the method for production of semiconductor products, it is characterized in that, this implanted reliability analysis system is by the reliability set up of statistics and the relation of other parameter, comprises the relation of the reliability of the parameter value of arbitrary this parameter and final products.
11. application implanted reliability analysis system as claimed in claim 9 is in the method for production of semiconductor products, it is characterized in that, this implanted reliability analysis system can also pass through statistical, the variation that concerns between reliability and some special parameter under the more different process technique provides the approach of calculating the reliability of new process technique from the reliability of existing process technique.
12. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that, the data format of this implanted reliability analysis system is compatible with other common DAS, for example Excel, JMP, MATLAB and SAS.
13. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that this database, this search assembly and this inquiry assembly are used for allowing arbitrary user can obtain any previous foundation and those machines, those wafers message relevant with those reliability analysis programs.
14. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that, the diagram and the form that also can use this implanted reliability analysis system to be produced provide product design personnel and research staff just can consider the reference message of reliability factor in product reality before production line is produced.
15. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that, the diagram and the form that also can use this implanted reliability analysis system to be produced, test result report and failure analysis report are provided at any time, instant reliability information is provided.
16. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that, still can use this implanted reliability analysis system to carry out the scheduling of those machines, this implanted reliability analysis system is except writing down the job schedule of all those machines; When the test that can the proactive notification operator will carry out and judging has machine to have outside enough neutral gears can test; The message relevant with any test still can be provided, be measured by those boards as those tests, so also can be when board has problem from these data tracings to the board that goes wrong relatively; Remind the operator when this carries out those preparations; When a plurality of testers apply for using same board in the same period, then return the proactive notification related personnel and hold consultation, to improve board utilization rate and manpower configuration optimization.
17. application implanted reliability analysis system as claimed in claim 1 is in the method for production of semiconductor products, it is characterized in that, also can use this implanted reliability analysis system that the fool proof function is provided, when operating personnel adjust the parameter of those machines and those reliability analysis programs, if the parameter value of setting has format error or with the normal range (NR) accepted of this data-base recording obvious deviation is arranged, just initiatively give a warning.
18. a system that uses the implanted reliability analysis in production of semiconductor products comprises:
One implanted reliability analysis assembly, should in use implanted reliability analysis assembly and exchange most data with most machines, most product and most fabrication steps simultaneously, and use known implanted reliability analysis to handle those data and produce most relevent informations that operate;
One crash handling assembly, this crash handling assembly receive that this implanted reliability analysis assembly transmitted with those machines, majority inefficacy message that those products are relevant with those fabrication steps, and analyze those messages;
One lost efficacy reports assembly, the majority inefficacy relevent information that this inefficacy report assembly is produced according to this crash handling assembly, producing lost efficacy with those machines, majority that those products are relevant with those fabrication steps reports that inefficacy report can be obtained fast by fuzzy query;
One scheduling assembly, this ordering assembly is according to those running relevent information arrangements
The workflow of those machines, those products and those fabrication steps, and the majority work relevent information relevant with the workflow that is ranked is provided; Can track the historical data of dependence test board as scheduling assembly when the data exception, understanding the accuracy and the accuracy of board, and then from these data tracings to the board that goes wrong relatively; Show which test each tester has done; In addition, when the scheduling assembly can the proactive notification tester be tested; And can show the current state and the utilance of each board, and apply for that if any a plurality of applicants the same period uses same board, can inform initiatively that then the related personnel is to hold consultation, so that various resource can reach optimum utilization;
One Product Validation/monitoring/assessment report assembly, this Product Validation/monitoring/assessment report assembly produces the most production reliability messages relevant with those Product Validation/monitoring/assessments by this implanted reliability analysis assembly and those running relevent informations;
One processing procedure checking/monitoring/assessment report assembly, this processing procedure checking/monitoring/assessment report assembly produces the most processing procedure performance messages relevant with those fabrication steps by this implanted reliability analysis assembly and those running relevent informations;
One wafer level reliability control/online processing procedure assessment/monitoring assembly, this wafer level reliability control/online processing procedure assessment/monitoring assembly is by this implanted reliability analysis assembly and those running relevent informations, directly on production line, monitor, produce and those Product Validations, most reliability messages that those machines are relevant with those fabrication steps;
One report assembly 38 is Product Validation/monitoring/assessment report assembly 35, processing procedure checking/monitoring/assessment report assembly 36 and wafer level reliability control/online processing procedure assessment/monitoring assembly 37 related datas according to input automatically, generation and these machines, these Product Validations and the relevant comprehensive report of these processing procedures checking; Report assembly system is the input initial data automatically, its way is to generate keyword automatically, scout the stationary storage district automatically whether new test data is arranged, if any new test data, then data are keyed in database automatically, to deduct mistake that artificial input caused, to reduce tester's burden; In addition, required comprehensive report and relevant documentation can be inquired about and be found fast to the keyword that the utilization of report assembly generates automatically;
One analyzes assembly, this analyzes assembly according to this product report checking/monitoring/assessment/assembly, this wafer level reliability control/online processing procedure assessment/monitoring/assembly of this processing procedure checking/monitoring/assessment report assembly, and the generation of failure analysis assembly and those machines, an aggregate data analysis that those products are relevant with those fabrication steps.
19. application implanted reliability analysis as claimed in claim 18 is characterized in that in the system of production of semiconductor products this report assembly system follows according to those product quality messages, those processing procedure performance messages and those reliability messages and produces this comprehensive report.
20. application implanted reliability analysis as claimed in claim 18 is in the system of production of semiconductor products, it is characterized in that this analysis assembly carries out this aggregate data analysis according to those product quality messages, those processing procedure performance messages and those reliability messages.
21. application implanted reliability analysis as claimed in claim 18 is characterized in that in the system of production of semiconductor products this implanted reliability analysis assembly also can receive this comprehensive report, and integrates this comprehensive report and operate relevent information to those.
22. application implanted reliability analysis as claimed in claim 18 is in the system of production of semiconductor products, it is characterized in that, this implanted reliability analysis assembly also can receive this aggregate data analysis, and integrates this aggregate data and analyze to those running relevent informations.
23. application implanted reliability analysis as claimed in claim 18 is characterized in that in the system of production of semiconductor products this implanted reliability analysis assembly also can receive this inefficacy report, and integrates this inefficacy report to those running relevent informations
24. application implanted reliability analysis as claimed in claim 18 is characterized in that in the system of production of semiconductor products this product report assembly is to be connected with this implanted reliability analysis assembly by this scheduling assembly.
25. application implanted reliability analysis as claimed in claim 18 is characterized in that in the system of production of semiconductor products this processing procedure report assembly system is connected with this implanted reliability analysis assembly by this scheduling assembly.
26. application implanted reliability analysis as claimed in claim 18 is characterized in that in the system of production of semiconductor products it is to be connected with this implanted reliability analysis assembly by this scheduling assembly that this reliability is measured assembly.
27. application implanted reliability analysis as claimed in claim 18 is characterized in that in the system of production of semiconductor products this reliability is measured assembly can carry out a wafer level reliability analysis or an encapsulation level reliability analysis.
28. application implanted reliability analysis as claimed in claim 18 is in the system of production of semiconductor products, it is characterized in that it is one of following that at least one reliability analysis program system that this reliability measures that assembly carried out is selected from: hot carrier injects to be tested, the test of dielectric medium collapse time, the breakdown voltage test, the bias voltage temperature test, the electron transfer test, the ion mobility test, stress migration test, the electricity slurry causes to damage to be tested, hot carrier injects test, the breakdown voltage test, the constant temperature electron transfer, the high temperature service life test, the low temperature life test, the decreasing failure rate test, the accelerated ageing test, pre-condition test, the pressure cooker test, the constant temperature and humidity test, thermal shock test, the variations in temperature loop test, the high-temperature storage test, the low temperature stress test, the test of acceleration soft error rate, electrostatic discharge testing, the bolt-lock test, the test of system soft mistake rate.
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| CN 02136848 CN1249799C (en) | 2002-09-06 | 2002-09-06 | Embeded reliability analysis system applied to production of semiconductor products |
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| CN 02136848 CN1249799C (en) | 2002-09-06 | 2002-09-06 | Embeded reliability analysis system applied to production of semiconductor products |
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| CN100394421C (en) * | 2004-12-13 | 2008-06-11 | 台湾积体电路制造股份有限公司 | System and method of analyse product good rate |
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| CN103678529A (en) * | 2013-11-29 | 2014-03-26 | 上海华力微电子有限公司 | Integration method of wafer test data of multiple times |
| CN103678529B (en) * | 2013-11-29 | 2017-01-18 | 上海华力微电子有限公司 | Integration method of wafer test data of multiple times |
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