TW574743B - Building-in-reliability diagnosis system for semiconductor manufacturing - Google Patents
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574743 號 91120000 月 曰 修正 五、發明說明(1) 【發明領域】 本發明係有關於應用枯x ^ (buUdln…eliabUlfv入式可靠度分析系統 於半導體產品生產,特别//iagn〇Sis SyStem,BIRDS) 曰in ®你r f ! ί〜疋應用植入式可靠度分析系統於 日日圓層級(wafer- level) 1 J之可靠度分析。 【發明背景】 習知技術 個別晶粒封裝 與品管測試。 reliability, 分析已廣泛地 試所得資料與 但是封裝 關的測試步驟 半導體產品的 的使用便面對 度分析來確定 機,若不作完 爭取時效,又 同時,隨 分析所需要進 樣品的數目都 、個別機台與 中,大多是在晶圓 完成後,彳進行的 一般稱此為封骏層 pLR)之測試分析g 被使用’不只相關 分析所得結果也已 層級可靠度分析有 相當的花時間,動 商品生命期快速縮 兩難的困境:若耗 某產品的可靠度, 整的封裝層級可靠 不能確定此產品之 著半導體產品的曰 行的步驟、所需要 大幅增加。由於習 個別樣品都有專人 完工、晶粒(c h i ρ)切割與 半導體元件的可靠度分析 級可靠度(package-level 5而由於封裝層級可靠度 的技術與產品已成熟,測 有足夠的公信力。 一個無法避免的缺失:相 輒數月之久。因此,隨著 短,封裝層級可靠度分析 時數月進行封裝層級可靠 此產品往往已錯失市場時 度分析便讓某產品上市以 可靠度。 益複雜,封裝層級可靠度 使用的機台與所需要測試 知技術中,雖然個別步驟 負責,將此步驟/機台/樣No. 574743 No. 91120000 Revised January 5, Description of the Invention (1) [Field of the Invention] The present invention relates to the application of the dry reliability analysis system for semiconductor products, especially // iagn〇Sis SyStem, BIRDS ) Said in ® you rf! 疋 ~ 疋 Reliability analysis using an implanted reliability analysis system at a wafer-level 1 J. [Background of the Invention] Conventional Technology Individual die packaging and quality control testing. Reliability, analysis of the data obtained from extensive testing and test steps related to packaging, the use of semiconductor products will be determined by the degree of analysis, if not done to obtain timeliness, and at the same time, with the number of samples required for analysis, the individual Most of the machines and equipment are tested and analyzed after the wafer is completed, which is generally called the pjun layer. It is not only related to the analysis results, but also has a level of reliability analysis. The dilemma of the rapid contraction of the product life cycle: if the reliability of a certain product is consumed, the entire package level cannot be determined, and the steps required for the production of this product's semiconductor product will increase significantly. Because individual samples have been completed by individual engineers, chip (chi ρ) cutting, and semiconductor component reliability analysis level reliability (package-level 5), and because the packaging level reliability technology and products have matured, the test has sufficient credibility. An unavoidable deficiency: months long. Therefore, with the short, package-level reliability analysis takes months to perform package-level reliability. This product often misses the market-time analysis and allows a product to go to market with reliability. Complex, package-level reliability is used in the machine and required testing know-how, although individual steps are responsible, this step / machine / sample
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案號 91120000 五 、發明說明(2) 品的品管與可靠度極佳化,但並沒有統合 機台/樣品)之品管與可靠度。因此,封 ^ 土 V驟/ 之可靠度往往不能極佳化(因為不同部 θ門度分析 柢消),而且不同個體也不能分享彼此的經二;;相互 針對封裝層級可靠度分析耗時過久、的缺 諸如德州“等公司已逐漸發展出測試速度 的圓 層級(wafer-level)可靠度分析。藉由在a 的日日0 程中或形成好後便進行可靠度測試,待= 阳粒製 ,c"通過驗證後才進行切割封裝的作 少可靠度測試所需要的時間。當然 巾;度減 與封裝層級可靠度分析二者的步驟有所不^』罪度刀析 f知之晶圓層級可靠度分柯的實際應用,仍會 故遇下列二個缺失:第―、習知晶圓層級可靠 法有效整合各步驟/機台,樣品的品管與可靠 : =將整體品管與可靠度最佳化;第某些晶圓層級; 罪度/刀析缺乏實驗數據與理論根據,來 可靠度分析是等效。 〃对装增、,及 ,综上所述,與半導體製程之品f與可靠度有關的習知 技術’都有尚待解決之不可忽略的缺失。 【發明目的及概述】 本發明一主要目的是提供可以有效整合各步驟/機台/ 樣品的良率與可靠度,進而將整體品管與可靠度最佳化的 方法Case No. 91120000 5. Description of the invention (2) The quality control and reliability of the product are optimized, but the quality control and reliability of the machine / sample are not integrated. As a result, the reliability of the seal V / cannot often be optimized (because the θ-gate analysis of different parts is eliminated), and different individuals cannot share each other's experience; each other's reliability analysis of the packaging level is time-consuming For a long time, companies such as Texas ’have gradually developed a round-level reliability analysis of test speed. By performing reliability tests during the day and day 0 of a or after they are formed, wait for = yang Granular, c " the time required for the reliability test of the cut and package before passing the verification package. Of course, the steps of the reduction and the reliability analysis of the packaging level are not the same. The practical application of the round-level reliability analysis will still encounter the following two shortcomings: No. 1, the conventional wafer-level reliability method effectively integrates each step / machine, and the quality and reliability of the sample: = the overall quality control and reliability Optimization; some wafer level; crime / scoring analysis lacks experimental data and theoretical basis, and reliability analysis is equivalent. 〃 For equipment increase, and, in summary, the same as the semiconductor process product f Related to reliability "The conventional technology" has unresolved shortcomings that remain to be solved. [Objective and Summary of the Invention] One of the main objectives of the present invention is to provide the yield and reliability of various steps / machines / samples that can be effectively integrated, and then the overall quality control And reliability optimization methods
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土 ^發明另一主要目的是提供數據可以證明晶圓層級可 罪度/刀析以及封裝層級可靠度分析二者是否等效與相對應 關係的方法。 本發明的基本特徵是應用近年才被提出的植入式可靠 度勿析丄來整合各個層級可靠度分析。特別是應用建立在 各種叮罪度分析測試資料的資料庫(database)與分析工具 ,來有效發揮各種層級之可靠度分析。由於植入式可靠度 分析系統是已知技術,在此將不多介紹,相關的細節至少 可參閱:W.K.T. Kary Chien & Charles H.J· Huang, Practical Building-In Reliability (BIR)The other main purpose of the invention is to provide data that can prove the equivalence and correspondence between the wafer-level guilty / knife analysis and the package-level reliability analysis. The basic feature of the present invention is to integrate the reliability analysis of each level by using the implantable reliability analysis that has only been proposed in recent years. In particular, the database and analysis tools built on various kinds of stinginess analysis test data are used to effectively exert the reliability analysis of various levels. Since the implantable reliability analysis system is a known technology, it will not be introduced here. The relevant details can be found at least: W.K.T. Kary Chien & Charles H.J. Huang, Practical Building-In Reliability (BIR)
Approaches for Semiconductor Manufacturing", IEEEApproaches for Semiconductor Manufacturing ", IEEE
Transactions on Reliability, vol· 51 ,no 3Transactions on Reliability, vol · 51, no 3
September 2 002. 本發明之應用,至少還可具有下列幾個特徵: (1 )利用BIRDS,可以掌握任何參數與最終結果的關係 ,不論這個參數是最終測量/最終產品的參數,或是中間 測虿/中間產品的參數。因此,藉由參考BIRDS,可以在產 品設計階段便有效評估各個細節與對最狄產 質的影響,而u等到產品形成後才進行^:=量-與 修正。 (2 )任何與可罪度有關的問題,都可以透過B I R回溯 既往資料,依照經驗並透過推理引擎而有效地找到根本原 因0 (3)由於BIRDS是一個整合性的系統,可以建立現有技September 2 002. The application of the present invention can also have at least the following features: (1) Using BIRDS, one can grasp the relationship between any parameter and the final result, whether this parameter is the parameter of the final measurement / final product or an intermediate measurement虿 / Intermediate product parameters. Therefore, by referring to BIRDS, each detail and its impact on the highest quality can be effectively evaluated at the product design stage, and u waits until the product is formed before ^: = quantity- and correction. (2) Any problem related to guilty can be traced back to the past through B I R, and the root cause can be effectively found through experience and the reasoning engine. 0 (3) Because BIRDS is an integrated system, existing technology can be established
574743 案號 91120000 曰 修正 五、發明說明(4) 術下包含所有與可靠度有關項目的資料庫。對新技術開發 、製程最佳化、製程監控、可靠度監控與良率改善,; 以提供重要的參考依據。 ° 【發明詳細 首先, 徵:只有在 的測量並獲 沒有分享彼 這些常被忽 零散地存在 相對地 徵:將所有 使用習知之 等方式,獲 與各步驟1 2 與各機器1 1 調整;可以 量數據與資 更可以整合 品或整條生 根據上 用植入式可 一圖所示, 說明】 第一 A圖與第一B圖顯示習 各機器1 1與各步驟1 2分別 得相關資訊1 3,但不同機 此的資訊1 3,而且不同機 略’但這些資料並無有目μ,丨土 μ饭?己錄,只是 不同的系統。 ’第一 C圖與第一D圖顯示本發明的一大基本特 知技術的一大基本特 進行可靠度(或品管) 器11與不同步驟12並 台間也有交互作用, 的性的被記錄 個別的 植入式 得整體 的進行 運作前 在各步 料庫1 4 各機器 產線之 述之基 靠度分 至少包 資訊1 3 可靠度 的可靠 。如此 ,便考 驟12與 的對比 11與各 最佳化 本概念 析系統 含下列 即時地整合 分析1 5,配 度分析結果 作,本發明 量可能影響 各機器11運 預判結果的 步驟1 2個別 可靠度。 成一個 合電腦 ’並回 不只可 可靠度 行中, 可靠度 調整, 資料庫1 4,並 化工具與統計 饋至各機器1 1 以在各步驟1 2 的因素而進行 便即時根據測 與進行修正; 以追求最終產 ,本發明一較佳實施例為一種應 於半導體產 基本步驟 品生產的方法。如第574743 Case No. 91120000 Revision V. Description of the invention (4) A database containing all the items related to reliability under the operation. Provide important reference for new technology development, process optimization, process monitoring, reliability monitoring and yield improvement. ° [Details of the invention First of all, the sign: only the measurement and no share of these are often scattered relative to the ground sign: the use of all known methods, etc., with each step 1 2 and each machine 1 1 adjustment; can The quantity data and resources can be integrated or the whole product can be shown in the figure according to the implanted type used above. Explanation] The first A and B diagrams show the relevant information for each machine 11 and step 12 respectively. 1 3, but this information is different for different machines 1 3, and different machines are slightly different, but these data have no purpose μ, 丨 soil μ rice? Recorded, just different systems. 'The first C diagram and the first D diagram show a basic basic reliability of a basic knowing technology of the present invention (or quality control). There is also an interaction between the machine 11 and the different steps 12 and the sexual performance. Before recording the overall operation of the individual implants, the basic reliability points of each production line in each step warehouse 1 4 include at least information 1 3 reliability and reliability. In this way, we will examine the comparison between step 12 and 11 and each optimization. The concept analysis system includes the following real-time integrated analysis 1 5 and the analysis of the distribution results. The amount of the invention may affect the pre-judgment results of each machine 11 2 Individual reliability. "Complete a computer" and not only the reliability, the reliability adjustment, the database 14, and the combined tools and statistics are fed to each machine 1 1 to carry out the factors in each step 1 2 according to the test and the real-time Amendment; In order to pursue the final production, a preferred embodiment of the present invention is a method that should be applied to the basic steps of semiconductor production. Such as
第9頁 2003.10.30.009 574743 ___案號 91120000 _ 五、發明說明(5) 如第一背景方塊21所示, 圓。在此任一機器是用來對至 分析程序,而任一晶圓至少被 如第二背景方塊22所示, 統。此植入式可靠度分析系統 、評估總成(Ass es smen t as se a s s e m b 1 y )、控制總成(C ο n t r o (Development assembly)、搜 ’查詢總成(Query assembly) assembly ) ° 如調整方塊2 3所示,參考 整這些機器與這些可靠度分析 如可靠度測量方塊24所示 進行這些可靠度分析程序,並 序、任一機器與任一晶圓之多 除了至少包含任一可靠度分析 之工作參數以及任一晶圓之測 析程序所發現或發生的問題, 如回饋方塊25所示,分析 罪度分析系統,藉以獲得半導 體產品製造過程之製程可靠度 糸統。 在此,必須強調的是本實 度分析程序的細節,本實施例 月 曰____ 準備多數個機器與多數個晶 少一晶圓進行至少一可靠度 一機器所處理。 準備一植入式可靠度分析系 至少包含資料庫(Database) m b 1 y )、基線總成(B a s e 1 i n e 1 assembly)與發展總成 尋總成(Search assembly) ’與分析總成(A n a 1 y s i s 植入式可靠度分析系統,調 程序的參數。 ,使用這些機器對這些晶圓 同時§己錄任一可靠度分析程 數個資訊。在此,這些資訊 程序之運作參數、任一機器 量結果,更包含了可靠度分 以及解決問題的方式。 並整合這些資訊至植入式可 體產品之產品可靠度與半導 ,並更新植入式可靠度分析 施例並沒有限定所使用可靠 可以應用在傳統之封裝層級Page 9 2003.10.30.009 574743 ___Case No. 91120000 _ V. Description of the invention (5) As shown in the first background square 21, the circle. Any machine is used here for the alignment analysis process, and any wafer is at least as shown in the second background box 22, system. This implantable reliability analysis system, evaluation assembly (Ass es smen t as se assemb 1 y), control assembly (C ο ntro (Development assembly), search 'Query assembly (Assembly) assembly) ° If adjusted As shown in block 23, refer to these machines and these reliability analyses as shown in the reliability measurement box 24. Perform these reliability analysis procedures in sequence, including any machine and any wafer except for at least any reliability. Analyze the working parameters of the analysis and any problems found or occurred in the analysis process of any wafer. As shown in the feedback box 25, analyze the crime degree analysis system to obtain the process reliability system of the semiconductor product manufacturing process. Here, it must be emphasized that the details of the actual analysis procedure are as follows. In this embodiment, ____ prepare a plurality of machines and a large number of wafers for at least one reliability and one machine for processing. Prepare an implantable reliability analysis system including at least a database (Database mb 1 y), a baseline assembly (Base 1 ine 1 assembly), and a development assembly Search assembly (Search assembly) and an analysis assembly (A na 1 ysis implantable reliability analysis system, adjust the parameters of the program. Use these machines to record any number of reliability analysis procedures for these wafers at the same time. Here, the operating parameters of these information programs, any The results of the machine measurement also include the reliability score and the way to solve the problem. This information is integrated into the product reliability and semiconductivity of the implantable body product, and the implantable reliability analysis examples are not limited to use. Reliable can be applied to traditional packaging levels
第10頁 2003.10.30. 010 574743 _________案號91120000_年月日 修正_ 五、發明說明(6) 可靠度分析程序或是新進產品之晶圓層級可靠度分析程序 。本實施例所使用之可靠度分析程序至少可以是下列之一 (但不限於此):製程驗證(process Qualificati〇n)相關 程序、產品驗證(Product Qualification)相關程序、 製程評估(Process Eva 1 uat ion)相關程序、產品評估 (Product Evaluation)相關程序、製程監測(pr〇cess Moni t〇r )相關程序、定期產品監測(R〇utine Pr〇duct Monitor )相關程序、在線製程評估與監測(In-Line Process Evaluation & Monitor)相關程序 ° 製程驗證(Process Qua 1 i f i cat ion)及監測(Moni tor) 相關程序至少可以是下列之一(但不限於此):熱載子注入 測試(Η 〇 t C a r r i er Injection Test)、介電質崩潰時間測 試(Time Dependent Dielectric Breakdown Test)、崩潰 電壓測試(Voltage Ramp Test)、偏壓溫度測試(Bias Temperature Test)、電子遷移測試(Electromigration test)、離子移動率測試(I〇n Mobile Test)、應力遷移 測試(Stress Migration Test)、電漿引發損壞測試 (Plasma Induced Damage Test) 〇 晶圓層級可靠度控制(Wafer-Level-Reliability Control )及監測(Mon it or)與在線製程評估與監測(In-Line Process Evaluation & Monitor )相關程序至少可 以是下列之一(但不限於此):熱載子注入測試(Ho tPage 10 2003.10.30. 010 574743 _________ Case No. 91120000_ year month day amendment _ V. Description of the invention (6) Reliability analysis program or wafer-level reliability analysis program for new products. The reliability analysis program used in this embodiment may be at least one of the following (but not limited to this): process qualification related procedures, product qualification related procedures, process evaluation (Process Eva 1 uat) ion) related procedures, product evaluation (Product Evaluation) related procedures, process monitoring (Prcess Moni t0r) related procedures, periodic product monitoring (Routine PrOduct Monitor) related procedures, online process evaluation and monitoring (In -Line Process Evaluation & Monitor) related procedures ° Process Qua 1 ifi cat ion and monitoring (Moni tor) related procedures can be at least one of the following (but not limited to): hot carrier injection test (Η 〇 〇 t C arri er Injection Test), Time Dependent Dielectric Breakdown Test, Voltage Ramp Test, Bias Temperature Test, Electromigration test, Ion Ion Mobile Test, Stress Migration Test Plasma Induced Damage Test (Wafer-Level-Reliability Control) and monitoring (Mon it or) are related to In-Line Process Evaluation & Monitor The program can be at least one of the following (but not limited to this): Hot Carrier Injection Test (Ho t
Carrier Injection Test)、崩潰電壓測試(Voltage Ramp Test)、恒溫電子遷移(IsothermalCarrier Injection Test), Voltage Ramp Test, Isothermal
第11頁 2003.10.30.011 574743 __案號91120000_年月曰 修正__ 五、發明說明(7)Page 11 2003.10.30.011 574743 __Case No. 91120000_ Year Month Amendment __ V. Description of the invention (7)
Electromigration Test ) ° 產品驗證相關程序至少可以是下列之一(但不限於此) :高溫壽命測試(High Temperature Operating Life Test)、低溫壽命測試(Low Temperature Operating Life Test)、早期失效率測試(Early Failure RateElectromigration Test) ° The procedures related to product verification can be at least one of the following (but not limited to this): High Temperature Operating Life Test, Low Temperature Operating Life Test, Early Failure Rate Test (Early Failure Rate
Test)、加速老化測試(Highly Accelerated Stress Test )、預條件測試(Pre-condi tioning Test)、壓力鋼 測試(Pressure Cooker Test)、恒溫恒濕測試 (Temperature & Humidity With Bias Test)、熱衝擊 測試(Thermal Shock Test)、溫度變化循環測試 (Temperature Cycling Test)、高溫儲存測試(High Temperature Storage Test)、低溫應力測試(L〇w Temperature Stress Test)、加速軟錯誤率測試 (Accelerated Soft Error Rate Test )、靜電放電測試 (Electrostatic Discharge Test)、栓鎖測試(Latch UP Test)、系統軟錯誤率測試(System s〇ft Err〇r Rate Test) ° 另外,由於本實施例所引用的植入式可靠度分析,是 時(in_time)反應的方式。在可靠度測量 =巧訊進行分析與整合。進一步地…:统封 程序往往不能一面進行生產-面測量, 產一面測…此本實施例特別適用於晶圓層級可靠度iTest), Highly Accelerated Stress Test, Pre-conditioning Test, Pressure Cooker Test, Temperature & Humidity With Bias Test, Thermal Shock Test (Thermal Shock Test), Temperature Cycling Test, High Temperature Storage Test, Low Temperature Stress Test, Accelerated Soft Error Rate Test , Electrostatic Discharge Test, Latch UP Test, System Soft Error Rate Test (System s〇ft Err〇r Rate Test) ° In addition, due to the implantable reliability cited in this embodiment Analysis is the way of in (time) response. Analysis and integration in reliability measurement = Qiaoxun. Further ...: Unification procedures often fail to perform production-side measurement, production-side measurement ... This embodiment is particularly suitable for wafer level reliability i
第12頁 2003.10.30.012 574743 __塞號91120000 年 月 日 你不_ 五、發明說明(8) 析。 在此’由於植入式可靠度分析是近年新被提出的概念 ’已异疋習知技術的概念而只是幾乎未曾被具體應用,在 此,將不針對植入式可靠度分析的細節進行解釋,只是摘 要描述本實施例所使用建立在植入式可靠度分析之可靠度 分析系統的一些主要特徵如下: (1)不被動地測量最終產品,而是直接測量與控制最 終產品製造過程之多數參數。例如各機器之工作參數,或 是各步驟之流程參數,以預知產品可靠度。 (2 )垂直整合完整流程(f 1 ow )中前後進行之多數個次 流程(sub-flOW)(或說多數個步驟)的多數資料,藉以克服 習知技術中不同次流程之個別品管/可靠度相關訊息無法 系統化交流的缺點。 (3) 水平整合同一次流程中同時分別進行之多數單元 (如多數機器)的多數資料,藉以克服習知技術中不同單元 之個別品管/可靠度相關訊息無法系統化交流的缺點。 (4) 藉由持續記錄與分析比較來自於多數個來源之多 數筆資料,來評估任一來源的可靠度以及任一來源的變化 對整體的影響。 (5 )透過資料分析的方法建立可靠度與其它參數的關 係。在此可能應用的資料分析至少有貝式定理(Bayes i an Approach )、管制圖(Statistica 1 Contro1 Chart ) 、因素分析(Factor Analysis)、變異數分析 (Analysis of Variances)、多變量分析Page 12 2003.10.30.012 574743 __Serial No. 91120000 Month, day, you don't_ V. Explanation of invention (8). Here, 'as implantable reliability analysis is a newly proposed concept in recent years', it is different from the concept of known technology, but has not been applied in detail. Here, the details of implantable reliability analysis will not be explained. It simply summarizes some of the main features of the reliability analysis system based on implantable reliability analysis used in this embodiment: (1) Instead of passively measuring the final product, it directly measures and controls the majority of the final product manufacturing process. parameter. For example, the working parameters of each machine or the process parameters of each step to predict the reliability of the product. (2) The vertical integration of the majority of the sub-flOW (or most steps) in the complete process (f 1 ow), to overcome the individual quality control of different sub-processes in the conventional technology / Disadvantage of the failure to systematically communicate reliability-related information. (3) Horizontally integrate most of the data of most units (such as most machines) in the same process at the same time, in order to overcome the shortcomings of individual quality control / reliability related information of different units in the conventional technology that cannot be systematically communicated. (4) Evaluate the reliability of any source and the overall impact of changes from any source by continuously recording and analyzing multiple pieces of data from multiple sources. (5) Establish the relationship between reliability and other parameters through data analysis. The data analysis that may be applied here includes at least Bayes theorem, Statistica 1 Contro1 Chart, Factor Analysis, Analysis of Variances, and Multivariate Analysis
第13頁 2003. 10.30.013 574743 _案號91120000_年月曰 修正_ 五、發明說明(9) (Multivariate Analysis)、判別分析(Discriminant Analysis)、主成份分析(Principal component analysis)、實驗設計/反應曲面(Designs of Exper i ments/Response Surface Method )、迴歸分析 (Regression Analysis)、決策樹(Decision Tree) 、迪克萊特程序(Dirichlet Process)、混合整數規劃 (Mixed Integer Programming)、線形及非線性規劃 (Linear/Non - linear Programming)、等候理論 (Queuing Theory)、隨機過程(StochasticPage 13 2003. 10.30.013 574743 _ Case No. 91120000 _ year month and month amendment_ V. Description of the invention (9) (Multivariate Analysis), Discriminant Analysis, Principal component analysis, Experimental design / Designs of Experments / Response Surface Method, Regression Analysis, Decision Tree, Dirichlet Process, Mixed Integer Programming, Linear and Nonlinear Programming (Linear / Non-linear Programming), waiting theory (Queuing Theory), stochastic process (Stochastic
Process)、資源規劃(Resources pianning),而可能 的其它參數至少有製程監控參數、良率、特定之晶圓接受 度測試(Wafer Acceptance Test)參數、線上機器參數、 晶圓針測(Chip Probing)參數、最終檢測(Final Test)參 數、可靠度測試參數。 (6 )透過資料分析所建立之可靠度與其它參數的關係 ,包含任一該參數之參數值與最終產品之可靠度的關係。 因此,可以在製程進行中發現此參數值異常時,便能預測 最終產品之可能缺失與可靠度,進而據以進行修改。 (7)透過資料分析方式,比較不同製程技術下可靠度 與某些特定參數間關係的變化,提供從已有製程技術之可 靠Π新製程技術之可靠度的途徑。例如根據已成熟之 0.30 ’025,0.20微米製程與〇.18微米製程的電子遷移測 試與介電質崩潰測試等的測試資料,推算不同製程之參數 與成品的關係,進而推算正為路屁^ π 开止在發展中之〇· 15及〇· 13微米製Process), Resources pianning, and other possible parameters include at least process monitoring parameters, yield, specific wafer acceptance test parameters, online machine parameters, and chip probing Parameters, final test parameters, reliability test parameters. (6) The relationship between the reliability and other parameters established through data analysis, including the relationship between the parameter value of any of these parameters and the reliability of the final product. Therefore, when this parameter value is found abnormal during the process, it is possible to predict the possible lack and reliability of the final product, and then modify it accordingly. (7) Through data analysis methods, compare the changes in the relationship between the reliability under different process technologies and certain specific parameters, and provide a way to rely on the reliability of existing process technologies and the reliability of new process technologies. For example, based on the test data of the mature 0.30'025, 0.20 micron process and 0.018 micron process, such as electron migration test and dielectric breakdown test, the relationship between the parameters of different processes and the finished product is estimated, and then it is estimated that the road is fart ^ π start and stop in the development of 0.15 and 0.13 micron
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程與ο. 當 施例可 資料分 除 立與這 息,本 自資料 成所使 可以根 係,修 尋規則 18微米 然,為 以讓植 析軟體 此之外 些機器 貫施例 庫主動 用搜尋 據歷次 改搜尋 製程的 了與其 入式可 相容,,為了 、這些 還提供 搜索並 引擎的 查詢的 使用的 參數與成品 它技術及其 靠度分析系 例如E X c e 1 讓任何使用 晶圓與這些 了搜尋總成 獲得所需訊 人工智慧, 關鍵字使用 規則,並建 關係。 它電腦軟體相 統之資料格式 、JMP、MATLAB 者都可以獲得 可靠度分析程 與查詢總成, 息的管道。當 最好是具有學 過程與最終查 立不同使用者 整合,本實 與其它常見 與SAS。 任何先前建 序有關的訊 提供使用者 然,搜尋總 習的功能, 詢結果的關 的個人化搜 另外,本實施 產生之圖示 工作日報、 品實際在生 考訊息,例 同參數值與 估可靠度的 心期地產出 求產出,而 另J 過—預 分析報告, 進一步 與報表 周報, 產線進 如不同 完整製 關係。 ’也可 也可以 定量時 提供即 地,由 例還可以使用植入式可靠度 ’例如圖形報表(Graphical 主動提供產品設計人員與研 行生產前,就可以考量可靠 參數值與最終產品之可靠度 程之可靠度的關係、目前測 當然’在此圖示與報表的產 以是應產品設計人員與研發 是在實際測量結果與預計測 ’主動地隨時提供測試結果 時之可靠度資訊。 於植入式可靠度分析系統可 分析系統所 report) Μ 發人員在產 度因素的參 的關係、不 量結果與預 出,可以是 人員等的要 量結果的差 報告與失效 以記錄任何Cheng and ο. When the examples can separate and separate the data, the original data can be used to root the system, and the rule is 18 microns. In order to allow the plant analysis software to actively use the example library, Searching according to previous changes in the search process is compatible with its introspection. In order to provide the search parameters and search engine query parameters and finished products, other technologies and reliability analysis systems such as EX ce 1 allow any use of wafers and These search assemblies get the artificial intelligence you need, keyword usage rules, and relationships. Its computer software has a common data format, JMP, and MATLAB. People can obtain the reliability analysis process and query assembly and information channels. When it is best to have the learning process integrated with the final search for different users, this is actually common with other SAS. Any previous information related to the sequence provides the user with the function of searching the general practice, and the search of the results related to the personalized search. In addition, the implementation of the workday report, the actual product test information, such as parameter values and estimates Reliability is required to produce output at the desired time, and the other is to pass the pre-analysis report, which is further related to the report weekly, and the production line enters a different complete system. 'It can also be provided immediately when quantified, and implantable reliability can also be used by example.' For example, graphic reports (Graphical actively provides product designers and R & D before production can consider the reliability parameter values and the reliability of the final product. The relationship between the reliability of the process and the current test, of course, the production of the graphics and reports here should be the reliability information when the product designer and the R & D are actively providing the test results at any time. The in-line reliability analysis system can analyze the reports reported by the system. The relationship between the personnel's productivity factors, the unquantified results, and the prediction, can be the difference report and failure of the required results of the personnel to record any
第15頁 2003.10.30.015 574743 月 曰 修正 案號 91120000 五、發明說明(11) :試程序的細節與任何機器-植入式可靠度分析系統進行這些機器二二:還可以利用 本實施例可以根據已登記之工作 ,士(工作進度)。 要進行的測試;可以根據已登記工;進产操作者將 種測試相關資料(如耗時多少箄) 又 已儲存之各 料,提供與任何測試有關的訊息,提 =相關資 那些準備。這些測試與機器的關提m气 料的重要訊息。例如,當一機器 器編號’筛選出由該機器產出晶圓以 以瞭解該故障可能導致的可靠度問題。又川试貝料,糟 除此之外,本實施例可使用該植入式可靠产 防呆功能。藉由參考植入式可靠度分析系ς已儲存之 貝料,如果某機裔或某步驟之操作人員在調機器盘可靠度 分析程序的參數時,所設定的參數值有格式錯誤或與資料 庫之可接受標準值有明顯偏差,便主動發出警告。 本發明之另一較佳實施例為一種應用植入式可靠度分 析於半導體產品生產的系統。如第三Α圖所示,至少具有 :植入式可靠度分析總成31、失效處理總成3 2、失效報告 總成33、排程總成34、產品驗證/監測/評估(Pr〇duct Qualification)報告總成35、製程驗證/監測/評估 (Process Qual i f i cat ion)報告總成36、晶圓層級可靠度 控制/在線製程評估/監測(Waf er Level rel iab i 1 i ty Control)總成37、報告總成38和分析總成39。Page 15 2003.10.30.015 574743 Month Amendment No. 91120000 V. Description of the Invention (11): Details of the test procedure and any machine-implantable reliability analysis system to perform these machines 22: This embodiment can also be used according to Registered job, taxi (work progress). Tests to be performed; can be based on registered workers; the production operator will provide test-related information (such as how long it takes) and stored materials, provide information related to any test, and provide relevant information for those preparations. These tests are important information related to the machine's gas. For example, when a machine number 'screens out wafers produced by the machine to understand the reliability issues that the failure may cause. In addition, the test shell material is bad, in addition to this, this embodiment can use the implantable reliable production foolproof function. By referring to the stored reliability of the implanted reliability analysis system, if the operator of a certain machine or a certain step adjusts the parameters of the reliability analysis program of the machine disk, the set parameter value has a format error or is related to the data. If there is a significant deviation in the acceptable standard value of the library, an active warning will be issued. Another preferred embodiment of the present invention is a system for applying implantable reliability analysis to the production of semiconductor products. As shown in Figure 3A, at least: implanted reliability analysis assembly 31, failure processing assembly 3 2, failure report assembly 33, scheduling assembly 34, product verification / monitoring / evaluation (Prduct Qualification) report assembly 35, process verification / monitoring / evaluation (Process Qual ifi cat ion) report assembly 36, wafer level reliability control / online process evaluation / monitoring (Wafer Level rel iab i 1 i ty Control) 30, report 38, and 39 analysis.
第16頁 2003.10.30.016 574743 索號 91120000 五、發明說明(12) 年 曰 曰 修正 植入式可靠度分析總成3 1同時與多數機器、多數產品 與多數製程步驟交換多數資料,並使用習知之植入式可靠 度分析處理這些資料而產生多數運作相關訊息。 失效處理總成3 2接收植入式可靠度分析總成3 1所傳輸 過來之與這些機器、這些產品驗證與這些製程驗證相關之 多數失效訊息,並分析這些訊息。失效報告總成33根據失 效處理總成3 2所產生的多數失效相關訊息,產生與這些機 器、這些產品驗證與這些製 排程總成3 4根據這些運 些產品與這些製程步驟的工 程相關之多數工作相關訊息 可以儘可能地最佳化。如當 相關測試機台的歷史資料, (Accuracy )與精確度(pre 蹤到相對出問題之機台;顯 此外’排程總成會主動通知 一機台的目前狀態及利用率 段使用同一機台,則會主動 使各種資源能達到最佳利用 產品驗證/評估/監測報 析總成3 1以及這些運作相關 多數產品品質訊息。製程驗 植入式可靠度分析總成3 1以 這些I程驗證相關之多數製 程驗證相關之多數失效報告。 作相關訊息安排這些機器、這 作流程,並提供與排定工作流 ,以使機台使用率及人力配置 資料異常時排程總成能追蹤到 以瞭解機台的準確度 cision),進而從這些資料追 示每個測試者做了哪些測試; 測試者何時測試;並會顯示每 ’如有多個申請者申請同一時 告知相關人員以進行協商,以 〇 告總成3 5透過植入式可靠度分 訊息,產生與這些產品相關之 證/評估/監測報告總成36透過 及這些運作相關訊息,產生與 程性能訊息。晶圓層級可靠度Page 16 2003.10.30.016 574743 Call No. 91120000 V. Description of the invention (12) The revised implantable reliability analysis assembly 3 1 At the same time, it exchanges most data with most machines, most products and most process steps, and uses the known Implantable reliability analysis processes this data to produce most operationally relevant information. Failure handling assembly 3 2 Receives implanted reliability analysis assembly 3 1 Most failure messages related to these machines, these product verifications, and these process verifications are transmitted and analyzed. Failure report assembly 33 Based on most failure-related messages generated by the failure treatment assembly 3 2, it is related to these machines, these product verifications, and these manufacturing schedule assemblies 3 4 According to these products, these processes are related to the engineering of these process steps. Most job-related messages can be optimized as much as possible. For example, when the historical data of the relevant test machine, (Accuracy) and accuracy (pre tracked to the relatively problematic machine; obviously, the 'schedule assembly will actively notify the current status and utilization of a machine using the same machine Taiwan, will actively make use of various resources to achieve the best use of product verification / assessment / monitoring analysis assembly 3 1 and quality information of most products related to these operations. Process inspection implanted reliability analysis assembly 3 1 Validation-related most processes Validation-related most failure reports. Provide relevant information to arrange these machines, this process, and provide and schedule workflows, so that the schedule assembly can be tracked when the machine utilization rate and manpower configuration data are abnormal. In order to understand the accuracy of the machine), and then use these materials to track which tests each tester has done; when the testers test; and to display the relevant personnel for negotiation if there are multiple applicants applying for the same time Report the assembly 3 to 5 through the implanted reliability sub-messages to generate the certification / evaluation / monitoring report assembly 36 related to these products and these operations. Message, produce and process performance information. Wafer level reliability
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2003.10.30.017 )/4743 案號 911200flf) 五、發明說明(13) 臼 一修正 控制/在線製程評估/監測 成31以及這些運作相關訊息成3產7 J 可靠度分析總 與這些製程步驟相關之多數 ;;、=二產品、迫些機益 報告總成38係根據自動於罪又°凡心。 佩目動輸入的產品 告總成35、製程驗證/監測/ i測/疔估報 可查痒伙连丨/ * ,台制< j/ °平估報告總成36以及晶圓層級 了罪度控制/在線製程評估/政:丨 i言此撒抑、、古此太〇人 皿測、、心成3 7相關資料,產生與 足二機為、XI二產口 口驗證鱼這此制 •鈕心仏;於& *认 ,、乂些製私驗證相關之綜合報告 ,報告總成係自動輸入原始眘祖 甘 _ 上 t 7始貝枓,其做法乃自動生成關鍵 # 、自動偵察固定儲存區是否有新的測試資料,如有新的 測試資料,則將資料自動鍵入資料庫,以減去人工輸入所 造成的錯誤、降低測試者之負擔;此外,報告總成利用自 動生成的關鍵詞,可查詢並快速找到所需的綜合報告及相 關文擋。 分析總成3 9至少根據產品/監測/評估報告總成3 5、製 裎/監測/評估報告總成3 6、晶圓層級可靠度控制/在線製 裎評估/監測總成3 7以及失效報告總成3 3產生與這些機器 、這些產品驗證與這些製程驗證相關之綜合性資料分析。 並可視需要進一步根據排程總成34及/或失效報告總成33 來產生與這些機器、這些產品驗證與這些製程驗證相關之 综合性資料分析。 在此,由於產品/監測/評估報告總成35、製程驗證/ 監測/評估報告總成36以及晶圓層級可靠度控制/在線製程 評估/監測總成3 7的主要功能是產生這些產品品質訊息、 這些製程性能訊息、這些可靠度訊息,因此報告總成3 8可2003.10.30.017) / 4743 Case No. 911200flf) V. Description of the invention (13) Modified control / online process evaluation / monitoring 31 and these operation related information 3 3 7 J reliability analysis is always related to most of these process steps ;, == Second product, forcing some opportunity report assembly 38 is based on autonomy and sinfulness. Pay attention to the input of the product to the assembly 35, process verification / monitoring / i measurement / evaluation report can be checked itch / /, Taiwanese &j; ° evaluation report assembly 36 and wafer level crime Degree Control / Online Process Evaluation / Politics: 丨 I say this slaying, ancient and this time 〇 person dish test, xincheng 37 7 related data, generate and verify the system • Button heart: In & recognition, some comprehensive reports related to private verification, the report assembly is automatically entered into the original Shen Zugan _ shang t 7 Shibei, the method is to automatically generate key #, automatic reconnaissance Whether there is new test data in the fixed storage area. If there is new test data, the data is automatically entered into the database to reduce errors caused by manual input and reduce the burden on testers. In addition, the report assembly uses automatically generated data. Keywords, you can query and quickly find the required comprehensive report and related documents. Analysis assembly 3 9 At least according to product / monitoring / evaluation report assembly 3 5. Manufacturing / monitoring / evaluation report assembly 3 6. Wafer level reliability control / online manufacturing evaluation / monitoring assembly 3 7 and failure report The assembly 3 3 generates comprehensive data analysis related to these machines, these product verifications and these process verifications. Based on the schedule assembly 34 and / or failure report assembly 33, as required, comprehensive data analysis related to these machines, these product verifications, and these process verifications can be generated. Here, because the product / monitoring / evaluation report assembly 35, process verification / monitoring / evaluation report assembly 36, and wafer-level reliability control / online process evaluation / monitoring assembly 3 7 are the main functions of generating product quality information , These process performance information, these reliability information, so the report assembly 3 8 can
第18頁 2003.10.30.018 574743Page 18 2003.10.30.018 574743
五、發明說明(14) 以僅根據這些訊息來產生綜合報告,分析總成3 g也 根據這些來進行綜合性資料分析。 Μκ 91120000 成21 ’由於排程總成24已接收植入式可靠度分析總 成所產生之所有運作相關訊息,如第三β圖所示,本與 ==產品驗證/監測/評估報告總成35透過排程二 34與植入式可靠度分析總成31連接;可以讓製程/ =總成36係透過排程總成34與植入式可靠度分析、】總: 魄=、类I 曰曰曰圓層級可靠度控制/在、線製程評估/監測 〜、k排程總成3 4與植入式可靠度分析總成31連接, 3 I =讓t析總成⑽透過失效報告總成33與失效處理總成 、。虽然,第三B圖所示僅為一種可能架構,本每> m:疋植入式可靠度分析總成31必須同時透過排程總 i 驗證/監測/評估報告總成35透過、製程驗證/ ;估/ ΐ ί告總成36以及晶圓層級可靠度控制/在線製程 7估/監測總成37進行連接,而是可以個別地 成3 4進行接收。 徘序〜 f外,為了提供回饋的功能,如第三C圖所示,植入 析總成31可以接收综合報告,並整合綜合報告 此=1 ΐ作相關訊息;植入式可靠度分析總成31也可以接 性資料分析,並整合綜合性資料分析至 關訊息;並拮入々可主— 一 -^ 生,波敕人 ^罪度分析總成31也可以接收失效報 ° 正_5失效報分析至這些運作相關訊息。當缺,第 ;c圖所示僅為一種可能架構,本實施例並不植入第 可罪度分析總成31必須同時接收綜合報告、運作相關^息V. Description of the invention (14) To generate a comprehensive report based on only these messages, the analysis assembly 3g also conducts comprehensive data analysis based on these. Μκ 91120000 成 21 'As the schedule assembly 24 has received all the operational-related information generated by the implantable reliability analysis assembly, as shown in the third β diagram, this and == product verification / monitoring / evaluation report assembly 35 is connected to the implantable reliability analysis assembly 31 through schedule two 34; the process / = assembly 36 can be connected to the implantable reliability analysis through schedule assembly 34, and the total is: = =, class I Round-level reliability control / in-line, process evaluation / monitoring ~, k schedule assembly 3 4 is connected to implantable reliability analysis assembly 31, 3 I = let t analysis assembly ⑽ pass failure report assembly 33 and failure handling assembly. Although the third diagram B shows only one possible architecture, the > m: 疋 implantable reliability analysis assembly 31 must pass the schedule verification i verification / monitoring / evaluation report assembly 35 through, process verification /; Assessment / 告 The assembly 36 and the wafer-level reliability control / online process 7 estimation / monitoring assembly 37 are connected, but can be received individually as 3 4. In order to provide feedback, as shown in the third figure C, the implant analysis assembly 31 can receive the comprehensive report, and integrate the comprehensive report. This = 1 makes relevant information; the implant reliability analysis total Cheng 31 can also access the data analysis, and integrate the comprehensive data to analyze the critical information; and get involved in the master — one-^, stubborn people ^ sin degree analysis assembly 31 can also receive failure reports ° positive _5 Failure report analysis to these operations related information. When it is absent, Figure c shows only one possible architecture. This embodiment does not embed the criminality analysis assembly 31. It must receive comprehensive reports and operation-related information at the same time.
第19頁 2003.10.30.019 574743Page 19 2003.10.30.019 574743
以及失效報告,而是可以個別地接收。 再者,晶圓層級可靠度控制/在線製程評估/龄 37可以進行晶圓層級可靠度分析,本實施例並不;制:此 細節。但為了發揮植入式可靠度分析的性能,本實施例較 適合應用在可以即時監測之晶圓層級可靠度分析。舉例來 說,晶圓層級可靠度控制/在線製程評估/監測總成”可以 進行的各種可靠度分析程序可以是選自下列各種測試:熱 載子/主入測试、電子遷移測試、崩潰電壓測試。 接下來,為了簡明地強調應用本發明對半導體產品生 產程序的影響,第四A圖至第圖分別顯示習知半導體製 造程序以及應用本發明之半導體製造程序的基本流程。 、如第四A圖與第―圖所示’習知半導體製造程序通常 可以分為四大步驟方塊(研發設計步驟方塊41、製造步驟 方塊42、測試方塊43以及可靠度分析方塊44)與二大相關 訊息方塊(製造步驟相關資料方塊45以及產出相關資料方 塊46)。 研發設計步驟方塊4 1係指正式進行生產之前的一切動 作,例如待製造產品的產品規格開發、待製造產品之測試 以及待進彳于之製造步驟的調整測試等等。 製造步驟方塊42係指正式進行待製造產品之生產的— 切動作,例如晶圓清潔(clean)、氧化(〇xidati〇n)、熱處 理(thermal treatment)、微影(ph〇t〇Hth〇graphy)、蝕 刻(etching)、摻雜(doping)、擴散(diffusi〇n)、金屬導 線形成(metalization)等等。As well as failure reports, they can be received individually. Furthermore, wafer-level reliability control / on-line process evaluation / age 37 can perform wafer-level reliability analysis, which is not in this embodiment; manufacturing: this detail. However, in order to make use of the performance of the implantable reliability analysis, this embodiment is more suitable for the wafer-level reliability analysis that can be monitored in real time. For example, various reliability analysis procedures that can be performed at the wafer level reliability control / on-line process evaluation / monitoring assembly can be selected from various tests: hot carrier / main entry test, electron migration test, breakdown voltage Test. Next, in order to succinctly emphasize the impact of the application of the present invention on the production process of semiconductor products, Figures 4A to 4 respectively show the basic flow of a conventional semiconductor manufacturing process and a semiconductor manufacturing process to which the present invention is applied. Figure A and Figure ―The conventional semiconductor manufacturing process can usually be divided into four major step blocks (R & D design step block 41, manufacturing step block 42, test block 43 and reliability analysis block 44) and two related information blocks (Manufacturing steps related data box 45 and output related data box 46). R & D design step box 41 refers to all actions before formal production, such as product specification development of the product to be manufactured, testing of the product to be manufactured, and to be carried out. The adjustment test of the manufacturing steps, etc. The manufacturing step block 42 refers to the formal production of the product to be manufactured. Production — cutting operations, such as wafer cleaning, oxidation, thermal treatment, photography, etching, doping , Diffusion, metallization, and so on.
修正 案號 91120000 五、發明說明(!6) 574743 測試方塊4 3係指在產品製造好後對產品之品質等的測 試動作,例如晶圓接受度測試(wafer accePtance test) 以及晶粒探針測試(c h i p p r o b i n g t e s t)。 可靠度分析方塊44係指對大批產品以及相關製造步驟 之V靠度分析’至少製程可罪度及產品可靠度這二部份的 玎靠度。 製造步驟相關資料方塊4 5係指製造步驟方塊4 2中所有 動作的進行、執行這些動作之機器、執行這些動作之操作 人員等等,在進行製造步驟方塊42時所產生的一切資料。 產出相關資料方塊4 6係指測試方塊43中所有動作的進 行、執行這些動作之機器、執行這些動作之操作人員等等 ,在進行測試方塊4 3所產生的一切資料。 如第四C圖與第四D圖所示,應用本發明之半導體製造 程序除了擁有習知之三大步驟方塊(研發設計步驟方塊4 i 、製造步驟方塊42以及測試方塊43)與二大相關訊息方塊 (製造步驟相關資料方塊4 5以及產出相關資料方塊4 6)外, 還額外擁有植入式可靠度分析方塊4 7以及線上可靠度監測 次方塊48以及可靠度控制次方塊49。在此,植入式度 分析方塊47取代了習知技術之可靠度分析方塊44,而線上 可靠度監測次方塊4 8至少可以是晶圓層級可靠度分析。 植入式可靠度分析方塊4 7係用以執行植入式可靠度分 析的方塊,與習知技術之可靠度分析方塊44相比較,^ ^ 具有下列的特徵:Amendment No. 91120000 V. Description of the Invention (! 6) 574743 Test Block 4 3 refers to the test operation of the product quality after the product is manufactured, such as wafer acceptance test (wafer accePtance test) and die probe test (Chipprobingtest). The reliability analysis block 44 refers to the V-reliability analysis of a large number of products and related manufacturing steps. At least the reliability of the two parts of the process guilty degree and the product reliability. Manufacturing step related data box 45 refers to all the data generated during the manufacturing step box 42 when all the actions in the manufacturing step box 42 are performed, the machine performing these actions, the operator performing these actions, and so on. Output of relevant data box 4 6 refers to all the data generated in the test box 43, the execution of all the actions in the test box 43, the machine performing these actions, the operator performing these actions, and so on. As shown in Figures 4C and 4D, in addition to the conventional three major process blocks (R & D design step block 4i, manufacturing step block 42 and test block 43) and two major related messages, the semiconductor manufacturing process to which the present invention is applied. In addition to the blocks (data box 45 related to the manufacturing steps and the data box 46 related to the output), there are additionally an embedded reliability analysis block 47, an online reliability monitoring sub-block 48, and a reliability control sub-block 49. Here, the implantability analysis block 47 replaces the reliability analysis block 44 of the conventional technology, and the online reliability monitoring sub-block 4 8 can be at least a wafer-level reliability analysis. The implanted reliability analysis block 47 is a block for performing the implanted reliability analysis. Compared with the reliability analysis block 44 of the conventional technology, ^ ^ has the following characteristics:
第21頁 20〇3.10.30.021 574743 案號 91120000 五、發明說明(17)Page 21 20〇3.10.30.021 574743 Case No. 91120000 V. Description of the invention (17)
(1)植入式可靠度分析方塊47會接收製造步驟相關資 料方塊45以及產出相關資料方塊46,並根據這些資料來進 行植入式可靠度分析。 (2 )植入式可罪度分析方塊4 7會分別與製造步驟方塊 42以及測試方塊43二者進行系統化地互動,例如資料交換 、即時修正、以及即時狀況報告等等。 (3 )植入式可罪度分析方塊4 7會系統化地將運作处果 傳輸至研發設計步驟方塊41。藉此,使得研發設計步驟方 塊41的運作即可引入可靠度的考量。 • ( 4 )植入式可罪度分析方塊4 γ至少可以進行下列的動 ,·製程可靠度評估、晶圓層級可靠度分析、產品可靠度 :平估、數據分析、排程、報表產生、失效分析以及失效分 八在此線上可罪度監測次方塊4 8係作為植入式可靠度 始H ^塊47與製造步驟方塊42的界面,而可靠度控制次方 Α糸作為植入式可罪度分析方塊4 7與製造步驟方塊4 2的 』然地’習知技術中不同步驟方塊(4丨/ 4 2 4 3 4 4 )之 六關2為單行道,先進行方塊無法預知隨後進行方塊的 且谷i Ik後進行方塊的内容也不能回饋至先進行方塊。並 益不,訊息相關方塊(4 5 / 4 6 )不只是相互獨立的,而且也 …、法回绩至各個訊息相關方塊(4 1 /42/43/44)。 之相對地,本發明可以讓不同步驟方塊(41 /4 2/4 3/44 ) 間的關係為雙向來回,先進行方塊可以預知隨後進行方(1) The implanted reliability analysis block 47 receives the manufacturing step-related data block 45 and the output-related data block 46, and performs the implanted reliability analysis based on these data. (2) The implantable guilt analysis block 47 will systematically interact with both the manufacturing step block 42 and the test block 43, such as data exchange, real-time correction, and real-time status report. (3) The implantable guilty degree analysis block 47 will systematically transmit the operational results to the R & D and design step block 41. This allows the operation of the R & D and design step block 41 to introduce reliability considerations. • (4) Implantable guilty analysis block 4 γ can perform at least the following actions: process reliability assessment, wafer-level reliability analysis, product reliability: leveling, data analysis, scheduling, report generation, The failure analysis and failure are divided into eight parts on this line. The crime monitoring sub-block 48 is used as the interface between the implantable reliability starting block 47 and the manufacturing step block 42, and the reliability control power Α 糸 is used as an implantable Sin degree analysis block 4 7 and the manufacturing step block 4 2 of the "naturally" conventional technology in the different step blocks (4 丨 / 4 2 4 3 4 4) Six levels 2 are one-way streets. The content of the block that is made after the block is not returned to the block that was made first. What's more, the message-related blocks (4 5/4 6) are not only independent of each other, but also…, and return to each message-related block (4 1/42/43/44). In contrast, the present invention can make the relationship between the blocks of different steps (41/4 2/4 3/44) back and forth in two directions.
第22頁 2003. 10.30. 022 574743 S1_9U20000 Λ___3. 曰 修正 五、發明說明(18) 塊的内容,隨後進行 並且不同訊息相關 罪度分析方塊4 7相互 析方塊4 7回饋至各個 最後,必須強調 種可能功能與各種構 有特別明文限制,應 所需要的變化、功能 以上所述僅為本 定本發明之申請專利 精神下所完成之等效 專利範圍中。 方塊的内容也可以回饋至先進行方塊 方塊(4 5 / 4 6 )不只可以透過植入式可 整合的,也可以透過植入式可靠度分 訊息相關方塊( 41 /42/43/44)。 地是上述實施例之各種可能變化、各 成都是相互獨立的,除非上述說明中 用各實施例時都可以視實際需要選擇 與構成。 發明之較佳實施例而已,並非用以限 範圍;凡其它未脫離本發明所揭示之 改變或修飾,均應包含在下述之申請Page 22 2003. 10.30. 022 574743 S1_9U20000 Λ ___ 3. Revision V. Description of the Invention (18) Block, and then carried out and analysis of crimes related to different messages Block 4 7 Mutual analysis of blocks 4 7 Feedback to the end, we must emphasize the species The possible functions and various structures are subject to special explicit restrictions. The above-mentioned changes and functions are only within the scope of equivalent patents completed under the spirit of the patent application of the present invention. The content of the box can also be fed back to the first box. The box (4 5/4 6) can be integrated not only through implantation, but also through the reliability of the message (41/42/43/44). The ground is that all possible variations and components of the above embodiments are independent of each other, unless each embodiment is used in the above description, it can be selected and configured according to actual needs. The preferred embodiments of the invention are only intended to limit the scope; all other changes or modifications that do not depart from the disclosure of the present invention should be included in the following applications
第23頁 2003.10.30.023 574743 _案號91120000_年月日__ 圖式簡單說明 【圖式簡單說明】 第一 A圖至第一 B圖為習知技術之主要特徵的橫截面示意 圖; 第一 C圖至第一 D圖為本發明之主要特徵的橫截面示意圖; 第二圖為本發明一較佳實施例的基本流程圖; 第三A圖、第三B圖及第三C圖為本發明另一較佳實施例的 基本構成圖,以及 第四A圖、第四B圖、第四C圖及第四D圖分別顯示習知半導 體製造程序以及應用本發明之半導體製造程序的基 本流程。 〔主要部分之代表符號〕 11 機器 12 步驟 13 資訊 14 資料庫 15 植入式可靠度分析 21 第一背景方塊 22 第二背景方塊 23 調整方塊 24 可靠度測量方塊 25 回饋方塊 31 植入式可靠度分析總成 3 2 失效處理總成 33 失效報告總成Page 23 2003.10.30.023 574743 _Case No. 91120000_Year Month and Day__ Brief Description of Drawings [Simplified Description of Drawings] Figures A through B are schematic cross-sectional views of the main features of the conventional technology; Figures C to D are schematic cross-sectional views of the main features of the present invention; Figure 2 is a basic flowchart of a preferred embodiment of the present invention; Figures A, B and C The basic configuration diagram of another preferred embodiment of the invention, and the fourth A, fourth B, fourth C, and fourth D diagrams respectively show the basic semiconductor manufacturing process and the basic flow of the semiconductor manufacturing process to which the present invention is applied. . [Representative symbols of main parts] 11 Machine 12 Step 13 Information 14 Database 15 Implanted reliability analysis 21 First background block 22 Second background block 23 Adjustment block 24 Reliability measurement block 25 Feedback block 31 Implanted reliability Analysis assembly 3 2 Failure handling assembly 33 Failure report assembly
第24頁 2003. 10.30.024 574743 案號91120000_年月日_修正 圖式簡單說明 34 排程總成 35 產品驗證/監測/評估報告總成 36 製程驗證/監測/評估報告總成 37 晶圓層級可靠度控制/在線製程評估/監測總成 38 報告總成 39 分析總成 41 研發設計步驟方塊 42 製造步驟方塊 43 測試方塊 44 可靠度分析方塊 45 製造步驟相關資料方塊 46 產出相關資料方塊 47 植入式可靠度分析方塊 48 線上可靠度監測次方塊 49 可靠度控制次方塊Page 24 2003. 10.30.024 574743 Case No. 91120000_Year Month Day_Amendment of the simple diagram 34 Schedule Assembly 35 Product Verification / Monitoring / Evaluation Report Assembly 36 Process Verification / Monitoring / Evaluation Report Assembly 37 Wafers Hierarchical Reliability Control / Online Process Evaluation / Monitoring Assembly 38 Report Assembly 39 Analysis Assembly 41 R & D Design Step Block 42 Manufacturing Step Block 43 Test Block 44 Reliability Analysis Block 45 Manufacturing Process Related Data Box 46 Output Related Data Box 47 Implantable reliability analysis block 48 Online reliability monitoring sub-block 49 Reliability control sub-block
第25頁 2003.10.30.025Page 25 2003.10.30.025
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6999897B2 (en) | 2004-03-11 | 2006-02-14 | Powerchip Semiconductor Corp. | Method and related system for semiconductor equipment early warning management |
US7260444B2 (en) | 2005-04-26 | 2007-08-21 | Powerchip Semiconductor Corp. | Real-time management systems and methods for manufacturing management and yield rate analysis integration |
TWI417715B (en) * | 2005-08-18 | 2013-12-01 | Brooks Automation Inc | System and method for electronic diagnostics of a process vacuum environment |
TWI833488B (en) * | 2022-03-02 | 2024-02-21 | 日商愛德萬測試股份有限公司 | Semiconductor test result analysis device, semiconductor test result analysis method and computer program |
TWI833489B (en) * | 2022-03-02 | 2024-02-21 | 日商愛德萬測試股份有限公司 | Semiconductor test result analysis device, semiconductor test result analysis method and computer program |
-
2002
- 2002-09-02 TW TW91120000A patent/TW574743B/en not_active IP Right Cessation
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6999897B2 (en) | 2004-03-11 | 2006-02-14 | Powerchip Semiconductor Corp. | Method and related system for semiconductor equipment early warning management |
US7260444B2 (en) | 2005-04-26 | 2007-08-21 | Powerchip Semiconductor Corp. | Real-time management systems and methods for manufacturing management and yield rate analysis integration |
TWI417715B (en) * | 2005-08-18 | 2013-12-01 | Brooks Automation Inc | System and method for electronic diagnostics of a process vacuum environment |
TWI833488B (en) * | 2022-03-02 | 2024-02-21 | 日商愛德萬測試股份有限公司 | Semiconductor test result analysis device, semiconductor test result analysis method and computer program |
TWI833489B (en) * | 2022-03-02 | 2024-02-21 | 日商愛德萬測試股份有限公司 | Semiconductor test result analysis device, semiconductor test result analysis method and computer program |
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