CN1479380A - Silicon nitride read-only memory cell for lowering secondary effect and its manufacturing method - Google Patents
Silicon nitride read-only memory cell for lowering secondary effect and its manufacturing method Download PDFInfo
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- CN1479380A CN1479380A CNA021421919A CN02142191A CN1479380A CN 1479380 A CN1479380 A CN 1479380A CN A021421919 A CNA021421919 A CN A021421919A CN 02142191 A CN02142191 A CN 02142191A CN 1479380 A CN1479380 A CN 1479380A
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Abstract
The storage unit is composed of a substrate, silicon monoxide/silicon nitride/silicon oxide layer on the substrate, the grid electrode, the source/drain electrodes and shallow pocket doping area. The grid electrode is on silicon monoxide/silicon nitride/silicon oxide layer. The source/drain electrodes adjacent to grid electrode are on the substrate. The shallow pocket doping area adjacent to grid electrode is located between source/drain electrode and silicon monoxide/silicon nitride/silicon oxide layer. The depth of shallow pocket doping area must be small enough to make the current of source/drain electrodes not be disturbed.
Description
Technical field
The invention relates to a kind of silicon nitride read-only memory unit (nitride read onlymemory cell is called for short NROM cell), and be particularly to the silicon nitride read-only memory unit of a kind of second effect of reduction (second-bit effect).
Background technology
The practice of silicon nitride read-only memory unit (NROM cell) is to form one deck charge immersing layer (trapping layer) in substrate earlier, it is by silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, abbreviation ONO) structure that lamination constituted, the layer that the i.e. conduct of silicon nitride layer wherein is absorbed in electric charge, and utilize this kind material to be called " silicon nitride read-only memory unit " as the read-only memory unit of charge immersing layer.Technology subsequently is to form a grid on the silicon oxide/silicon nitride/silicon oxide layer, again an ion implantation technology is carried out in substrate, to form the source/drain electrode (source/drain) of adjoins gate in substrate.
For silicon nitride read-only memory unit, a silicon nitride read-only memory unit can respectively store a position (bit) near the silicon nitride layer in the ONO layer of drain electrode and source electrode basically.Yet, can when carrying out reverse reading (reverse read), produce second effect if stored one near the drain electrode position; That is to say that the position that has originally existed can forward be read in influence, and energy barrier (barrier) is improved, the start voltage (threshold voltage is called for short Vt) that causes forward reading improves.And mostly present solution is to take to increase drain voltage (Vd), reduce effect (drain-induced barrier lowering to increase the energy barrier that drain voltage was caused, be called for short DIBL), come in response to the problems referred to above, but along with component size is constantly dwindled, excessive drain voltage also can cause operational difficulty.
Summary of the invention
Therefore, the purpose of this invention is to provide the silicon nitride read-only memory unit and the manufacture method thereof of second effect of a kind of reduction, increase in case the energy barrier that the leak-stopping pole tension is caused reduces effect (DIBL), and then the start voltage when increasing reverse reading.
A further object of the present invention provides the silicon nitride read-only memory unit and the manufacture method thereof of second effect of a kind of reduction, can not increase the minimizing energy barrier that drain voltage caused reduction effect (DIBL) under the drain voltage.
Another object of the present invention provides the silicon nitride read-only memory unit and the manufacture method thereof of second effect of a kind of reduction, and the energy barrier that can reduce drain voltage simultaneously and caused reduces effect (DIBL) and keeps the effect that forward reads.
According to above-mentioned and other purpose, the present invention proposes the silicon nitride read-only memory unit of second effect of a kind of reduction, be by a substrate, be arranged in suprabasil silicon monoxide/silicon nitride/silicon oxide layer, be positioned at a grid on the silicon oxide/silicon nitride/silicon oxide layer, be positioned at the source/drain electrode of substrate adjoins gate, and a shallow pocket (shallow pocket) doped region of adjoins gate is formed between source/drain electrode and silicon oxide/silicon nitride/silicon oxide layer, and the degree of depth of wherein shallow pocket doped region needs little interference-free to the electric current that makes the source of flowing to/drain electrode.
The present invention proposes a kind of method of making the silicon nitride read-only memory unit that reduces by second effect in addition, is included in and forms silicon monoxide/silicon nitride/silicon oxide layer in the substrate, forms a grid again on the silicon oxide/silicon nitride/silicon oxide layer.Then, be the cover curtain with the grid, a shallow pocket ion implantation technology is carried out in substrate, to form the shallow pocket doped region of adjoins gate in substrate, the degree of depth of wherein shallow pocket doped region need be small enough to make the electric current that forward reads interference-free.Then, implanting ions in the substrate outside shallow pocket doped region is with formation source/drain electrode.
The present invention is because adjoins gate has a shallow pocket doped region between source/drain electrode and silicon oxide/silicon nitride/silicon oxide layer, and the degree of depth of shallow pocket doped region is essential enough little, and the electric current that forward reads is interfered.Therefore, can prevent that energy barrier that drain voltage causes from reducing effect (DIBL) and increasing, and then the start voltage when increasing reverse reading.And, because the degree of depth of shallow pocket doped region proposed by the invention can not make the electric current that forward reads be interfered, so the energy barrier that can reduce drain voltage simultaneously and caused reduces effect (DIBL) and keeps the effect that forward reads.And the present invention is not increasing the minimizing energy barrier that drain voltage caused reduction effect (DIBL) under the drain voltage, so can guarantee the difficulty on the element operation.
Description of drawings
Fig. 1 is the generalized section according to the silicon nitride read-only memory unit (NROM cell) of second effect of reduction of a preferred embodiment of the present invention;
The present invention shown in Figure 2 and known silicon nitride read-only memory unit carry out forward with reverse read operation on start voltage (Vt) curve chart; And
Fig. 3 A to Fig. 3 C is the manufacturing process profile according to the silicon nitride read-only memory unit (NROM cell) of second effect of reduction of a preferred embodiment of the present invention.
100,300: substrate
101: silicon nitride layer
102,302: the silicon oxide/silicon nitride/silicon oxide stack layer
103: the electric charge recessed region
106: current flow path
110a, 110b, 310a, 310b: shallow pocket doped region
116a, 116b, 316a, 316b: source/drain electrode
200: the curve chart position
306: the cover curtain
308: shallow pocket ion implantation technology
312: clearance wall
314: ion implantation technology
Embodiment
Fig. 1 is according to the silicon nitride read-only memory unit of second effect of reduction (second-biteffect) of a preferred embodiment of the present invention generalized section of (nitride read only memory cell is called for short NROM cell).
Please refer to Fig. 1, the silicon nitride read-only memory unit of embodiments of the invention is by a substrate 100, be positioned at the silicon monoxide/silicon nitride/silicon oxide layer 102 in the substrate 100, be positioned at silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, abbreviation ONO) grid 104 on the layer 102, be arranged in source/drain electrode (source/drain) 116a of substrate 100 adjoins gate 104,116b, and be positioned at source/drain electrode 116a, the shallow pocket of adjoins gate 104 (shallow pocket) doped region 110a between 116b and the silicon oxide/silicon nitride/silicon oxide layer 102,110b forms, wherein shallow pocket doped region 110a, the degree of depth of 110b is less than 400 dusts, and preferred depths is less than the 200 Izod right sides; With and width for example be 500 dusts.When silicon nitride read-only memory unit has following characteristic when forward reading (forward read); That is to say, if there is electric charge (charge) to exist, the electric current that forward reads can be as shown in Figure 1 current flow path 106, near drain electrode 116b the time, flow, up to arriving drain electrode 116b from changing over towards substrate 100 inner constant depth along the flow direction of the passage (channel) between source/drain electrode 116a, 116b drain electrode 116b originally.Therefore, the shallow pocket doped region 110a of silicon nitride read-only memory unit of the present invention, the 110b degree of depth must reach little, not disturbed by it so that flow to the electric current of source/drain electrode 116a, 116b when forward reading, and the start voltage (threshold voltage is called for short Vt) when keeping it forward to read.
Please continue with reference to Fig. 1, when the silicon nitride layer 101 that has electric charge recessed region (trapping region) 103 in the silicon oxide/silicon nitride/silicon oxide layer 102 of drain electrode 116b top has stored one (bit), second effect that produce will be reduced to minimum because of the existence of shallow pocket doped region 110b during carrying out reverse reading (reverse read), the energy barrier that drain voltage caused that also can avoid energy barrier (barrier) reduction to be caused reduces effect (drain-induced barrierlowering, be called for short DIBL) increase, and then the start voltage (Vt) when promoting reverse reading.For making the present invention and known difference more obvious, please refer to shown in Figure 2.
Figure 2 shows that the present invention and known silicon nitride read-only memory unit carry out forward with reverse read operation on start voltage (Vt) curve chart.
Please refer to Fig. 2, when live width be 0.3 micron, when drain voltage is 1.6 volts, utilize silicon nitride read-only memory unit of the present invention and known silicon nitride read-only memory unit to carry out forward reading respectively, the graph of a relation of the start voltage of the start voltage in the time of can obtaining reverse reading when forward reading with reverse.As can be seen from Figure 2 after curve chart position 200, start voltage when being reverse reading is above 2.5 volts, and after the start voltage when forward reading surpasses 0.1 volt, identical forward reading under the start voltage, the measured reverse start voltage that reads of silicon nitride read-only memory unit of the present invention will be obviously greater than known numerical value.Therefore, the present invention can avoid energy barrier that drain voltage causes to reduce effect (DIBL) really to be increased, and then the start voltage (Vt) when promoting reverse reading.About the manufacture method of silicon nitride read-only memory unit of the present invention then shown in Fig. 3 A to Fig. 3 C.
Fig. 3 A to Fig. 3 C is the manufacturing process profile according to the silicon nitride read-only memory unit (NROM cell) of second effect of reduction of a preferred embodiment of the present invention.
Please refer to Fig. 3 A, in substrate 300, form silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, be called for short ONO) stack layer (stacked layer) 302, the nesting structural embedded control that it constituted is made up of one deck bottom oxide, one deck silicon nitride layer and one deck top oxide layer.Then, form one deck conductor layer on silicon oxide/silicon nitride/silicon oxide stack layer 302, with the grid 304 as silicon nitride read-only memory unit, wherein material for example is polysilicon (polysilicon layer).
Then, please refer to Fig. 3 B, on silicon oxide/silicon nitride/silicon oxide layer 302, form for example photoresistance of a cover curtain 306, to expose the zone of adjoins gate 304.Subsequently, carry out a shallow pocket ion implantation technology 308, to form shallow pocket doped region 310a, 310b in substrate 300, its degree of depth is less than 400 dusts; And preferred depths is less than the 200 Izod right sides, and the implant concentration of wherein shallow pocket ion implantation technology 308 for example is 1.5 * 10
18Cm
-3In addition,, also grid 304 can be used as the cover curtain of ion implantation technology, directly carry out shallow pocket ion implantation technology 308 even if in substrate 300, do not form cover curtain 306.
Subsequently, please refer to Fig. 3 C, remove cover curtain 306 (asking for an interview Fig. 3 B), be that grid 304 sidewalls form clearance wall 312.Then, an ion implantation technology 314 is carried out in substrate, in substrate 300, to form source/drain electrode 316a, the 316b of adjoins gate 304.
As mentioned above, feature of the present invention comprises:
1. the present invention prevents energy barrier reduction effect (DIBL) increase that drain voltage causes by the shallow pocket doped region of adjoins gate between source/drain electrode and the silicon oxide/silicon nitride/silicon oxide layer, and then the start voltage when increasing reverse reading.
2. the present invention can not increase the minimizing energy barrier that drain voltage caused reduction effect (DIBL) under the drain voltage.
3. the degree of depth of shallow pocket doped region proposed by the invention not be owing to can make the electric current that forward reads be interfered, so the energy barrier that can reduce drain voltage simultaneously and caused reduces effect (DIBL) and keeps the effect that forward reads.
Claims (15)
1. silicon nitride read-only memory unit that reduces by second effect is characterized in that this memory cell comprises:
One substrate;
Silicon monoxide/silicon nitride/silicon oxide layer is positioned in this substrate;
One grid is positioned on this silicon oxide/silicon nitride/silicon oxide layer;
One source/drain electrode is arranged in this substrate in abutting connection with this grid; And
One shallow pocket doped region, in abutting connection with this grid, it is interference-free that wherein the degree of depth of this shallow pocket doped region is small enough to make the electric current that flow to this source/drain electrode between this source/drain electrode and this silicon oxide/silicon nitride/silicon oxide layer.
2. the silicon nitride read-only memory unit of second effect of reduction as claimed in claim 1 is characterized in that the degree of depth of this shallow pocket doped region is less than 400 dusts.
3. the silicon nitride read-only memory unit of second effect of reduction as claimed in claim 1 is characterized in that the material of this grid comprises polysilicon.
4. the silicon nitride read-only memory unit of second effect of reduction as claimed in claim 1 is characterized in that the degree of depth of this shallow pocket doped region is less than 200 dusts.
5. method of making the silicon nitride read-only memory unit that reduces by second effect is characterized in that this method comprises:
One substrate is provided;
In this substrate, form silicon monoxide/silicon nitride/silicon oxide layer;
On this silicon oxide/silicon nitride/silicon oxide layer, form a grid;
On this silicon oxide/silicon nitride/silicon oxide layer, form a cover curtain, to expose a zone in abutting connection with this grid;
Implement a shallow pocket and implant technology, with in form a shallow pocket doped region in this substrate of this grid, wherein this shallow pocket doped region has one first degree of depth;
Remove this cover curtain; And
Form the source/drain electrode in abutting connection with this grid in this substrate, the most shallow degree of depth of flow path when approaching this shallow pocket doped region that flow to the electric current of this source/drain electrode when wherein forward reading is one second degree of depth, and wherein this second degree of depth is greater than this first degree of depth.
6. manufacturing as claimed in claim 5 reduces the method for the silicon nitride read-only memory unit of second effect, it is characterized in that the degree of depth of this shallow pocket doped region is less than 400 dusts.
7. manufacturing as claimed in claim 5 reduces the method for the silicon nitride read-only memory unit of second effect, it is characterized in that the degree of depth of this shallow pocket doped region is less than 200 dusts.
8. manufacturing as claimed in claim 5 reduces the method for the silicon nitride read-only memory unit of second effect, it is characterized in that the material of this grid comprises polysilicon.
9. manufacturing as claimed in claim 5 reduces the method for the silicon nitride read-only memory unit of second effect, it is characterized in that, this cover curtain comprises photoresistance.
10. manufacturing as claimed in claim 5 reduces the method for the silicon nitride read-only memory unit of second effect, it is characterized in that, forms in abutting connection with the step of this source/drain electrode of this grid in this substrate, comprising:
Form a clearance wall in this gate lateral wall; And
An ion implantation technology is carried out in this substrate, in this substrate, to form this source/drain electrode in abutting connection with this grid.
11. a method of making the silicon nitride read-only memory unit that reduces by second effect is characterized in that this method comprises:
One substrate is provided;
In this substrate, form silicon monoxide/silicon nitride/silicon oxide layer;
On this silicon oxide/silicon nitride/silicon oxide layer, form a grid;
Implement a shallow pocket and implant technology, in this substrate, to form the shallow pocket doped region with one first degree of depth, the most shallow degree of depth of the current flow path during wherein this first degree of depth is shallower than and forward reads under this shallow pocket doped region; And
In this substrate, form a source/drain electrode.
12. manufacturing as claimed in claim 11 reduces the method for the silicon nitride read-only memory unit of second effect, it is characterized in that the degree of depth of this shallow pocket doped region is less than 400 dusts.
13. manufacturing as claimed in claim 11 reduces the method for the silicon nitride read-only memory unit of second effect, it is characterized in that the degree of depth of this shallow pocket doped region is less than 200 dusts.
14. manufacturing as claimed in claim 11 reduces the method for the silicon nitride read-only memory unit of second effect, it is characterized in that the material of this grid comprises polysilicon.
15. manufacturing as claimed in claim 11 reduces the method for the silicon nitride read-only memory unit of second effect, it is characterized in that, forms the step of this source/drain electrode in this substrate, comprising:
Form a clearance wall in this gate lateral wall; And
An ion implantation technology is carried out in this substrate, in this substrate, to form this source/drain electrode in abutting connection with this grid.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 02142191 CN1260822C (en) | 2002-08-30 | 2002-08-30 | Silicon nitride read-only memory cell for lowering secondary effect and its manufacturing method |
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| CN 02142191 CN1260822C (en) | 2002-08-30 | 2002-08-30 | Silicon nitride read-only memory cell for lowering secondary effect and its manufacturing method |
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| CN1479380A true CN1479380A (en) | 2004-03-03 |
| CN1260822C CN1260822C (en) | 2006-06-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100379027C (en) * | 2004-04-14 | 2008-04-02 | 旺宏电子股份有限公司 | Method for using drain coupling to suppress the second bit effect of localized split floating gate devices |
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2002
- 2002-08-30 CN CN 02142191 patent/CN1260822C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100379027C (en) * | 2004-04-14 | 2008-04-02 | 旺宏电子股份有限公司 | Method for using drain coupling to suppress the second bit effect of localized split floating gate devices |
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| CN1260822C (en) | 2006-06-21 |
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