CN1231963C - Process for preparing silicon nitride ROM - Google Patents
Process for preparing silicon nitride ROM Download PDFInfo
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- CN1231963C CN1231963C CN 01120413 CN01120413A CN1231963C CN 1231963 C CN1231963 C CN 1231963C CN 01120413 CN01120413 CN 01120413 CN 01120413 A CN01120413 A CN 01120413A CN 1231963 C CN1231963 C CN 1231963C
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Abstract
The present invention relates to a manufacture method of a silicon nitride ROM, which comprises the following steps: a capture layer is orderly formed on a substrate; next, a patterned light-resisting layer is formed on the substrate, and the light-resisting layer is used as a cover curtain; a step of pocket ion implantation is carried out, a first type of dopant is implanted in a source pole/drawing pole area of the substrate, and then, part of the capture layer is removed in order to make the capture layer patterned; finally, a step of source pole/drawing pole ion implantation is carried out, and a second type of dopant is implanted in the source pole/drawing pole area of the substrate; then, the light-resisting layer is removed; subsequently, the capture layer is used as the cover curtain to carry out thermal process in order to make the surface of the substrate of the source pole/drawing pole area form an embedding type source pole/drawing pole oxidizing layer; meanwhile, the second shape of dopant forms an embedding type source pole/drawing pole below the embedding type source pole/drawing pole oxidizing layer, and the first type of dopant forms a pocket type doping area at the margin of a channel area at the circumference of the embedding type pole/drawing pole due to thermal diffusion; finally, a grid pole of a conductive body is formed on the substrate.
Description
Technical field
The invention relates to the formation method of a kind of pouch-type doped region (pocket doping region), and particularly relevant for a kind of manufacture method of utilizing thermal diffusion method to form the silicon nitride ROM of pouch-type doped region.
Background technology
Wipe and programmable read only memory (Erasable ProgrammableRead-Only Memory known, EPROM), quickflashing can be wiped and programmable read only memory (FlashEPROM) or quickflashing are erasable removes and programmable read only memory (Flash ElectricallyErasable Programmable Read-Only Memory, Flash EEPROM) in the element, its grid part is made of floating grid and control gate.Write fashionablely carrying out data, hot electron will be via the pocket doped region of the substrate that is positioned at floating grid below, and tunnelling (tunneling) is arranged in the thin silicon dioxide layer of floating grid below and enters floating grid and sink into floating grid, to store the data that is write.
Known floating grid is made of polysilicon mostly, when the semiconductor element integrated level improves, can be accompanied by the problem that electric leakage takes place, therefore, known solution is to utilize the formed seizure layer of silica-silicon-nitride and silicon oxide (Trapping Layer) structure to replace floating grid, mode to utilize hot carrier to inject is stored in the silicon nitride of insulation charge carrier, reaches the purpose of data storage.With silica-silicon-nitride and silicon oxide as the memory element of catching layer, according to the mode of its operation can be called silicon nitride ROM (Nitride Read Only Memory, NROM), ONO EEPROM or be called the SONOS element.
Known silicon nitride ROM element comprises a substrate, has silicon oxide/silicon nitride/silicon oxide structure (ONO) in this substrate, and it is formed is following oxide layer, silicon nitride layer and last silicon oxide dielectric layer in regular turn.Form gate conductor layer at the silicon oxide/silicon nitride/silicon oxide superstructure.In silicon oxide/silicon nitride/silicon oxide structure substrate on two sides, have source area and drain region.Has a channel region below the silicon oxide/silicon nitride/silicon oxide structure and between source area and drain region.In addition, also include the pocket doped region at silicon oxide/silicon nitride/silicon oxide layer structure down either side and source area and drain region adjacent.
The known method for preparing the pouch-type doped region, it is the method for utilizing the inclination angle ion to inject, impurity is flow into channel region edge and the adjoiner of the predetermined source electrode extension area that forms with the drain electrode extension area, and the mode of promptly utilizing the inclination angle ion to inject is formed at predetermined zone with doping.Then, carry out thermal process again, make the impurity that is injected evenly disperse to form the pocket doped region.
Because being the method for utilizing the inclination angle ion to inject, the pocket doped region carries out the injection of impurity, therefore, the process of injecting, injecting the region shape of impurity can't control effectively, and after Technology for Heating Processing, the pocket doped region can be expanded and form bigger zone, causes being positioned at the contraction in length of the channel region under silica-silicon-nitride and silicon oxide structure.
When integrated artistic when high integration develops, because known inclination angle is injected formed pouch-type doped region and can't be dwindled thereupon, cause when reducing the grid live width, the channel region that is positioned at the grid below has more obvious shortening phenomenon, even the pocket doped region that is respectively adjacent to source electrode, drain electrode is contacted, and the phenomenon that causes critical voltage (Threshold Voltage) to rise, (Reverse Short Channel Effect RSCE) influences the conductivity and the efficient (Performance) of element promptly to produce contrary short-channel effect.
Summary of the invention
Therefore, the objective of the invention is to propose a kind of formation method of pouch-type doped region.The method can be so that the pouch-type doped region forms along the edge of source area and drain electrode, and can not make channel region shorten, so that element has good electrical conductivity.
For addressing the above problem, the present invention is vertically injected among predetermined origin polar region and the drain region by the impurity that earlier pouch-type is injected, again when utilizing thermal process to form embedded source electrode zone and flush type drain region, make the substrate raceway groove of the impurity thermal diffusion of pouch-type injection, form the pouch-type doped region to silica-silicon-nitride and silicon oxide structural base.Because method of the present invention can be by the size and the profile of thermal diffusion rate controlled pocket doped region, thereby can avoid contrary short channel phenomenon, prevent component wear and improve the qualification rate of product.
The present invention proposes a kind of manufacture method of silicon nitride ROM, is to form one in regular turn to catch layer in substrate.Then, form the photoresist layer of patterning in substrate, the basal region of the seizure layer below that wherein aforementioned photoresist layer covered is defined as channel region, and the basal region of exposed seizure layer below is defined as source area and drain region.Then, with aforementioned photoresist layer is mask, carry out pocket ion implantation step, the first type impurity is injected source area and the drain region of substrate, is mask with this photoresist layer again, removes that part is caught layer so that the seizure layer patternization, be mask with this photoresist layer at last, carry out source area and drain region ion implantation step, the second type impurity is injected the source area and the drain region of substrate, then, remove photoresist layer.Then, to catch layer is that mask carries out thermal process, so that the substrate surface of source area and drain region forms flush type source electrode oxide layer and flush type drain electrode oxide layer, make the second type impurity below flush type source electrode oxide layer and flush type drain electrode oxide layer, form flush type source electrode and flush type drain electrode simultaneously, the first type impurity forms corresponding pouch-type doped region at the flush type source electrode with the channel region edge of flush type drain electrode periphery because of thermal diffusion, at last, in substrate, form the conductor grid.
The present invention flows into source area and drain region earlier with the impurity of pouch-type doped region, utilizes the mode of thermal diffusion to form the pouch-type doped region again.The method can be controlled the shape of pouch-type doped region effectively, to avoid known inclination angle ion to inject caused irregularly shaped, and owing to can control the width of the capable doped region of pocket effectively, therefore can avoid channel region to shorten phenomenon, and then improve the puncture voltage of element.
For above and other objects of the present invention, feature and advantage can be become apparent, an embodiment cited below particularly, and conjunction with figs. is described in detail below:
Description of drawings
Fig. 1 to Fig. 5 is the schematic diagram of manufacture method of the silicon nitride ROM of the embodiment of the invention.
Fig. 6 is the drain voltage of silicon nitride ROM of the embodiment of the invention and the graph of a relation of critical voltage difference.
Description of reference numerals:
100: substrate
102: oxide layer
104: nitride layer
106: dielectric layer
108: photoresist layer
110: catch layer
112: the first type impurities
114: the second type impurities
116: flush type source electrode oxide layer and flush type drain electrode oxide layer
118: flush type source electrode and flush type drain electrode
120: the pouch-type doped region
122: the conductor grid
150: channel region
160: source electrode and drain region
Embodiment
Fig. 1 to Fig. 5 is the schematic diagram of manufacture method of the silicon nitride ROM of the embodiment of the invention.Please refer to Fig. 1, form oxide layer 102, nitride layer 104, dielectric layer 106 in regular turn in substrate 100, wherein oxide layer 102, nitride layer 104 are collectively referred to as with dielectric layer 106 and catch layer 110.Oxide layer 102 for example is a silicon dioxide layer, and nitride layer 104 for example is a silicon nitride layer, and dielectric layer 106 for example is a silicon dioxide layer.The formation method of oxide layer 102 for example is a thermal oxidation method, and the formation method of dielectric layer 106 for example is a thermal oxidation method, and the formation method of nitride layer 104 is chemical vapour deposition technique for example.
Then, in substrate 100, form the photoresist layer 108 of patterning, substrate 100 zone definitions of seizure layer 110 below that photoresist layer 108 is covered are channel region 150, part substrate 100 zone definitions of exposed seizure layer 110 below are source area and drain region 160, and wherein photoresist layer 108 comprises one of positive photoresist layer and negative photoresist layer.
Then, please refer to Fig. 2, utilize photoresist layer 108 to be mask, carry out pocket ion implantation step, the first type impurity 112 is injected the source area and the drain region 160 of substrate 100.Wherein first impurity 112 for example is a P type impurity, and P type impurity comprises boron ion or BF
2When the P type impurity that is injected when pocket ion implantation step was the boron ion, the dosage of its injection for example was 5.0 * 10
12/ cm
2～1.0 * 10
13/ cm
2About; The energy that injects for example is about 40KeV～60KeV.
Then, please refer to Fig. 3, utilize photoresist layer 108 to be mask, carry out etching step, remove part and catch layer 110, expose substrate 100, so that catch layer 110 patterning.The method that wherein removes part seizure layer 110 for example is dry ecthing method.
Then, please refer to Fig. 4, utilize photoresist layer 108 to be mask, carry out source area and drain ion implantation step, the second type impurity 114 is injected the source area and the drain region 160 of substrate 100.Wherein to mix 114 matter for example be N type impurity to second type, and N type impurity is selected from one of group that arsenic ion and phosphonium ion form.When the N type impurity that is injected when source area and drain region ion implantation step was arsenic ion, its dosage for example was 2.0 * 10
15/ cm
2～4.0 * 10
15/ cm
2About; Energy for example is about 40KeV～60KeV.
Then, please refer to Fig. 5, remove photoresist layer 108, expose and catch layer 110, the method for wherein removing photoresist layer 108 for example divests method for wet type or dry type divests method.
Then, utilize and catch layer 110 as mask, carry out thermal process, so that substrate 100 surfaces of source area and drain region 160 form flush type source electrode oxide layer and flush type drain electrode oxide layer 116, make the mode of the second type impurity 114 simultaneously via thermal diffusion, then form corresponding pouch-type doped region 120 at drain channel region 150 edges of 118 peripheries of flush type source electrode and flush type and below flush type source electrode oxide layer and flush type drain electrode oxide layer 116, form flush type source electrode and flush type 118, the first type impurities that drain because of thermal diffusion.Wherein thermal process for example is to implement about 750～900 degree Celsius.
Because the quality of the first type impurity 112 is less than the quality of the second type impurity 114, therefore, the diffusion rate of the first type impurity 112 is higher than the diffusion rate of the second type impurity 114, so in the process of thermal diffusion, the first type impurity can be diffused in substrate 100 raceway grooves of catching under the layer 110 by the first type impurity doped region, and forms corresponding pouch-type doped region 120 at drain channel region 150 edges of 118 peripheries of flush type source electrode and flush type.
Then, in substrate 100, form one deck conductor layer, utilize the mode of lithography again, this conductor layer of patterning and form conductor grid 122.
Then, please refer to Fig. 6, for the pocket doped region that utilizes formed pocket doped region of thermal diffusion and tradition to utilize the direct mode of injecting with the inclination angle ion to form of the present invention compares, critical voltage when by experimental data as can be known, pocket doped region of the present invention inject to be caught layer with charge carrier under identical drain voltage is lower than the critical voltage of traditional pocket doped region.This is because the size and the profile of pocket doped region of the present invention can be controlled effectively, and to keep certain channel length, therefore can not take place has more stable critical voltage against short-channel effect.
The present invention utilizes the mode of thermal diffusion to form the pouch-type doped region, therefore can control the shape of pouch-type doped region effectively, so can avoid known oblique angle to inject caused irregularly shaped, and owing to can control the width of the capable doped region of pocket effectively, therefore can avoid channel region to shorten phenomenon, and then improve the puncture voltage of element.
Though the present invention with a NROM as the embodiment explanation as above; right its is not in order to limit the present invention; any person skilled in the art; without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations; for example, the present invention can be applied in general memory element or the general semiconductor element, so protection scope of the present invention is when being as the criterion with claims.
Claims (17)
1. the manufacture method of a silicon nitride ROM, it is characterized by: this method comprises:
One substrate is provided;
In this substrate, form one and catch layer, this seizures layer by an oxide layer, be positioned at the mononitride layer on this oxide layer and the dielectric layer that is positioned on this nitride layer is constituted;
In this substrate, form a photoresist layer of patterning, this basal region of part of this seizure layer below that wherein this photoresist layer covered is defined as a channel region, and this basal region of part of this exposed seizure floor below is defined as an one source pole district and a drain region;
With this photoresist layer is mask, carries out a pocket ion implantation step, one first type impurity is injected this source area and this drain region of this substrate;
With this photoresist layer is mask, removes this seizure layer of part, so that should catch layer patternization;
With this photoresist layer is mask, carries out one source pole district and drain region ion implantation step, one second type impurity is injected this source area and this drain region of this substrate;
Remove this photoresist layer;
With this seizure layer is mask, carry out a thermal process, so that this substrate surface of this source area and this drain region forms a flush type source electrode oxide layer and flush type drain electrode oxide layer, make this second type impurity form a flush type source electrode and flush type drain electrode in this flush type source electrode oxide layer and this flush type drain electrode oxide layer below simultaneously, this first type impurity forms a corresponding pouch-type doped region at this flush type source electrode with this channel region edge of this flush type drain electrode periphery because of thermal diffusion; And
In this substrate, form a conductor grid.
2. the manufacture method of silicon nitride ROM as claimed in claim 1, it is characterized by: this first type impurity is the P type, this second type impurity is the N type.
3. the manufacture method of silicon nitride ROM as claimed in claim 2, it is characterized by: this first type impurity is selected from boron ion or BF
2One of.
4. the manufacture method of silicon nitride ROM as claimed in claim 2, it is characterized by: this first type impurity of this pocket ion implantation step is the boron ion, and its dosage is 5.0 * 10
12/ cm
2～1.0 * 10
13/ cm
2, energy is 40KeV～650KeV.
5. the manufacture method of silicon nitride ROM as claimed in claim 2 is characterized by: this second type impurity is selected from one of group that arsenic ion and phosphonium ion form.
6. the manufacture method of silicon nitride ROM as claimed in claim 2, it is characterized by: this second type impurity of this source area and drain ion implantation step is an arsenic ion, and its dosage is 2.0 * 10
15/ cm
2～4.0 * 10
15/ cm
2, energy is 40KeV～60KeV.
7. the manufacture method of silicon nitride ROM as claimed in claim 1 is characterized by: the execution between 750 degree～900 degree Celsius of this thermal process.
8. the formation method of the pouch-type doped region of a memory element is characterized by: comprising:
One substrate is provided;
Form a mask layer in this substrate, wherein this basal region of the part that this mask layer covered is defined as a channel region, and this basal region of exposed part is defined as an one source pole district and a drain region;
Utilize this mask layer to carry out a pocket ion implantation step, one first type impurity is injected this source area and this drain region of this substrate;
Utilize this mask layer once more, carry out one source pole district and drain region ion implantation step, one second type impurity is injected among this source area and this drain region of this substrate; Wherein the quality of the second type impurity is greater than the quality of the first type impurity; And
Carry out a thermal process, so that this second type impurity forms a flush type source electrode and flush type drain electrode because of thermal diffusion, this first type impurity forms a corresponding pouch-type doped region in this flush type source electrode with this channel region edge of this flush type drain electrode periphery because of thermal diffusion.
9. the formation method of the pouch-type doped region of memory element as claimed in claim 8, it is characterized by: the doping type of this first type impurity is the P type, this second type impurity is the N type.
10, the formation method of the pouch-type doped region of memory module as claimed in claim 9, wherein this first type impurity is selected from boron ion or BF
2One of.
11, the formation method of the pouch-type doped region of memory module as claimed in claim 9, wherein this first type impurity of this pocket ion implantation step is the boron ion, and its dosage is 5.0 * 10
12/ cm
2～1.0 * 10
13/ cm
2, energy is 40KeV～60KeV.
12. the formation method of the pouch-type doped region of memory element as claimed in claim 8 is characterized by: this thermal process is implemented between 750 degree～900 degree Celsius.
13. the formation method of the pouch-type doped region of a semiconductor element is characterized by: this method comprises:
One substrate is provided;
Form a mask layer in this substrate, wherein this basal region of the part that this mask layer covered is defined as a channel region, and this basal region of exposed part is defined as an one source pole district and a drain region;
Utilize this mask layer to carry out a pocket ion implantation step, one first type impurity is injected among this source area and this drain region of this substrate;
Utilize this mask layer once more, carry out one source pole district and drain region ion implantation step, one second type impurity is injected among this source area and this drain region of this substrate, wherein the quality of the second type impurity is greater than the quality of the first type impurity; And
Carry out a thermal process, so that this second type impurity forms a flush type source electrode and flush type drain electrode because of thermal diffusion, this first type impurity forms a corresponding pouch-type doped region in this flush type source electrode with this channel region edge of this flush type drain electrode periphery because of thermal diffusion.
14. the formation method of the pouch-type doped region of semiconductor element as claimed in claim 13 is characterized by: wherein this first type impurity is the P type; This second type impurity is the N type.
15, the formation method of the pouch-type doped region of semiconductor subassembly as claimed in claim 14, wherein this first type impurity is selected from boron ion or BF
2One of.
16, the formation method of the pouch-type doped region of semiconductor subassembly as claimed in claim 14, wherein this first type impurity of this pocket ion implantation step is the boron ion, and its dosage is 5.0 * 10
12/ cm
2～1.0 * 10
13/ cm
2, energy is 40KeV～60KeV.
17. the formation method of the pouch-type doped region of semiconductor element as claimed in claim 13 is characterized by: this thermal process is implemented between 750 degree～900 degree Celsius.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01120413 CN1231963C (en) | 2001-07-12 | 2001-07-12 | Process for preparing silicon nitride ROM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01120413 CN1231963C (en) | 2001-07-12 | 2001-07-12 | Process for preparing silicon nitride ROM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1396652A CN1396652A (en) | 2003-02-12 |
| CN1231963C true CN1231963C (en) | 2005-12-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01120413 Expired - Fee Related CN1231963C (en) | 2001-07-12 | 2001-07-12 | Process for preparing silicon nitride ROM |
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| CN (1) | CN1231963C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1302540C (en) * | 2003-07-10 | 2007-02-28 | 旺宏电子股份有限公司 | Method for promoting memory cell confining force of silicon nitride ROM |
| CN100394611C (en) * | 2003-08-18 | 2008-06-11 | 旺宏电子股份有限公司 | ONO flash memory digital set for eliminating interferes between adjacent memory cells |
| CN1321459C (en) * | 2003-10-22 | 2007-06-13 | 应用智慧有限公司 | Depressed trapped memory |
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2001
- 2001-07-12 CN CN 01120413 patent/CN1231963C/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| CN1396652A (en) | 2003-02-12 |
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