CN1477697A - Analysis methd of power supply random signal and its reducing method - Google Patents
Analysis methd of power supply random signal and its reducing method Download PDFInfo
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Abstract
The present invention relates to a method for analyzing and reducing power supply noise in the designing process of integrated circuit. Firstly, it utilizes computer-aided design software to analyze the related material of integrated circuit design and obtain the power supply network model of integrated circuit design, then defines that the power supply network model is formed from mutually-connected several unit blocks. After the related material is analyzed, the number of elements and their type parameters of electrically-connecting to all the unit blocks can be known, and can be used as element reference material of power supply network model unit block, then the equivalent circuit formed from elements electrically-connected to unit block can be used to calculate the voltage drop due to operation of every unit block.
Description
Technical field
The present invention relates to integrated circuit technique, be analytical method and reduction method about a kind of methd of power supply random signal (Power Noise), be particularly to be applied in the integrated circuit (IC) design process, a kind of analysis of methd of power supply random signal and reduction method, by suitable configuration capacitor in integrated circuit, to reduce the methd of power supply random signal in the integrated circuit.
Background technology
Development along with semiconductor fabrication and integrated circuit (IC) design, make various integrated circuits be widely used in many electronic products with difference in functionality, simultaneously, the wire spoke size of semiconductor element has entered time field of micron (Sub-Micro) even deep-sub-micrometer (Deep Sub-Micro), and the integration of integrated circuit also increases fast.Because the surface of semiconductor structure can't provide enough areas to make the required intraconnections of semiconductor element (Interconnection), so develop the technology that multi-metal intra-connection (Multilevel Interconnection), utilize several layers of metal level and dielectric layer to carry out the line between semiconductor element and the work of isolation, and power supply has just constituted the electric power network of integrated circuit to the metal connecting line of semiconductor element.
In the integrated circuit in deep-sub-micrometer field, the processing of signal and transmission often are subjected to the interference of many noises, for example leakage current noise, cross-talk noise (Crosstalk Noise), reflection noise (ReflectionNoise) and power supply are supplied noise (Power Supply Noise) etc., wherein when the frequency of operation of integrated circuit is more and more higher, the interference of power supply supply noise just gets over seriously, so need carry out the analysis of electric power network.
When analyzing the efficient of electric power network, what should be noted that mainly is electron transfer (Electromigration) and voltage drop (Voltage Drop).When the current density of the conductive metal wire of flowing through is too high, the phenomenon of migration will take place in the atom in the metal wire, make in the wafer the metal wire accelerated ageing and lost efficacy.
And operate in order to allow in the wafer semiconductor element of each position all can obtain enough voltage, need avoid occurring in the wafer excessive voltage drop.In other words, if produce very large voltage drop when some semiconductor element operates in the wafer, then other semiconductor elements (particularly being positioned at center wafer semiconductor element partly) are just failed to obtain enough voltage and are operated in the wafer, the usefulness of integrated circuit thereby decline, even wrong running appears.
Along with the frequency of operation of integrated circuit significantly improves, the switch speed of semiconductor element also promotes simultaneously in the wafer, because the moment electricity variation when semiconductor element carries out the state switching will cause abrupt voltage wave, this fluctuation meeting causes the pressure drop of moment to the bias voltage of whole power plane, and forms noise between power supply and ground connection.Along with the increase of frequency of operation, transmission speed and the density of electronic circuit, noise also improves widely, and then the system that seriously has influence on works normally, and causes misoperation.
In above-mentioned background of invention, progress along with semiconductor fabrication and integrated circuit (IC) design, the frequency of operation of integrated circuit is more and more higher, the area of wafer is simultaneously also increasing, so the pressure drop that the semiconductor element in the integrated circuit is caused when operation is increasing, the high frequency of operation of semiconductor element also causes serious methd of power supply random signal simultaneously, disturbs and polluted normal circuit to operate signal and power supply supply, influences the operational effectiveness of integrated circuit and the correctness that signal is handled.
Summary of the invention
Main purpose of the present invention is for analytical method that a kind of methd of power supply random signal is provided and reduction method thereof, when the integrated circuit (IC) design process, be defined as by the plurality of cells square by electric power network and form integrated circuit layout (Layout), and according to the element that is electrically connected to each unit square, as logic element, as the logical circuit of construction clock pulse tree (Clock Tree) and clock pulse transmission (as D type flip-flop; D-Flip-Flop) and parameter such as the quantity of pluse buffer etc. and type, estimate each unit square caused voltage drop and methd of power supply random signal when running, just appropriate location that can be in integrated circuit layout, configuration is as the capacitor of compensated voltage drop, so as to reducing voltage disturbance and methd of power supply random signal.
For reaching above-mentioned purpose, the invention provides a kind of analytical method and reduction method thereof of methd of power supply random signal, at first be to utilize CAD (computer aided design) (Computer Aided Design) software, relevant design data to integrated circuit is carried out the wafer power analysis, so as to obtaining electric power network model through integrated circuit (IC) design, then this electric power network model definition is constituted for being interlinked by the plurality of cells square, behind the related data of analysing integrated circuits design, can learn parameters such as the quantity of the element that is electrically connected to each unit square and type, with this element reference as the unit square, follow element reference according to each unit square, utilization is electrically connected to the equivalent electric circuit of the element formation of unit square, borrow circuit simulation software to estimate the caused pressure drop when operation of each unit square, just can learn the distribution situation and the voltage consumption amount of the voltage that each zone consumed in the electric power network model, in view of the above at the appropriate location of electric power network model configuration decoupling capacitance, with the caused pressure drop when operating of element in the adequate compensation integrated circuit, thereby reduce the interior methd of power supply random signal of integrated circuit.
In more detail, the invention provides a kind of analytical method of methd of power supply random signal, is to be applied in the integrated circuit (IC) design, and the analytical method of this methd of power supply random signal comprises at least:
One electric power network model of this integrated circuit (IC) design is provided;
Define this electric power network model for to form according to a preordering method by a plurality of unit square;
Contain area according to each unit square in a position and of this electric power network model, acquisition is electrically connected to the plurality of data of a plurality of elements of each unit square, and with the reference of these data as each unit square; And
According to these references of these unit squares, carry out a transactional analysis step, to obtain a transactional analysis result of this electric power network model.
The analytical method of described methd of power supply random signal, wherein above-mentioned transactional analysis result comprise power that each unit square is consumed and the voltage drop that causes at least when operation.
The analytical method of described methd of power supply random signal wherein more comprises this integrated circuit (IC) design is carried out an electric power network analytical procedure, so as to obtaining this electric power network model of this integrated circuit (IC) design.
The analytical method of described methd of power supply random signal, wherein above-mentioned electric power network model include a direct current electric power network model data and AC power network model data of this integrated circuit (IC) design.
The analytical method of described methd of power supply random signal, wherein above-mentioned preordering method is for being a plurality of rectangles by a plurality of metal wires that constitute this electric power network model with the unit square that defines this electric power network model, wherein those rectangles are made of those metal wires.
The analytical method of described methd of power supply random signal, wherein those elements include a plurality of logic elements, a plurality of sequential buffer and a plurality of parasitic antenna at least.
The analytical method of described methd of power supply random signal, wherein those parasitic antennas comprise a plurality of parasitic decoupling capacitances at least.
The analytical method of described methd of power supply random signal wherein behind the transactional analysis result who obtains this electric power network model, more comprises according to the transactional analysis result, in a plurality of decoupling capacitances of a plurality of position configuration of integrated circuit (IC) design.
The invention provides a kind of reduction method of methd of power supply random signal, is to be applied in the integrated circuit (IC) design, and the reduction method of this methd of power supply random signal comprises at least:
One electric power network model of this integrated circuit (IC) design is provided;
According to preordering method definition electric power network model is to be made up of a plurality of unit square;
Contain area according to each unit square in a position and of this electric power network model, acquisition is electrically connected to the plurality of data of a plurality of elements of each unit square, and with the reference of these data as each unit square;
According to these references of these unit squares, carry out a transactional analysis step, to obtain a transactional analysis result of this electric power network model; And
According to the transactional analysis result, in a plurality of decoupling capacitances of a plurality of position configuration of integrated circuit (IC) design.
The reduction method of described methd of power supply random signal, wherein above-mentioned transactional analysis result comprise power that each unit square is consumed and the voltage drop that causes at least when operation.
The reduction method of described methd of power supply random signal wherein more comprises this integrated circuit (IC) design is carried out an electric power network analytical procedure, so as to obtaining this electric power network model of integrated circuit (IC) design.
The reduction method of described methd of power supply random signal, wherein above-mentioned electric power network model include a direct current electric power network model data and AC power network model data of this integrated circuit (IC) design.
The reduction method of described methd of power supply random signal, wherein above-mentioned preordering method is for being a plurality of rectangles by a plurality of metal wires that constitute this electric power network model with the unit square that defines this electric power network model, wherein these rectangles are made of these metal wires.
The reduction method of described methd of power supply random signal, wherein those elements include a plurality of logic elements, a plurality of sequential buffer and a plurality of parasitic antenna at least.
The reduction method of described methd of power supply random signal, wherein those parasitic antennas comprise a plurality of parasitic decoupling capacitances at least.
Description of drawings
Fig. 1 is the handling process schematic diagram of one of the present invention embodiment;
Fig. 2 is according to Fig. 1, the schematic top plan view of the electric power network model when the integrated circuit (IC) design process after the process definition;
Fig. 3 is in the electric power network model of Fig. 2, the annexation schematic diagram of each element in the unit square.
Embodiment
Please refer to Fig. 1, its illustrate is the handling process schematic diagram of one of the present invention embodiment.As shown in Figure 1, in order to obtain the electric power network model of integrated circuit (IC) design earlier, so analyze in 30 at the electric power network of handling process 10, the relevant design reference 20 of elder generation's input ic design, utilize CAD software, carry out wafer power analysis (Chip Power Analysis), so as to obtaining the electric power network model of integrated circuit (IC) design, the electric power network model of integrated circuit (IC) design in view of the above, can obtain characterisitic parameter and data relevant for the DC power supply network model and the AC power network model of integrated circuit (IC) design, the reference of wherein relevant integrated circuit (IC) design, generally comprised: the standard component data bank, the electric power network impedance, frequency of operation, operating temperature range, temperature coefficient, the pressure drop scope, and relevant for the length and width of each metal wire in the electric power network metal level, the unit are resistance of metal wire and metal wire relevant parameter and data such as distance each other.
Please refer to Fig. 2, its illustrate is into according to the 1st figure, the schematic top plan view of the electric power network model when the integrated circuit (IC) design process after the process definition, wherein electric power network model 100 is to be made of metal level 120 and metal level 130, and metal level 120 and metal level 130 include numerous metal wires 140 and metal wire 150 respectively, and 110 forms with equivalent electric circuit of each unit square are connected to each other.Simulate for convenience and estimate that huge electric power network model 100 is in the normality situation and the transient state situation in when running, so behind the electric power network model 100 that obtains integrated circuit (IC) design, carry out the definition unit square and the component analysis 40 of handling process 10, area according to electric power network model 100, and constitute metal wire in each metal level of this electric power network model 100, electric power network model 100 is defined as to be interlinked by plurality of cells square 110 forms, wherein the type of the element that is comprised in each unit square 110 and quantity etc. are the designs according to integrated circuit, layout and position and the covering scope of each unit square 110 in electric power network model 100 places decide.Therefore, see through the step of definition unit square, reach more fast accurately during the electric power network model that can make the analysing integrated circuits design.
For example, as shown in Figure 2, if electric power network model 100 is to be made of metal level 120 and metal level 130, then can define each unit square 110 to electric power network model 100 is to utilize two metal line 140 and two metal line 150 the center on rectangular blocks forming at metal level 130 of position at metal level 120.
Please refer to Fig. 3, its illustrate is in the electric power network model of Fig. 2, the annexation schematic diagram of each element in the unit square.In the unit square 110 shown in Figure 3, many logic elements have been comprised, as the logical circuit of construction clock pulse tree and clock pulse transmission and pluse buffer etc., for example comprised two logic elements-D type flip-flop (D-Flip Flop) (D type flip-flop 160 and D type flip-flop 170), two sequential buffers (sequential buffer 180 and sequential buffer 190), and other parasitic antenna 200, as parasitic decoupling capacitance on the wafer (On-chip Parasitic DecouplingCapacitance) etc., but it is shown in Figure 3 that number of elements in the unit square 110 and type etc. are not restricted to, but decide on design.
Then, in order to carry out transactional analysis to being defined as the electric power network model of forming by plurality of cells square 110 100, so as to learning the voltage drop that circuit produced of each position in each unit square 110 corresponding wafers, so need carry out transient analysis (Transient Analysis) or transactional analysis to element, utilize the data of relevant various elements in the reference element data bank, each unit square 110 in the electric power network model 100 of Fig. 2 is analyzed, so as to knowing the type of the element that is electrically connected to each unit square 110, quantity, operating parameters, geometric parameter and other related datas.
For example, data according to relevant various elements in the reference element data bank, unit square 110 to Fig. 3 carries out component analysis, can learn that the element that is electrically connected to unit square 110 includes a plurality of logic elements (as two D type flip-flops), two sequential buffers and other parasitic antenna, wherein D type flip-flop 160 is the D type flip-flop of the first kind, D type flip-flop 170 is the D type flip-flop of second type, and sequential buffer 180 is the sequential buffers that belong to the category-A type, 190 in sequential buffer is the sequential buffer that belongs to the category-B type, and other parasitic antenna 200 includes wafer endoparasitism electric capacity etc., these elements all are to be connected between metal wire 210 (for the metal wire of supply operating power) and the metal wire 220 (for the metal wire of ground connection or virtual ground) in the equivalent electric circuit of unit square 110.In addition, still need and consider the resistance 240 and the resistance 250 of metal wire 210 and metal wire 220, and be electrically connected to the input of the element of unit square 110/the go out related datas such as connection of end, related datas such as output as the output of the input of the sequential of logic element, logic element and input, sequential buffer, just can obtain to be electrically connected to the complete reference data of each element of unit square 110, and with this element reference as unit square 110.
Then, just can be according to the element reference that contains each unit square 110, utilize breadboardin and analysis software such as Hspice, electric power network model 100 to integrated circuit carries out transactional analysis 50, to estimate power that the element that is electrically connected to each unit square 110 consumed and the pressure drop that causes when transient state is operated, so as to learning power that each unit square 110 is consumed in the electric power network model 100 and the pressure drop that causes, at last, the power supply attenuation distribution situation in the time of just can obtaining power supply and be supplied to each position of integrated circuit on the wafer.
Yet, because integrate circuit function now is powerful day by day, need to adopt many elements or semiconductor element to constitute, therefore, the quantity of element that is electrically connected to each unit square 110 is very huge, if will be electrically connected to the related data of whole elements of each unit square 110, all drop into and carry out the transactional analysis 50 of electric power network model 100, then spent time and system resource etc. are with considerable, thereby significantly increase the design cost of integrated circuit, also make the cost of product rise, so before the transactional analysis of carrying out electric power network model 100, can carry out the Screening Treatment 70 of the handling process 10 of Fig. 1 earlier.
So-called Screening Treatment 70, be according in the element reference of unit square 110 about type, quantity, operating parameters, geometric parameter and other related datas of each element, assess the influence of power that each element consumed unit square 110 and the pressure drop that causes, to reject the little element of the influence of consumed power and the pressure drop that causes, so as to reducing the data of the transactional analysis that participates in electric power network model 100, reduce and analyze required time and system resource, the transactional analysis result's of electric power network model 100 accuracy can't be seriously influenced simultaneously.
For example, in the Screening Treatment 70 of the handling process 10 of Fig. 1, the analysis of methd of power supply random signal of the present invention and reduction method provide two kinds of default screening steps (screening step 80 and screening step 90), so as to explaining related setting and running, right this usefulness does not for illustrative purposes only limit the implementation method of Screening Treatment 70 or the quantity of screening step.
The screening scope of these two kinds default screening steps is also inequality, can do suitably to adjust or revise according to the element of different integrated circuit (IC) design and employing, reduce to analyze required time and system resource to reach, can not have a strong impact on the transactional analysis result's of electric power network model 100 the purpose of accuracy simultaneously again.For example, the unit square 110 of Fig. 3 includes the D type flip-flop 160 of a first kind and the D type flip-flop 170 of one second type, when analyzing and relatively D type flip-flop 160 and D type flip-flop 170 are in operation separately after institute's consumed power and the voltage drop that causes, learn the consumed power of the first kind D type flip-flop 160 in the operation and the voltage drop that causes, much larger than the consumed power of the second type D type flip-flop 170 and the voltage drop that causes, therefore when the consumed power of the unit square 110 in the estimation operation and the voltage drop that causes, the element data of the D type flip-flop 170 of relevant this second type then can not need participate in computing, to reduce the spent time of estimation.And, according to the design of integrated circuit, the related data that adopts element and transactional analysis predetermined data such as expend time in, can set screening step 80 in the element reference of a selected cell square 110, the related data of the D type flip-flop 160 of the relevant first kind participates in the transactional analysis 50 of electric power network model 100, and the related data of other elements is then rejected in the element reference of unit square 110.Similarly, in other default screening steps, also can set with various relevant reference datas according to different design conditions, thereby reduce the data of the transactional analysis that participates in electric power network model 100, analyze required time and system resource so as to reaching to reduce, simultaneously, the transactional analysis result's of electric power network model 100 accuracy also can not decline to a great extent.
On the other hand, in above-mentioned example, only be to comprise the D type flip-flop 160 of a first kind in the unit square 110, the D type flip-flop 170 of one second type, an A type sequential buffer 180 and a Type B sequential buffer 190 are example, if a certain unit square is the D type flip-flop 160 that includes a plurality of first kind, the D type flip-flop 170 of a plurality of second types, and during other different elements, then need these D type flip-flops 160, D type flip-flop 170 and other elements carry out labor in operation time institute's consumed power and the voltage drop that causes, just can determine to adopt the related data of which element to participate in the transactional analysis of electric power network model 100.Otherwise the transactional analysis result's of the electric power network model 100 after the estimation accuracy will decline to a great extent.In addition, because the type of the element that each unit square comprised and quantity etc., be to decide on the design and the layout of integrated circuit, so before setting screening step 80 or screening step 90, data information when the type of element, quantity, the data information when normality operates and transient state operate in essential each unit square of labor etc., just can accurately set suitable screening step,, keep the result's of transactional analysis 50 pin-point accuracy simultaneously again so as to promoting the execution speed of transactional analysis 50.
On the other hand, if desire obtains the transactional analysis result of the electric power network model 100 of high accuracy, then can omit Screening Treatment 70, directly according to the element reference that contains each unit square, utilize breadboardin and analysis software such as Hspice, the electric power network model 100 of integrated circuit is carried out transactional analysis 50.
After the electric power network model 100 of integrated circuit carries out transactional analysis 50, just can obtain the transactional analysis result of electric power network model 100, the designer just can learn via the transactional analysis result, power that each unit square 110 is consumed when operation in the electric power network model 100 and the voltage drop that causes just can be optimized and revised accordingly to integrated circuit (IC) design.
In addition, because the element caused voltage drop when state switches in the integrated circuit, particularly caused voltage drop when the state of high-frequency operation switches can be polluted the power supply supply and be formed methd of power supply random signal, disturb the processing of signal.Therefore, the transactional analysis result of visual electric power network model 100, according to the design code of integrated circuit, the data such as (Loop-up Table) and Cell Library of tabling look-up, carry out the configuration decoupling capacitance 60 of the handling process 10 of Fig. 1, decoupling capacitance in the appropriate location of integrated circuit (IC) design configuration some, so as to reducing the disturbance situation of voltage, compensating element, is caused voltage drop when state switches, reduce the noise that is produced when element changes state, to keep the accurate position of stable power.For example, can add the unit square 110 that suitable decoupling capacitance 230 is electrically connected to Fig. 3, to reduce the disturbance situation of voltage.
And, behind the appropriate location of integrated circuit (IC) design configuration decoupling capacitance, still can utilize breadboardin and analysis software that integrated circuit (IC) design is carried out transactional analysis 50 once more, so as to the consumption and the distribution situation of the electric power network model 100 of learning integrated circuit (IC) design power behind the configuration decoupling capacitance.
Analytical method and the reduction method thereof of advantage of the present invention for a kind of methd of power supply random signal is provided, by With the electric power network model definition of IC design for to be formed by the plurality of cells square, then according to electricity The type, quantity, operating parameters, geometric parameter that property is connected to the element of each unit square with other mutually Close data, utilize breadboardin and analysis software, the electric power network model of IC design is carried out Transactional analysis, with the consumed power that obtains relevant unit square and the voltage drop that causes, just can The decoupling capacitance of the appropriate location configuration some of IC design is so as to reducing element at shape Caused voltage drop and methd of power supply random signal when attitude is switched are kept the accurate position of stable power supply.
Claims (15)
1. the analytical method of a methd of power supply random signal is to be applied in the integrated circuit (IC) design, it is characterized in that the analytical method of this methd of power supply random signal comprises at least:
One electric power network model of this integrated circuit (IC) design is provided;
Define this electric power network model for to form according to a preordering method by a plurality of unit square;
Contain area according to each unit square in a position and of this electric power network model, acquisition is electrically connected to the plurality of data of a plurality of elements of each unit square, and with the reference of these data as each unit square; And
According to these references of these unit squares, carry out a transactional analysis step, to obtain a transactional analysis result of this electric power network model.
2. the analytical method of methd of power supply random signal as claimed in claim 1 is characterized in that, described transactional analysis result comprises power that each unit square is consumed and the voltage drop that causes at least when operation.
3. the analytical method of methd of power supply random signal as claimed in claim 1 is characterized in that, wherein more comprises this integrated circuit (IC) design is carried out an electric power network analytical procedure, so as to obtaining this electric power network model of this integrated circuit (IC) design.
4. the analytical method of methd of power supply random signal as claimed in claim 1 is characterized in that, described electric power network model includes a direct current electric power network model data and AC power network model data of this integrated circuit (IC) design.
5. the analytical method of methd of power supply random signal as claimed in claim 1, it is characterized in that, described preordering method is for being a plurality of rectangles by a plurality of metal wires that constitute this electric power network model with the unit square that defines this electric power network model, and wherein those rectangles are made of those metal wires.
6. the analytical method of methd of power supply random signal as claimed in claim 1 is characterized in that, wherein those elements include a plurality of logic elements, a plurality of sequential buffer and a plurality of parasitic antenna at least.
7. the analytical method of methd of power supply random signal as claimed in claim 6 is characterized in that, wherein those parasitic antennas comprise a plurality of parasitic decoupling capacitances at least.
8. the analytical method of methd of power supply random signal as claimed in claim 1, it is characterized in that, wherein behind the transactional analysis result who obtains this electric power network model, more comprise according to the transactional analysis result, in a plurality of decoupling capacitances of a plurality of position configuration of integrated circuit (IC) design.
9. the reduction method of a methd of power supply random signal is to be applied in the integrated circuit (IC) design, it is characterized in that, the reduction method of this methd of power supply random signal comprises at least:
One electric power network model of this integrated circuit (IC) design is provided;
According to preordering method definition electric power network model is to be made up of a plurality of unit square;
Contain area according to each unit square in a position and of this electric power network model, acquisition is electrically connected to the plurality of data of a plurality of elements of each unit square, and with the reference of these data as each unit square;
According to these references of these unit squares, carry out a transactional analysis step, to obtain a transactional analysis result of this electric power network model; And
According to the transactional analysis result, in a plurality of decoupling capacitances of a plurality of position configuration of integrated circuit (IC) design.
10. the reduction method of methd of power supply random signal as claimed in claim 9 is characterized in that, described transactional analysis result comprises power that each unit square is consumed and the voltage drop that causes at least when operation.
11. the reduction method of methd of power supply random signal as claimed in claim 9 is characterized in that, wherein more comprises this integrated circuit (IC) design is carried out an electric power network analytical procedure, so as to obtaining this electric power network model of integrated circuit (IC) design.
12. the reduction method of methd of power supply random signal as claimed in claim 9 is characterized in that, described electric power network model includes a direct current electric power network model data and AC power network model data of this integrated circuit (IC) design.
13. the reduction method of methd of power supply random signal as claimed in claim 9, it is characterized in that, described preordering method is for being a plurality of rectangles by a plurality of metal wires that constitute this electric power network model with the unit square that defines this electric power network model, and wherein these rectangles are made of these metal wires.
14. the reduction method of methd of power supply random signal as claimed in claim 9 is characterized in that, wherein those elements include a plurality of logic elements, a plurality of sequential buffer and a plurality of parasitic antenna at least.
15. the reduction method of methd of power supply random signal as claimed in claim 14 is characterized in that, wherein those parasitic antennas comprise a plurality of parasitic decoupling capacitances at least.
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| CNB021304726A CN1294642C (en) | 2002-08-21 | 2002-08-21 | Analysis methd of power supply random signal and its reducing method |
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Cited By (4)
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| US9183345B2 (en) | 2014-01-14 | 2015-11-10 | Industrial Technology Research Institute | Apparatus and method for generating a power delivery network |
| CN105447242A (en) * | 2015-11-17 | 2016-03-30 | 西安华芯半导体有限公司 | Method for analyzing state of power supply network of integrated circuit in real time |
| CN108089624A (en) * | 2016-11-21 | 2018-05-29 | 龙芯中科技术有限公司 | The compensation method of chip internal dynamic pressure drop and device |
| CN111796199A (en) * | 2020-07-30 | 2020-10-20 | 上海兆芯集成电路有限公司 | Power supply network uniformity and power consumption testing method |
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| JP3584693B2 (en) * | 1996-09-18 | 2004-11-04 | 株式会社デンソー | Semiconductor integrated circuit |
| JPH10107235A (en) * | 1996-09-27 | 1998-04-24 | Hitachi Ltd | Method for constituting gate array lsi and circuit device using the same |
| US5942951A (en) * | 1997-03-11 | 1999-08-24 | Stmicroelectronics, Inc. | Method and apparatus for reducing a noise differential in an electronic circuit |
| JP3450739B2 (en) * | 1999-03-24 | 2003-09-29 | 松下電器産業株式会社 | LSI placement method |
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| US9183345B2 (en) | 2014-01-14 | 2015-11-10 | Industrial Technology Research Institute | Apparatus and method for generating a power delivery network |
| CN105447242A (en) * | 2015-11-17 | 2016-03-30 | 西安华芯半导体有限公司 | Method for analyzing state of power supply network of integrated circuit in real time |
| CN105447242B (en) * | 2015-11-17 | 2019-01-15 | 西安紫光国芯半导体有限公司 | A kind of method of real-time analysing integrated circuits electric power network state |
| CN108089624A (en) * | 2016-11-21 | 2018-05-29 | 龙芯中科技术有限公司 | The compensation method of chip internal dynamic pressure drop and device |
| CN108089624B (en) * | 2016-11-21 | 2020-04-07 | 龙芯中科技术有限公司 | Method and device for compensating dynamic voltage drop inside chip |
| CN111796199A (en) * | 2020-07-30 | 2020-10-20 | 上海兆芯集成电路有限公司 | Power supply network uniformity and power consumption testing method |
| CN111796199B (en) * | 2020-07-30 | 2022-12-27 | 上海兆芯集成电路有限公司 | Power supply network uniformity and power consumption testing method |
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