CN1474449A - Operation method of silion nitride read-only memory element - Google Patents
Operation method of silion nitride read-only memory element Download PDFInfo
- Publication number
- CN1474449A CN1474449A CNA021282501A CN02128250A CN1474449A CN 1474449 A CN1474449 A CN 1474449A CN A021282501 A CNA021282501 A CN A021282501A CN 02128250 A CN02128250 A CN 02128250A CN 1474449 A CN1474449 A CN 1474449A
- Authority
- CN
- China
- Prior art keywords
- memory element
- sequencing
- nitride read
- silion
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
The user of silicon nitride read-only memory elements is that a heavy doping base is provided for surroundings of source electrode/drain electrode. When programming, a relative plus source bias-voltage or a relatively minus base bias-voltage are used for increasing base effect and reducing the electric current of channel hot electron injection program. Before erasing of array of silicon nitride read-only memory element, a pre-programming is applied for all memory units to prevent over erasion.
Description
Technical field
The invention relates to a kind of method of operation of read-only memory element, and be particularly to a kind of silion nitride read-only memory element method of operation of (nitride read only memory device is called for short NROMdevice).
Background technology
Present silion nitride read-only memory element is to utilize silicon oxide/silicon nitride/silicon oxide (ONO) stacking-type (Stacked) structure that composite bed constituted as charge immersing layer, and on silicon oxide/silicon nitride/silicon oxide (ONO) layer, grid is arranged, and the source/drain electrode that in substrate, has adjoins gate.Because the material of charge immersing layer is mainly silicon nitride, so this kind can electricity erase and but program read-only memory (electrically erasable programmable ROM) is also referred to as silicon nitride ROM (NROM).
Because silicon nitride layer has the effect of catching electric charge,, but concentrate on the regional area of silicon nitride layer so the electronics of injecting among the silicon nitride layer can't be uniformly distributed among the whole silicon nitride layer.Therefore, when the silion nitride read-only memory element sequencing, electronics only can store near the path partially ground above source electrode or the drain electrode.So,, can among single silicon nitride layer, have two groups of electronics, single group's electronics or not have electronics by changing the voltage that source/drain regions applies of grid and its both sides.Therefore, silicon nitride ROM can write four kinds of states among single memory cell, is the flash memory of two of a kind of single memory cells (1 cell, 2 bit).
Yet after semiconductor element constantly developed towards miniaturization, the grid live width also can be dwindled gradually, and causes silion nitride read-only memory element generation problem in operation, needs electric current greatly when for example carrying out programming operations; And particularly when erasing (erasing), because can inject electric hole (hole) near the path partially ground above source electrode or the drain electrode, especially through after repeatedly erasing, because a large amount of electric holes of accumulation above source electrode or drain electrode, so having serious electric leakage (leakage) with the electronics of the another one of same bit line of its use or character line takes place, particularly situation at high temperature is more serious, and Here it is so-called " (over-erase) excessively erases ".And after initial voltage (initial voltage) reduction or passage length (channel length) shortening, said circumstances equally can be more serious.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of method of operation of silion nitride read-only memory element, influence the electronics of adjacent another one with a large amount of electric hole that prevents accumulation above source electrode or drain electrode, and produce serious electric leakage.
A further object of the present invention provides a kind of method of operation of silion nitride read-only memory element, can avoid taking place excessively to erase.
Another object of the present invention provides a kind of method of operation of silion nitride read-only memory element, can reduce the electric current that injects (channel hot electron inection is called for short CHEI) sequencing as channel hot electron.
According to above-mentioned and other purpose, the present invention proposes a kind of method of operation of silion nitride read-only memory element, and being provides a tool heavily doped substrate around source/drain electrode.When the sequencing silicon nitride ROM, use the negative substrate bias (more negative substrate bias) of source electrode bias voltage (more positive source bias) or of a calibration, reduce the electric current that injects (CHEI) sequencing as channel hot electron so as to increasing substrate effect (body effect).In addition, before the nitride read-only storage array of erasing, also implement a pre-programming operations (pre-programming operation), become the state (written state) that writes, prevent from excessively to erase with all memory cell in the sequencing nitride read-only storage array.
The present invention is because provide a tool heavily doped substrate around source/drain electrode, to increase the usefulness of sequencing.And when sequencing, use the source electrode bias voltage of calibration or negative substrate bias, so as to increasing the substrate effect, so can reduce the electric current that injects (CHEI) sequencing as channel hot electron.In addition, therefore the present invention also implements a pre-programming operations before erasing, can avoid above the source/drain electrode a large amount of electric hole of accumulation to influence the electronics of adjacent another one, and produce serious electric leakage, and then prevent that silion nitride read-only memory element from taking place excessively to erase.
Description of drawings
Fig. 1 is the operating process block diagram according to the silion nitride read-only memory element of a preferred embodiment of the present invention.
10: a silion nitride read-only memory element is provided, wherein around source/drain electrode, provides a tool heavily doped substrate
20: increase the substrate effect
30: before erasing, implement pre-sequencing
210: the bias voltage that increases source electrode
220: the back bias voltage that increases substrate
Embodiment
Present embodiment mainly is with silion nitride read-only memory element (nitride read only memorydevice, be called for short NROM device) be example, and along with element constantly dwindles, make the mechanism of carrying out the silion nitride read-only memory element sequencing inject (channel hotelectron inection with channel hot electron, abbreviation CHEI) method is main, and its operating procedure as shown in Figure 1.
Fig. 1 is the operating process block diagram according to the silion nitride read-only memory element of a preferred embodiment of the present invention (NROM device).
Please refer to Fig. 1, in step 10, provide a silion nitride read-only memory element, wherein provide the heavily doped substrate of a tool (heavily dopingsubstrate) on every side in source/drain electrode (source/drain).Because one of purpose of the present invention is to reduce the sequencing electric current, and the sequencing electric current reduces the usefulness (programming efficiency) that can influence sequencing.Therefore, need make source/drain electrode substrate on every side is heavily doped substrate; Just to increase n+ source/drain electrode substrate doping content (doping concentration) on every side, with the usefulness of increase sequencing, and the method for increase substrate doping content for example is to utilize memory cell ion implantation technology (cellimplantation) or pouch-type ion implantation technology (pocket implantation).
Then, in step 20, increase substrate effect (body effect).Because when injecting (CHEI) sequencing silion nitride read-only memory element by channel hot electron, increasing the substrate effect is the method that the required channel hot electron of a kind of effective reduction is injected (CHEI) sequencing electric current.For instance, the method that increases the substrate effect can be utilized the source electrode bias voltage (more positivesource bias) of a calibration, just as in the step 210, increases the bias voltage (Vs) of source electrode; Or utilize negative substrate bias (more negative substrate bias), as in the step 220, the back bias voltage of increase substrate (| V
B|).
Afterwards, in step 30, in the pre-sequencing of (erasing) preceding execution (pre-programming) of erasing, this is the problem of (over-erase) of erasing in order to eliminate excessively, and the electric hole of injecting with electronic compensation (injected hole).Therefore, before erasing, need all memory cell in the sequencing nitride read-only storage array (array) to become the state (written state) that writes.And the method for implementing pre-sequencing not only can be injected (CHEI) by channel hot electron, also can implement by F-N tunneling effect (F-N tunneling) or any other mechanism (mechanism) with the electronics injection mode.Table 1 item is the comparison between the method for operation of known method and silion nitride read-only memory element of the present invention.
| Known method | The present invention | |
| Memory cell initial voltage (volt) | 1.3 | ?2.5 |
| Sequencing Vg (volt) | 9～11 | ?6 |
| Sequencing Vd (volt) | 6 | ?6 |
| Sequencing Vs (volt) | 0 | ?1～2 |
| Sequencing electric current (μ A) | 350～400 | ?50～100 |
Table 1
As shown in Table 1, the present invention increases the bias voltage (Vs) of source electrode, then can obtain the sequencing electric current low than known method.In addition, table 2 item is the comparison sheet of the sequencing usefulness between the method for operation of known method and silion nitride read-only memory element of the present invention.
| Electric current | Number of Storage Units | Time | |
| Known | 500μA | ?4 | 2 μ seconds |
| The present invention | 100μA | ?20 | 3 μ seconds |
Table 2
Though the present invention needs the more time in operation, because of the Number of Storage Units that writes each time Number of Storage Units much larger than known write-once, so overall view it, the present invention still has more known high operating efficiency.
Therefore, feature of the present invention comprises:
1. the present invention is because the substrate around source/drain electrode has the doping content of increase, so when the sequencing electric current reduces, the usefulness of element sequencing is reduced.
2. the present invention is owing to source electrode bias voltage that uses calibration when the sequencing silion nitride read-only memory element or negative substrate bias, so as to increasing the substrate effect, so can reduce the electric current as channel hot electron injection (CHEI) sequencing.
3. the present invention is because before erasing, also implement a pre-programming operations, so that all memory cell in the element become the state that writes, the position that therefore can avoid being erased influences the electronics of adjacent another one through a large amount of electric hole of accumulating after repeatedly erasing, and produces serious electric leakage.
4. the present invention acts on the bias voltage of grid, source/drain electrode and substrate by change, increase the substrate effect, and before erasing, carry out pre-sequencing, thus can be under the trend of miniaturization of components development, prevent from simultaneously excessively to erase and improve element sequencing usefulness.
Figure of description
Claims (15)
1. the method for operation of a silion nitride read-only memory element, be suitable for operating a silion nitride read-only memory element, this silion nitride read-only memory element comprises one source pole, one drain electrode, an and substrate, wherein this substrate has a doping content that increases around this source electrode and this drain electrode, it is characterized in that the step of this method comprises:
Increase the substrate effect, inject (CHEI) sequencing electric current to reduce a required channel hot electron, wherein the bias voltage that acts on this grid, this source electrode, this drain electrode and this substrate by change increases the substrate effect; And
Before erasing, implement a pre-sequencing, come all memory cell in this silicon nitride memory element of sequencing to become the state that writes.
2. the method for operation of silion nitride read-only memory element as claimed in claim 1 is characterized in that, the step that increases the substrate effect comprises the source electrode bias voltage that utilizes a calibration.
3. the method for operation of silion nitride read-only memory element as claimed in claim 1 is characterized in that, the step that increases the substrate effect comprises utilizes negative substrate bias.
4. the method for operation of silion nitride read-only memory element as claimed in claim 1 is characterized in that, the method for implementing this pre-sequencing comprises channel hot electron injection (CHEI).
5. the method for operation of silion nitride read-only memory element as claimed in claim 1 is characterized in that, the method for implementing this pre-sequencing comprises the F-N tunneling effect.
6. the method for operation of silion nitride read-only memory element as claimed in claim 1 is characterized in that, the method for implementing this pre-sequencing comprises the mechanism with the electronics injection mode.
7. the method for operation of silion nitride read-only memory element as claimed in claim 1 is characterized in that, the method that forms the doping content of this increase comprise utilize memory cell ion implantation technology and pouch-type ion implantation technology one of them.
8. the method for operation of a silion nitride read-only memory element is suitable for operating a silion nitride read-only memory element, and this silion nitride read-only memory element comprises one source pole, it is characterized in that, the step of this method comprises:
Increase the substrate effect by the bias voltage that increases this source electrode, inject (CHEI) sequencing electric current to reduce a required channel hot electron; And
Before erasing, implement a pre-sequencing, come all memory cell in this silicon nitride memory element of sequencing to become the state that writes.
9. the method for operation of silion nitride read-only memory element as claimed in claim 8 is characterized in that, the method for implementing this pre-sequencing comprises channel hot electron injection (CHEI).
10. the method for operation of silion nitride read-only memory element as claimed in claim 8 is characterized in that, the method for implementing this pre-sequencing comprises the F-N tunneling effect.
11. the method for operation of silion nitride read-only memory element as claimed in claim 8 is characterized in that, the method for implementing this pre-sequencing comprises the mechanism with the electronics injection mode.
12. the method for operation of a silion nitride read-only memory element is suitable for operating a silion nitride read-only memory element, this silion nitride read-only memory element comprises a substrate, it is characterized in that, the step of this method comprises:
Increase the substrate effect by the back bias voltage that increases this substrate, inject (CHEI) sequencing electric current to reduce a required channel hot electron; And
Before erasing, implement a pre-sequencing, come all memory cell in this silicon nitride memory element of sequencing to become the state that writes.
13. the method for operation of silion nitride read-only memory element as claimed in claim 12 is characterized in that, the method for implementing this pre-sequencing comprises channel hot electron injection (CHEI).
14. the method for operation of silion nitride read-only memory element as claimed in claim 12 is characterized in that, the method for implementing this pre-sequencing comprises the F-N tunneling effect.
15. the method for operation of silion nitride read-only memory element as claimed in claim 12 is characterized in that, the method for implementing this pre-sequencing comprises the mechanism with the electronics injection mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021282501A CN100397621C (en) | 2002-08-06 | 2002-08-06 | Operation method of silion nitride read-only memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021282501A CN100397621C (en) | 2002-08-06 | 2002-08-06 | Operation method of silion nitride read-only memory element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1474449A true CN1474449A (en) | 2004-02-11 |
| CN100397621C CN100397621C (en) | 2008-06-25 |
Family
ID=34143657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021282501A Expired - Lifetime CN100397621C (en) | 2002-08-06 | 2002-08-06 | Operation method of silion nitride read-only memory element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100397621C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100383955C (en) * | 2005-06-03 | 2008-04-23 | 旺宏电子股份有限公司 | Method for dynamic adjusting operation of memory chip, and device for measuring thickness of 0N0 layer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5617357A (en) * | 1995-04-07 | 1997-04-01 | Advanced Micro Devices, Inc. | Flash EEPROM memory with improved discharge speed using substrate bias and method therefor |
| US6185133B1 (en) * | 1998-06-26 | 2001-02-06 | Amic Technology, Inc. | Flash EPROM using junction hot hole injection for erase |
| US6492231B2 (en) * | 2000-06-09 | 2002-12-10 | Winbond Electronics Corporation | Method of making triple self-aligned split-gate non-volatile memory device |
-
2002
- 2002-08-06 CN CNB021282501A patent/CN100397621C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100383955C (en) * | 2005-06-03 | 2008-04-23 | 旺宏电子股份有限公司 | Method for dynamic adjusting operation of memory chip, and device for measuring thickness of 0N0 layer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100397621C (en) | 2008-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6445617B1 (en) | Non-volatile semiconductor memory and methods of driving, operating, and manufacturing this memory | |
| CN100538897C (en) | The algorithm of dynamic reference programming | |
| KR0184024B1 (en) | Semiconductor device having a multi-layer channel structure | |
| KR100211187B1 (en) | Non-volatile semiconductor memory device | |
| US6671209B2 (en) | Erasing method for p-channel NROM | |
| US6563741B2 (en) | Flash memory device and method of erasing | |
| US7492636B2 (en) | Methods for conducting double-side-biasing operations of NAND memory arrays | |
| WO2005083797A1 (en) | Multi-state memory cell with asymmetric charge trapping | |
| US20020190385A1 (en) | Silicon nitride read only memory structure and method of programming and erasure | |
| US5576991A (en) | Multistepped threshold convergence for a flash memory array | |
| JP4414126B2 (en) | A method for erasing a nonvolatile memory device. | |
| US20030223288A1 (en) | Non-volatile memory device | |
| KR100660864B1 (en) | Method of operating Silicon Oxide Nitride Oxide Semiconductor memory device | |
| KR100558004B1 (en) | Programing method of a non-volatile memory device including a charge storage layer between a gate electrode and a semiconductor substrate | |
| JP2005216471A (en) | Nonvolatile memory cell array having common drain line and method of operating the same | |
| JP2006252670A (en) | Method for driving nonvolatile memory and nonvolatile memory used therefor | |
| JP4602331B2 (en) | Programming memory with individual charge storage elements | |
| EP1555674B1 (en) | Nonvolatile memory cell and operating method | |
| CN1407614A (en) | Operation of programmed and erasing P-channel SONOS memory unit | |
| JPH04105368A (en) | Nonvolatile semiconductor storage device | |
| US6501681B1 (en) | Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in sonos non-volatile memories | |
| US7209385B1 (en) | Array structure for assisted-charge memory devices | |
| US7561470B2 (en) | Double-side-bias methods of programming and erasing a virtual ground array memory | |
| KR100217900B1 (en) | Programming method of a flash memory cell | |
| CN113437084B (en) | Erasing method of flash memory unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20080625 |
|
| CX01 | Expiry of patent term |