CN1407614A - Operation of programmed and erasing P-channel SONOS memory unit - Google Patents
Operation of programmed and erasing P-channel SONOS memory unit Download PDFInfo
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- CN1407614A CN1407614A CN 01130730 CN01130730A CN1407614A CN 1407614 A CN1407614 A CN 1407614A CN 01130730 CN01130730 CN 01130730 CN 01130730 A CN01130730 A CN 01130730A CN 1407614 A CN1407614 A CN 1407614A
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Abstract
An operation method for programing and erasing SONOS memory unit in P channel is disclosed herewith. The memory unit has a charge catching layer on a substrate, a grid layer on the charge catch layer and two dosed regions at the both sides of the substrate, one as the drain and another as the source. When programing, the first negative bias is applied between the drain and the source meanwhile the source and the substrate is grounded. When erasing, the second negative bias is applied to the grid, the third negative bias is applied to the drain meanwhile the substrate is grounded. Additionally, the absolute value of the third magnetic bias is larger than that of the second one.
Description
Technical field
The invention relates to the method for operation of semiconductor element, particularly relevant for a kind of sequencing and erase and have silicon-silicon oxide/silicon nitride/silicon oxide-method of the P channel silicon nitride ROM (P-channel NROM) of silicon (SONOS) structure, this P channel NROM has two bits in a mnemon.
Background technology
The non-voltile memory element of storage data is widely used at present and has many different purposes, and for instance, when the function of microprocessor is more and more powerful, its usually needs software program the more finish these functions.Therefore, it needs many internal memories to store all these programs and relevant information.
For increasing memory size, the size of memory element is dwindled greatly.Yet for known internal storage structure, each mnemon only can store the data of a bit.
Recently, a kind of internal storage structure occurs, the read-only memory (SONOS ROM) of so-called N channel substrate-silicon oxide/silicon nitride/silicon oxide-silicon is also referred to as N channel NROM, wherein the silicon oxide/silicon nitride/silicon oxide layer is as an electric charge capture layer, to store two Bit datas.N channel SONOSROM can make a mnemon have two bits when writing data, but these data can not be that unit is erased with single bit.Fig. 1 has narrated a kind of known N channel NROM and has write the method for data.
See also Fig. 1, form silicon monoxide/nitrogenize silicon/oxidative silicon (ONO) layer 110 in substrate 100, wherein ONO layer 110 is caught layer as one, wherein comprises one silica layer 104, a silicon nitride layer 106 and another silicon oxide layer 108.The both sides of catching layer 110 in substrate 100 form two N type doped region 102a and 102b.The polysilicon gate layer 112 that forms N doping is being caught on the layer 110.The mnemon of this structure has I-V curve as shown in Figure 2.When one 9 volts bias voltages (bias) when being applied to grid layer 112, will have hot electron and produce.
Mnemon as shown in Figure 1, when wanting sequencing or erase data, can be by setting suitable Vd, Vg, Vs and V
BBias voltage and realize.Doped region 102b is set to source area if doped region 102a is set to the drain region, and the relation that its sequencing is erased between (P/E) operation and bias voltage can be as shown in table 1.
Table 1
| ????Vg | ????Vd | ????Vs | ????V B | |
| Sequencing | ????9V | ????9V | ????0V | ????0V |
| Erase | ????0V | ????9V | (floating) floats | ????0V |
Be set at Vg=Vd=9V and Vs=V when bias voltage
BDuring=0V, then can produce hot electron, be trapped in the zone of close drain region 102a in the silicon nitride layer 106 then, part shown in shadow region 114.When data will be erased, promptly hot electron should be removed, its common utilization can bring to the hot carrier mechanism (hot carrier mechanism) that can be with (band to band) and carry out.Grid 112 and substrate 100 ground connection, and drain region 102a applies the bias voltage of a 9V, source area 102b then is set at and floats.In this way, then can produce hot hole and it is driven in the ONO layer 110, hot electron is wherein disappeared.Yet in the process of erasing, the electronics that is stored in the contiguous mnemon will be affected.This will cause data in the operation of erasing by whole erasing.In other words the single bit of can erasing of having no idea, can not have the operation of single bit in the process of erasing.
On the contrary, if doped region 102a as source area and doped region 102b as the drain region, one side promptly can be at other another bit that deposits in of silicon nitride layer 106, this will make has two bits in the mnemon.Yet in the operation of erasing, data also are to be erased in whole block ground.
The P channel NROM similar to N channel NROM, its dopant profile is different.Known method of operation is to write or reading of data with FN tunnelling (Fowler-Nordheim tunneling) mechanism.The electronics that produces because of FN tunnelling mechanism is not what localize, and can flow in the whole mnemon, so only can store a bit in the one mnemon.
In aforesaid NROM element, known P/E feature operation can not be reached single completely bit operating.
Summary of the invention
Therefore, the invention reside in the method for operation that a kind of P channel SONOS memory element is provided, and the operation that can reach single bit.
As embodiment and described herein, the invention provides a kind of method at the enterprising line programization of P channel SONOS memory element/erase operation for use.The method step is as follows: a P channel SONOS memory element is provided, and this element has that an electric charge capture layer is arranged in the substrate, a grid is positioned on this electric charge capture layer, two doped regions are positioned at and catch a layer substrate on two sides.When a doped region is set as the drain region, then another doped region then is used as source area.In the time will carrying out the sequencing action, grid and drain region are applied first back bias voltage, and with source area and substrate ground connection, wherein first back bias voltage is enough to make hot hole generation and iunjected charge to be caught in the layer.When will erasing action, then grid is applied one second back bias voltage, simultaneously the drain region is applied the 3rd back bias voltage, and with substrate ground connection, wherein the absolute value of the 3rd back bias voltage is greater than the absolute value of second back bias voltage, and the difference of the two is enough to make hot electron to produce and iunjected charge is caught in the layer.
In aforesaid method, can the repetitive operation program and source area and drain region exchanged, in identical mnemon, to carry out writing/erase operation for use of another bit.
Description of drawings
Fig. 1 is the generalized section of N channel NROM structure.
Fig. 2 is the grid current-voltage curve (Ig-Vgcurve) in N channel NROM when operation of Fig. 1.
Fig. 3 is the generalized section according to the P channel NROM structure that has two bit memory functions in one embodiment of the invention.
Grid current-voltage curve (Ig-Vg curve) when Fig. 4 is its operation of P channel SONOS memory element shown in Figure 3 is to get according to the embodiment of the invention.
Description of reference numerals:
100,200: substrate
102a, 102b, 202a, 202b: source electrode
104,204: silicon oxide layer
106,206: silicon nitride layer
108,208: silicon oxide layer
110,210: silicon oxide/silicon nitride/silicon oxide (ONO) layer
112,212: grid layer
114,214a, 214b: bit
Embodiment
For increasing the capacity of internal memory, the invention provides a P channel SONOS memory element method of operating, make can store two bits in the mnemon.The data that are stored in each mnemon can single bit be that unit erases, and therefore can reach the operation that single bit is erased.
See also Fig. 3, be generalized section according to the P channel NROM structure that has two bit memory functions in one embodiment of the invention.In Fig. 3, P channel SONOS memory element comprises a substrate 200, at the ONO layer 210 in the substrate 200, grid 212 on ONO layer 210.ONO layer 210 is structures of silicon monoxide/nitrogenize silicon/oxidative silicon, includes one silica layer 204, a silicon nitride layer 206 and one silica layer 208.In addition, two P are arranged
+Doped region 202a and 202b are arranged in ONO layer 210 substrate on two sides 200.Grid 212 for example is a P
+Doped polycrystalline silicon layer.The drain region be two doped region 202a and 202b one of them, and among two doped region 202a and the 202b another is just as source area.For instance, if a bit 214a is operated, the drain region is exactly doped region 202a so, and source area is exactly doped region 202b.When operating another bit 214b, on the contrary, the drain region is exactly doped region 202b, and source area is exactly doped region 202a.
P channel SONOS memory element of the present invention can be operated by a specific bias voltage, but two bit 214a and 214b to have storage data, and each bit can other erase.Fig. 4 is according to the grid current-voltage curve (Ig-Vg curve) of its operation of P channel SONOS memory element of one embodiment of the invention among Fig. 3.Can produce hot electron and hot hole in the P channel SONOS memory element of the present invention, these hot electrons produce down in different bias voltage configurations (biasconfiguration) with hot hole, and these bias voltage kenels are Vg, Vs, Vd and V
B, be meant the bias voltage that is applied to grid 212, source area, drain region and substrate 200 respectively.In Fig. 4, for example be-9V so just to have hot hole to produce, and for example be-1V so just to have hot electron to produce when grid 212 is applied in a bias voltage when grid 212 is applied in a bias voltage.That is to say that the absolute value that produces the required operating voltage (working voltage) of hot hole is higher than the absolute value that produces the required operating voltage of hot electron.
According to the characteristic of I-V curve among Fig. 4, hot hole can be stored in the silicon nitride layer 206 of ONO layer 210 near the place of the drain region of selecting, and this drain region for example is doped region 202a.If deposit bit 214a in, then doped region 202a is set to the drain region, and doped region 202b then is set to source area.Table 2 is can be in order to carry out the bias voltage configuration (bias configuration) of the sequencing action and the action of erasing.
Table 2
| ????Vg | ????Vd | ????Vs | ????V B | |
| Sequencing | ????-9V | ????-9V | ????0V | ????0V |
| Erase | ????-1V | ????-9V | (floating) floats | ????0V |
In the time will carrying out the sequencing action, grid bias Vg and drain bias Vd are set at the first high back bias voltage equally, for example are-9V.In this way, hot hole will be driven into and be accumulated in the part of close drain region 202a in the silicon nitride layer 206, promptly deposit bit 214a in, as shown in Figure 3.As the bit 214a that desires to erase, the hot hole that is accumulated in bit 214a position must be eliminated.The mechanism of erasing is hot electron to be driven in bit 214a position and data are erased.For this purpose, bias voltage for example is set to: Vg=-1V, and Vd=-9V, and Vs is set at and floats V
B=0V (ground connection).Therefore produce hot electron and import bit 214a position and general's hot hole elimination wherein.After cancelling out each other in electronics and electric hole, therefore data are erased.
If carry out sequencing to deposit another bit 214b in, then doped region 202b is selected as a drain region, and doped region 202a is promptly as source area.The configuration of bias voltage (configuration) is as described in Table 2 equally.
The mechanism that deposits another bit 214b in is identical with bit 214a, because the bias voltage that applies can produce a strong electric field in the place near the drain region, therefore can produce hot hole in the channel herein, it is attracted by the grid 212 of high back bias voltage simultaneously and passes silicon oxide layer 204, and insulated silicon nitride layer 206 is caught in wherein.So hot hole can be deposited to silicon nitride layer 206 partly, and stores precedent 1 data in this way.Same, when erasing action, hot hole can locally produce and flow to the silicon nitride layer 206 near the place, drain region.Other bit near source area can not be affected.Therefore, can single bit be the unit action of erasing, and do not influence another adjacent bit.In the present invention, this kind operation is called single bit operating.Known method in order to the data of erasing is to be that unit erases with a whole block, because it is to utilize the FN tunnelling mechanism data of erasing.Owing to utilize FN tunnelling mechanism can not produce electronics partly, therefore will inevitably have influence on contiguous bit and mnemon.
In the SONOS memory element, utilize the ONO layer with record data, make hot hole can be limited in the place near the drain region, therefore write or when erasing data, can store two bits in the mnemon according to aforesaid method of operation.On the other hand, data can be read by known mode.
In summary, the present invention uses a SONOS memory element that can store two bits of data in a mnemon, be data to be write in the silicon nitride layer near the position of drain region storing a bit, and will erase near a bit of drain region with hot electron with hot hole.
Though the present invention with the embodiment explanation as above; right its is not in order to qualification the present invention, any person skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion with claims.
Claims (12)
1. the method for operation of a sequencing and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon, wherein this SONOS mnemon includes two doped regions that a substrate, is arranged in this suprabasil ONO layer, a grid layer and is positioned at this substrate of these ONO layer both sides, and it is characterized by: this method of operation comprises:
One of them is appointed as the drain region with two doped regions, and another is a source area;
In the time will carrying out the sequencing action, hot hole is injected into partly a first area of close this drain region in this ONO layer; And
In the time will erasing action, the hot electron part is injected into close this place, drain region in this ONO layer, hot hole is eliminated.
2. the method for operation of the sequencing as claimed in claim 1 and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon, it is characterized by: the step that this hot hole is injected in this ONO layer partly comprises setting one bias voltage configuration, this bias voltage configuration is set at one first back bias voltage with this grid and this drain region, and with this source area ground connection, wherein the value of this first back bias voltage is enough to make hot hole to produce and injects this ONO layer.
3. the method for operation of the sequencing as claimed in claim 2 and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon is characterized by: this first back bias voltage is-9V.
4. the method for operation of the sequencing as claimed in claim 1 and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon, it is characterized by: the step that this hot electron part is injected in this ONO layer comprises setting one bias voltage configuration, this bias voltage configuration is set at one first back bias voltage with this drain region, and this grid is set at one second back bias voltage, and this substrate is set at an earthed voltage, wherein the absolute value of this first back bias voltage is greater than this second back bias voltage, and the difference of this first back bias voltage and this second back bias voltage is enough to make hot electron to produce and is injected in this ONO layer.
5. the method for operation of the sequencing as claimed in claim 4 and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon is characterized by: this first back bias voltage is-9V that this second back bias voltage is-1V.
6. the method for operation of the sequencing as claimed in claim 1 and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon, it is characterized by: the operation that writes and erase of one second bit in this P channel SONOS memory element, with opposite order this two doped region is appointed as source area and drain region.
7. the method for operation of a sequencing and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon, wherein this SONOS mnemon comprises two doped regions that a substrate, is arranged in a suprabasil ONO layer, a grid layer and is positioned at this substrate of these ONO layer both sides, and it is characterized by: this method of operation comprises:
One of them is source area to specify these two doped regions, and another is the drain region;
When wanting this mnemon of sequencing, apply one first bias voltage configuration to this grid, this drain electrode, this source electrode and this substrate, inject hot hole thus to the first area of this ONO layer near the drain region, promptly deposit one first bit in; And
When will erasing when action, by applying one second bias voltage configuration to this grid, this drain electrode, this source electrode and this substrate, and with local this first area of injecting this ONO layer of hot electron, so this hot hole in this first area is eliminated.
8. the method for operation of the sequencing as claimed in claim 7 and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon, it is characterized by: this first bias voltage configuration in the step of this mnemon sequencing is being comprised this grid of setting and this drain region are one first back bias voltage, and with this source area and this substrate ground connection, wherein the value of this first back bias voltage is enough to make hot hole to produce and injects this ONO layer.
9. the method for operation of the sequencing as claimed in claim 8 and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon is characterized by: this first back bias voltage is-9V.
10. the method for operation of the sequencing as claimed in claim 7 and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon, it is characterized by: comprise in this second bias voltage configuration this drain region is set at one first back bias voltage the step of local this first area of injecting this ONO layer of this hot electron, this grid is set at one second back bias voltage, and with this substrate ground connection, wherein the absolute value of this first back bias voltage is greater than this second back bias voltage, and the difference of this first back bias voltage and this second back bias voltage is enough to make hot electron to produce and is injected in this ONO layer.
11. the method for operation of the sequencing as claimed in claim 10 and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon is characterized by: this first back bias voltage is-9V that this second back bias voltage is-1V.
12. the method for operation of the sequencing as claimed in claim 7 and the P channel substrate-silicon oxide/silicon nitride/silicon oxide of erasing-silicon (SONOS) mnemon, it is characterized by: the operation that writes and erase of one second bit in this P channel SONOS memory element is with opposite order this two doped region to be appointed as source area and drain region.
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| CN 01130730 CN1213472C (en) | 2001-08-22 | 2001-08-22 | Operation of programmed and erasing P-channel SONOS memory unit |
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| CN 01130730 CN1213472C (en) | 2001-08-22 | 2001-08-22 | Operation of programmed and erasing P-channel SONOS memory unit |
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| CN100345283C (en) * | 2004-04-26 | 2007-10-24 | 旺宏电子股份有限公司 | Method and system for self-convergent erase in charge trapping memory cells |
| CN100390963C (en) * | 2004-06-02 | 2008-05-28 | 旺宏电子股份有限公司 | Program/erase method for p-channel charge trapping memory device |
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| CN100452406C (en) * | 2006-04-10 | 2009-01-14 | 清华大学 | Trap charge capturing quick flashing storage array structure and operating method thereof |
| CN100461425C (en) * | 2005-08-15 | 2009-02-11 | 力晶半导体股份有限公司 | Operation method for memory in P type channel |
| CN100463183C (en) * | 2005-10-10 | 2009-02-18 | 旺宏电子股份有限公司 | Method and apparatus for operating series nonvolatile memory unit |
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| CN100463187C (en) * | 2005-10-10 | 2009-02-18 | 旺宏电子股份有限公司 | Method and apparatus for operating charge trapping nonvolatile memory |
| CN1881592B (en) * | 2005-05-12 | 2010-05-12 | 三星电子株式会社 | Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices |
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| CN100447900C (en) * | 2003-06-17 | 2008-12-31 | 旺宏电子股份有限公司 | Overerase protection of memory cells for nonvolatile memory |
| CN100345283C (en) * | 2004-04-26 | 2007-10-24 | 旺宏电子股份有限公司 | Method and system for self-convergent erase in charge trapping memory cells |
| CN100390963C (en) * | 2004-06-02 | 2008-05-28 | 旺宏电子股份有限公司 | Program/erase method for p-channel charge trapping memory device |
| CN1722444B (en) * | 2004-07-06 | 2010-07-21 | 旺宏电子股份有限公司 | Charge trapping non-volatile memory and method for gate-by-gate erase for same |
| CN1881592B (en) * | 2005-05-12 | 2010-05-12 | 三星电子株式会社 | Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices |
| CN100461425C (en) * | 2005-08-15 | 2009-02-11 | 力晶半导体股份有限公司 | Operation method for memory in P type channel |
| CN100463184C (en) * | 2005-10-10 | 2009-02-18 | 旺宏电子股份有限公司 | Method and apparatus for operating paralledl arrangement nonvolatile memory |
| CN100463187C (en) * | 2005-10-10 | 2009-02-18 | 旺宏电子股份有限公司 | Method and apparatus for operating charge trapping nonvolatile memory |
| CN100463183C (en) * | 2005-10-10 | 2009-02-18 | 旺宏电子股份有限公司 | Method and apparatus for operating series nonvolatile memory unit |
| CN100452406C (en) * | 2006-04-10 | 2009-01-14 | 清华大学 | Trap charge capturing quick flashing storage array structure and operating method thereof |
| US7852673B2 (en) * | 2006-06-14 | 2010-12-14 | Macronix International Co., Ltd | Method for operating nonvolatitle memory array |
| CN101826526B (en) * | 2009-03-06 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor memory unit, driving method thereof and semiconductor memory |
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