CN1472801A - Chip packaging substrate - Google Patents
Chip packaging substrate Download PDFInfo
- Publication number
- CN1472801A CN1472801A CNA021270937A CN02127093A CN1472801A CN 1472801 A CN1472801 A CN 1472801A CN A021270937 A CNA021270937 A CN A021270937A CN 02127093 A CN02127093 A CN 02127093A CN 1472801 A CN1472801 A CN 1472801A
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- insulating barrier
- district
- chip package
- conductor layer
- test circuit
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Abstract
A wafer packaging substrate consists of a packaging area and connecting area as the packaging area is surrounded by the connecting area. The multiple electrode is located at surface of the connecting area with a testing circuit set in the connecting area too. The testing circuit is electric-connected to the said electrodes separately to detect whether there is any breakage on the wafer packaging substrate or not.
Description
Technical field
The invention relates to a kind of chip package base board,, can utilize this test circuit to detect whether layering of chip package base board, cause substrate to open circuit (Open), reach quality control in advance particularly relevant for a kind of chip package base board with test circuit.
Background technology
Along with the trend of electronic product towards compact development, the manufacturing of printed circuit board (PCB) is also ultra-thin towards thickness, and the live width of conducting wire is ultra-fine, the super narrow direction of line-spacing develops.At present industry the most normal use be plastic cement ball grid array (Plastic Ball Grid Array, PBGA) encapsulation, the PBGA base plate for packaging mainly is used on wafer set and the drawing wafer, utilize the tin ball to arrange in PBGA base plate for packaging bottom in the mode of array, as the pin between wafer and printed circuit board (PCB), substitute conductive metal frames in the past, its advantage is under the same size, number of pins can increase, and pin is apart from also strengthening, therefore the PBGA base plate for packaging be solve wafer-level packaging (Chip Scale Package/Flip Chip, FCBGA) and the portable product high I/O is counted the crucial encapsulation technology of demand.
Figure 1A is the vertical view of the known PBGA base plate for packaging assembly of expression.Shown in Figure 1A the base plate for packaging of printed circuit board (PCB) factory shipment when giving wafer package factory, it is arranged with 1 * 4 matrix-style, can encapsulate four wafers, but according to the required arranged mode that also has other of practical application, Figure 1B shows the vertical view of a cell substrate of PBGA base plate for packaging assembly among Figure 1A.Shown in Figure 1B, above-mentioned PBGA base plate for packaging 10 comprises a square encapsulation region 12, and the mode with array on it is provided with metal bond pad 121; One square links district 11 and surrounds above-mentioned encapsulation region 12, remains with the gap between the inner edge in binding district 11 and the outer rim of encapsulation region 12.Above-mentioned binding district 11 only is used for fixing above-mentioned encapsulation region 12, and the usefulness of equipment board clamping is provided when wafer encapsulates, therefore, can be cut after wafer is finished encapsulation, form waste material.
Usually the PBGA base plate for packaging has multi-layer conductor leads layer (more than 8 layers), the only about 0.5mm of its thickness, and the live width of each conductor layer, line-spacing are only below 0.1mm.And known printed circuit board (PCB) processing procedure comprises handling procedures such as high temperature, high humidity, strong acid, highly basic, therefore, the PBGA base plate for packaging is easy to produce because of rising-heat contracting-cold the situation of distortion, layering, or damages the conducting wire because produce fold during superimposed thin copper foil, causes product defects.
In addition, PBGA base plate for packaging and general printed circuit board (PCB) maximum be not both the PBGA base plate for packaging must with wafer package after, could carry out testing electrical property together with the wafer of the test circuit of design collocation in advance in the encapsulation region, and the test result of having done only can know whether the wafer finished of encapsulation is normal, and can not know it is PBGA base plate for packaging defectiveness respectively, crystal grain is bad, also or because of encapsulating institute cause, and cause the bad probability of wafer three's summation especially, therefore, the wafer manufacture yield can descend, or normal crystal grain usually takes place be packaged in situation on the bad PBGA base plate for packaging, cause the wafer manufacturing cost to improve.
Refer again to Figure 1A, owing to come out by same printed circuit board (PCB) processing procedure made simultaneously in the encapsulation region 12 of known PBGA base plate for packaging 10 and binding district 11, it has the plural metal level and the insulating barrier of similar number, its difference only is that the plural metal level of encapsulation region 12 is used to make set circuit (not shown), forms the complex lead layer; Link the usefulness that district 11 then is used to provide equipment board location, clamping, therefore the metal level in linking district 11 is not used to make circuit to form conductor layer, it still has plural simple metal layer, and after encapsulation region 12 is finished die package, is excised as waste material.
Summary of the invention
In view of this, purpose of the present invention just is to provide a kind of chip package base board with test circuit, utilization can be by the binding district as the waste material excision in known techniques, in above-mentioned binding district, make test circuit, for usefulness for the detection of chip package base board product, making this chip package base board can just carry out product before die package detects, make bad chip package base board with prior filtering, to promote the product yield, to reduce production costs, also can be applicable to provides identical function in the making of printed circuit board (PCB).
For reaching above-mentioned purpose, the invention provides a kind of chip package base board with test circuit, comprise the binding district that an encapsulation region and is connected with encapsulation region, it has the complex lead layer and is arranged at intervals at plural insulating barrier between the conductor layer, and link the district and be provided with a plurality of electrode and test circuits that chip package base board links the surface, district that are arranged at, wherein test circuit is to be arranged to link to electrically connect each electrode within the district, and at least by two adjacent conductor layers and be sandwiched in therebetween insulating barrier.
In a preferred embodiment, encapsulation region has by linking conductor layer and the insulating barrier that extend in the district.
In a preferred embodiment, linking the district is to surround to be arranged at the encapsulation region periphery.
In a preferred embodiment, link the district and have plurality of through holes (Vias), above-mentioned through hole is the through-wafer base plate for packaging, makes test circuit electrically connect each conductor layer.
Again, above-mentioned electrode and through hole are to be arranged at intervals to link in the district.
In a preferred embodiment, link the district and has a plurality of blind holes (Blind Vias), above-mentioned blind hole is to run through at least two conductor layers and be sandwiched in therebetween insulating barrier, makes test circuit electrically connect at least two conductor layers.
Again, above-mentioned electrode and blind hole are to be arranged at intervals to link in the district.
In a preferred embodiment, test circuit is made of electric conducting material.
In a preferred embodiment, above-mentioned insulating barrier is made of high molecular polymer (Polymer Resin).
The present invention provides a kind of chip package base board assembly with test circuit in addition, comprise a plurality of encapsulation regions and a binding district that is connected with each encapsulation region, it has the complex lead layer and is arranged at intervals at plural insulating barrier between the conductor layer, and link the district and be provided with a plurality of electrode and test circuits that chip package base board links the surface, district that are arranged at, wherein test circuit is to be arranged at each electrode of interior electric connection that links the district, and at least by two adjacent conductor layers and be sandwiched in therebetween insulating barrier.
In a preferred embodiment, encapsulation region has by linking conductor layer and the insulating barrier that extend in the district.
In a preferred embodiment, linking the district is to surround to be arranged at each encapsulation region periphery.
In a preferred embodiment, link the district and have plurality of through holes (Vias), above-mentioned through hole is the through-wafer base plate for packaging, makes test circuit electrically connect each conductor layer.
Again, above-mentioned electrode and through hole are to be arranged at intervals to link in the district.
In a preferred embodiment, link the district and has a plurality of blind holes (Blind Vias), above-mentioned blind hole is to run through at least two conductor layers and be sandwiched in therebetween insulating barrier, makes test circuit electrically connect at least two conductor layers
Again, above-mentioned electrode and blind hole are to be arranged at intervals to link in the district.
In a preferred embodiment, test circuit is made of electric conducting material.
In a preferred embodiment, above-mentioned insulating barrier is made of high molecular polymer (Polymer Resin).
Description of drawings
Figure 1A represents the vertical view of known PBGA base plate for packaging assembly;
Figure 1B shows the vertical view of a cell substrate of PBGA base plate for packaging assembly among Figure 1A;
Fig. 2 A is the vertical view of first embodiment of the invention PBGA base plate for packaging;
Fig. 2 B is the profile in a-a cross section among Fig. 2 A;
Fig. 3 is the vertical view of second embodiment of the invention PBGA base plate for packaging assembly;
Fig. 4 is the flow chart of the method for testing of chip package base board of the present invention.
The figure number explanation:
The 10-PBGA base plate for packaging;
11-links the district;
The 12-encapsulation region;
The 121-metal bond pad;
The 13-connecting portion;
The 20-PBGA base plate for packaging;
21-first electrode;
22-second electrode;
23-links the district;
The 231-through hole;
The 232-blind hole;
The 234-test circuit;
The 24-encapsulation region;
The 24-metal bond pad;
The 251-conductor layer No.1;
252-second conductor layer;
253-privates layer;
254-privates layer;
The 26-insulating barrier;
The 261-first insulation top layer;
The 262-second insulation top layer;
30-PBGA base plate for packaging assembly;
The 31-encapsulation region;
The 311-metal bond pad;
32-links the district;
The 34-test circuit;
The 341-metal electrode;
The 342-through hole;
The 343-blind hole.
Embodiment
See also Fig. 2 A, Fig. 2 A is the vertical view of PBGA base plate for packaging of the present invention, the chip package base board 20 of present embodiment, it is laminated by complex lead layer and insulation, chip package base board 20 comprises a square encapsulation region 24, mode with array on the encapsulation region 24 is provided with metal bond pad 241, and its inside has a set circuit, can be used for the encapsulation of wafer; Link district 23 and have a square, remain with the gap between the inner edge in binding district 23 and the outer rim of encapsulation region 24, and be connected with encapsulation region 24 in last corner in the periphery of encapsulation region 24.
Shown in Fig. 2 A, chip package base board 20 of the present invention has one first electrode 21 and one second electrode 22 in the insulation top layer that links district 23, link in the district 23 and have a test circuit 234 in addition, this test circuit 234 is around being arranged in the binding district 23 and electrically connecting above-mentioned first, second electrode 21,22.On the path of test circuit 234, utilize with encapsulation region 24 in identical circuit production mode form plurality of through holes 231 (Vias) and blind hole 232 (Blind vias), each conductor layer that makes chip package base board 20 link district 23 can electrically connect respectively, to detect whether produce the delamination or the situation of dislocation at chip package base board 20 at the conductor layer of diverse location.
Fig. 2 B is the profile in a-a cross section among Fig. 2 A, for simplicity of illustration, the PBGA base plate for packaging 20 of present embodiment only is made of four layers of metal level, each is completely cut off with an insulating barrier 26 between each metal level, and be folded between one first insulation top layer 261 and the one second exhausted top layer table 262, so the PBGA base plate for packaging 20 of present embodiment can form four layer conductor layers, and for convenience of description, be defined as the one one privates layer 251-254 from top to bottom in regular turn, but the actual PBGA base plate for packaging situation of looking may have more conductor layer.
Shown in Fig. 2 A, Fig. 2 B, through hole 231 is each conductor layer 251-254 and each insulating barrier 26 that run through whole PBGA base plate for packaging 20, inner metal or the conductive material of filling makes conductor layer No.1 251 can electrically connect privates layer 254, promptly connects the superiors and undermost conductor layer; Blind hole 232 is holes that each conductor layer forms intraconnections, and wherein blind hole 232 runs through any at least two conductor layer 251-254 and is sandwiched in therebetween insulating barrier 26, makes test circuit 234 can electrically connect above-mentioned conductor layer 251-254.Therefore, be arranged at the test circuit 234 that links in the district 23 among Fig. 2 B, extend by first electrode 21, it utilizes through hole 231 to extend to privates layer 254 earlier in conductor layer No.1 251, then extend to privates layer 253, conductor layer No.1 251, second conductor layer 252 via blind hole 232, last test circuit 234 around whole encapsulation region 24 after, electrically connect second electrode 22 be positioned at privates layer 254.First electrode 21 and second electrode 22 also can be not only one, can respectively be a plurality of, therefore can record between wantonly two electrodes on the PBGA base plate for packaging 20 whether have layering or the phenomenon that opens circuit respectively.
Fig. 3 is the vertical view of another embodiment of the present invention PBGA base plate for packaging assembly, as shown in Figure 3, base plate for packaging assembly 30 has four encapsulation regions 31 that are arrayed, on it respectively the mode with array a plurality of metal bond pads 311 are set, and each encapsulation region 31 inside has a set circuit, can be used for the encapsulation of wafer.Have the district of binding 32 in the periphery of encapsulation region 31, be used for fixing each encapsulation region 31, and the usefulness of sealed in unit clamping is provided.Link district 32 have one around test circuit 34, there is plurality of electrodes 341 on the insulation top layer in binding district 32, and test circuit 34 is to electrically connect each electrode 341, wherein test circuit 34 also utilizes known printed circuit board (PCB) manufacturing technology to form through hole 342 and blind hole 343 between each electrode, to electrically connect each circuit layer.What in addition, above-mentioned electrode 341 also can be according to first embodiment is arranged on down electrode insulating surface through test circuit 34 and electrically connecting.
As known from the above, the embodiment of the invention be to make full use of unnecessary binding district, the test circuit that centers on encapsulation region is set in linking the district, its layout type is very simple, therefore, when PBGA base plate for packaging assembly 30 completes, can test base plate for packaging assembly 30 earlier by plant substrate; If between wantonly two electrodes for opening circuit, know that promptly near the PBGA base plate for packaging 20 this two electrode is defective products, in making half-finished process or in the charging screening of encapsulation factory, earlier this PBGA base plate for packaging 20 is eliminated, just energy Da Fu increases the yield of wafer overall package, effectively reduces production costs.
In addition, the metal level in the conductor layer that the present invention carried is made of copper, gold, nickel or other conductive materials; And each insulating barrier is mainly by high molecular polymer (Polymer Resin), and for example epoxy resin (Epoxy), polyester (Polyester), cyanic acid polyester (Cyanate Ester) or polyethylene (Polyethylene) etc. constitute.
Fig. 4 is the flow chart of the method for testing of chip package base board of the present invention.As shown in Figure 4, earlier make a PBGA base plate for packaging with the processing procedure of conventional P bga substrate, wherein this PBGA base plate for packaging has a plurality of encapsulation regions and as described above and connects one of each encapsulation region and link the district, has plurality of electrodes and electrically connect the test circuit (S41) of each electrode in linking the district.When the base plate line etching of PBGA is finished or before the wafer package, utilize ohmer to detect whether wantonly two electrodes are path (S42), wherein can do a screening operation in advance in the PBGA manufacture process, defective products can be removed earlier, exempt to produce waste, and in the receiving inspection of encapsulation factory, if be path between wantonly two these electrodes, then this PBGA base plate for packaging is directly to carry out die package (S43) normally; If have one group for opening circuit between wantonly two these electrodes, judge that then this PBGA base plate for packaging has layering or other defective (S44), need this PBGA base plate for packaging is rejected (S45); Next carry out die package with these PBGA base plate for packaging that detected again, so just can significantly promote the whole yield of PBGA encapsulated wafer.
Claims (8)
1. chip package base board comprises:
One encapsulation region;
One links the district, be connected with this encapsulation region, this binding district has complex lead floor, plural insulating barrier, one first insulation top layer and one second insulation top layer, this first insulation top layer has a plurality of first electrodes, wherein this insulating barrier is arranged at intervals between this conductor layer, and this insulating barrier and this conductor layer insert and put between this first insulation top layer and this second insulation top layer;
One test circuit is to be arranged at this conductor layer and this insulating barrier, and wherein this test circuit is at least by two adjacent these conductor layers and be sandwiched in therebetween this insulating barrier, and electrically connects this first electrode.
2. chip package base board according to claim 1 is characterized in that: this second insulating barrier has a plurality of second electrodes, and this test circuit also electrically connects this second electrode.
3. chip package base board according to claim 1 is characterized in that: this binding district surrounds to be arranged at this encapsulation region periphery.
4. chip package base board according to claim 1 is characterized in that: this encapsulation region has this conductor layer and this insulating barrier that is extended by this binding district.
5. chip package base board according to claim 1, it is characterized in that: this binding district has plurality of through holes, this through hole is to run through this conductor layer, this insulating barrier, this first insulation top layer and this second insulation top layer, makes this test circuit electrically connect this conductor layer.
6. chip package base board according to claim 1 is characterized in that: this binding district has a plurality of blind holes, and this blind hole is to run through this at least two conductor layer and be sandwiched in therebetween this insulating barrier, makes this test circuit electrically connect this at least two conductor layer.
7. chip package base board according to claim 1 is characterized in that: this insulating barrier is made of high molecular polymer.
8. chip package base board according to claim 1 is characterized in that: this encapsulation region respectively has a set circuit, and the test circuit in this binding district is to be made simultaneously with this set circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02127093 CN1251325C (en) | 2002-07-29 | 2002-07-29 | Chip packaging substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02127093 CN1251325C (en) | 2002-07-29 | 2002-07-29 | Chip packaging substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1472801A true CN1472801A (en) | 2004-02-04 |
| CN1251325C CN1251325C (en) | 2006-04-12 |
Family
ID=34143468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02127093 Expired - Fee Related CN1251325C (en) | 2002-07-29 | 2002-07-29 | Chip packaging substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1251325C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103779251A (en) * | 2014-01-07 | 2014-05-07 | 上海众人网络安全技术有限公司 | COB binding line test method |
| CN110767624A (en) * | 2018-07-27 | 2020-02-07 | 矽品精密工业股份有限公司 | Bearing structure and packaging structure |
| WO2020248212A1 (en) * | 2019-06-14 | 2020-12-17 | 深圳市汇顶科技股份有限公司 | Chip encapsulation structure and electronic device |
-
2002
- 2002-07-29 CN CN 02127093 patent/CN1251325C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103779251A (en) * | 2014-01-07 | 2014-05-07 | 上海众人网络安全技术有限公司 | COB binding line test method |
| CN103779251B (en) * | 2014-01-07 | 2016-04-20 | 上海众人网络安全技术有限公司 | A kind of COB binding line method of testing |
| CN110767624A (en) * | 2018-07-27 | 2020-02-07 | 矽品精密工业股份有限公司 | Bearing structure and packaging structure |
| WO2020248212A1 (en) * | 2019-06-14 | 2020-12-17 | 深圳市汇顶科技股份有限公司 | Chip encapsulation structure and electronic device |
| US11302621B2 (en) | 2019-06-14 | 2022-04-12 | Shenzhen GOODIX Technology Co., Ltd. | Chip package structure and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1251325C (en) | 2006-04-12 |
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
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| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: TAIJI HOLDING CO., LTD. Free format text: FORMER OWNER: XITONG SCIENCE AND TECHNOLOGY CO LTD Effective date: 20091113 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20091113 Address after: Delaware Patentee after: Silicon Integrated Systems Corporation Address before: Hsinchu Science Park, Taiwan Patentee before: Xitong Science & Technology Co., Ltd. |
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060412 Termination date: 20130729 |