CN1472784A - Semiconductor power component device and packaging method thereof - Google Patents
Semiconductor power component device and packaging method thereof Download PDFInfo
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- CN1472784A CN1472784A CNA021269947A CN02126994A CN1472784A CN 1472784 A CN1472784 A CN 1472784A CN A021269947 A CNA021269947 A CN A021269947A CN 02126994 A CN02126994 A CN 02126994A CN 1472784 A CN1472784 A CN 1472784A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The device connects the first and the second vertical power elements connected with the first and the second wire frames in parallel so the packaging surface for heat radiating is enlarged by up and down bimetal plates lapped with two wire frames. The device can have connected-through resistance value decreased by 50%, current flowing-through value stand by parallel circuit increased by double times.
Description
Technical field
The present invention relates to be used to reduce conducting resistance, improve the semiconductor power component device and the method for packing thereof of conducting electric current and increase radiating efficiency, be meant especially and a kind ofly utilize two to leak the level contacts and be fixedly connected on first, second two rectilinear power components on first, second conductive metal frames respectively, the overlapped parallel-connection structure that connects and composes, and make this first, second lead frame be overlapped to form upper and lower bimetallic plates, utilize the upper strata metallic plate to enlarge the package surface of heat radiation.
Background technology
The Taiwan patent of invention is announced No. 426850 and has been disclosed a kind of " waterfall stacking-type wafer module ", and it mainly comprises: a laminated plates has a plurality of contacts at least on this laminated plates; A plurality of wafers are disposed on this laminated plates, and wherein each wafer includes a plurality of weld pads; One reshuffles layer, disposes and is electrically connected on these weld pads; One first insulating barrier, be disposed at above-mentioned reshuffle the layer and weld pad between, and by a plurality of connectors make reshuffle the layer become electric property to be connected with weld pad; A plurality of bump bond are disposed at first, second zone of reshuffling on the layer respectively, and wherein the bump bond in first, second zone disposes in the mirror image mode, and the bump bond of per two correspondences all is electrically connected by the reprovision layer.It is staggered superimposed that wherein above-mentioned wafer is divided into first and second row, the first area of the first row wafer is in the face of the second area of secondary series wafer, and the second area of the first row wafer is in the face of the first area of secondary series wafer, and the bump bond that the second area of opposite face is corresponding with the first area connects with a conductive projection respectively.In addition, two soft sheet type bearing devices, the chip with two ends of this two row chip is electrically connected with the contact of laminated plates respectively.
In addition, the Taiwan patent of invention is announced No. 423082 and has been disclosed a kind of " the folded wafer package that goes up of the wafer of Gao Jiti ", mainly comprise: the folded wafer module of going up of a wafer, this module is provided with the individual wafers of at least two active regions that link together on electric, and wherein the effect fauna of these two wafers is faced mutually; And the folded wafer assemblies jockey of going up of a wafer, in order on electric, described wafer is connected to external circuit.
Present known semiconductor power component device, such as the power metal oxide semiconductor field-effect transistor that is used for high speed diverter switch element (MOSFET), the insulated gate bipolar transistor (IGBT) that is used for the electric power diverter switch, bipolarity junction transistor (BJT), power diode (DIODE), or rectifier (RECTIFIER) etc., traditional single power component device, leak conducting resistance (that is R, of level/source electrode (or the collection utmost point/emitter-base bandgap grading)
DS-ON) bigger, its relative power loss is also big, and supervenes big heat, and then influences its product useful life.Therefore, reduce conducting resistance, improve the conducting electric current and increase radiating efficiency, improve product performance, be the problem of the anxious desire solution in high power semiconductor field.If but set about improving from the traditional circuit design aspect, not only increase the complexity of (PCC) power circuit and structure, and the research and development time is long, cost is very high.
Summary of the invention
Main purpose of the present invention is to provide a kind of reduction conducting resistance, improves the conducting electric current, increases radiating efficiency, and save the semiconductor power component device of encapsulation volume.
Semiconductor power component device provided by the invention comprises first and second two rectilinear power components, and the gate regions of described power component and gate regions, source area and source area are overlapping accordingly to link together, and connects and lead to pin; The leakage level of above-mentioned power component, be connected on first and second liang of conductive metal frames, wherein an end of first lead frame includes a pin, one end of second lead frame includes sidewall that extends perpendicular to this lead frame and the faying surface that is parallel to this lead frame, two lead frames are overlapped to form upper and lower bimetallic plates, utilize the upper strata metallic plate to enlarge the package surface of heat radiation.
Another object of the present invention is to provide a kind of conducting resistance that is used to reduce, improve the conducting electric current and increase radiating efficiency, and save the method for packing of the semiconductor power component device of encapsulation volume.
The step of above-mentioned method for packing comprises: first and second two rectilinear power components are fixed on first and second two lead frame symmetrically, and a leakage level contact forms electric property with lead frame respectively and is connected; Wherein an end of first lead frame forms the face of connecing of establishing that enlarges, and the other end extends a pin and two pins that separate; One end of second lead frame includes sidewall that extends perpendicular to this lead frame and the faying surface that is parallel to this lead frame, and the other end extends a pin faying surface; The grid of first power component is formed electric property with two pins that separate with source contact respectively by metal wire to be connected; By the tin stove, with tin ball shifting apparatus the tin ball is implanted in the grid and the source contact of first, second power component, and on the faying surface of the first lead frame pin and second lead frame; Second lead frame upset is connected on first lead frame, and makes the grid and grid, relative overlapping connection of source electrode of second power component and first power component with source contact; By baking box, heating and pressurization make the fusion of tin ball, and first, second power component and first, second lead frame are welded together relatively; With the encapsulation of plastic cement molding material, make first and second lead frame form upper and lower bimetallic plates on the semiconductor power component device surface, utilize the upper strata metallic plate to enlarge the package surface of heat radiation.
The present invention is combined into two power components the mode of a parallel-connection structure, not only make simple, and the conduction resistance value of this semiconductor power component device also can reduce by 1/2nd, the electric current bearing value of its parallel circuits doubles, constitute the package surface that upper and lower bimetallic plates have enlarged heat radiation by two lead frames, reach from the efficient of upper strata metallic plate by extraneous air heat radiation and to double effect, and save encapsulated space.
Description of drawings
Fig. 1 (A) is for showing the stereogram of semiconductor power component device end face of the present invention.
Fig. 1 (B) is for showing the stereogram of semiconductor power component device of the present invention bottom surface.
Fig. 1 (C) is for showing the preceding decomposing state stereogram of semiconductor power component device encapsulation of the present invention.
Fig. 2 is the intermediate steps end view of encapsulation semiconductor power component device of the present invention, and wherein the plastic cement molding material is represented with chain-dotted line.
Fig. 3 (A) is the encapsulation step schematic diagram of semiconductor power component device of the present invention to Fig. 3 (E).
Fig. 4 is the electronic circuitry of semiconductor power component device of the present invention.
Fig. 5 is the equivalent circuit diagram of semiconductor power component device of the present invention.
Fig. 6 implements the kenel schematic diagram for semiconductor power component device of the present invention is another kind of.
Fig. 7 is the another kind of encapsulation of semiconductor power component device of the present invention kenel schematic diagram.
Fig. 8 is the enforcement kenel schematic diagram of the invention process at the semiconductor power component device of plane formula layout.
Embodiment
Semiconductor power component device involved in the present invention, such as the power metal oxide semiconductor field-effect transistor that is used for electronic circuit component, perhaps insulated gate bipolar transistor etc., be rectilinear layout, promptly leak grade (Drain)/or the collection utmost point (Collector) is below, and source electrode (Source)/or emitter-base bandgap grading (Emitter) and the superincumbent layout type of grid (Gate), wherein this power component also can be diode, rectifier and bipolarity junction transistor.Below conjunction with figs. embodiment is illustrated that the present invention is applied to reduce conducting resistance, improve the conducting electric current and increase radiating efficiency, and save the semiconductor power component device and the method for packing thereof of encapsulated space.
As Fig. 1 (A) to Fig. 1 (C) and shown in Figure 2, semiconductor power component device 1 of the present invention, it comprises: the first power component Q1 and the second two power component Q2, the gate regions G1 of described power component Q1, Q2 and gate regions G2, source area S1 and source area S2 are overlapping accordingly to link together, and connects pin G, S respectively; Leakage level D1, the D2 of above-mentioned power component Q1, Q2 are connected on first conductive metal frames 10 and the second liang of conductive metal frames 20.Wherein an end of first lead frame 10 includes a pin D, the other end fixing face of connecing 11 of establishing that extends outwardly out, and be provided with fixing hole 12; One end of second lead frame 20 includes sidewall 21 that extends perpendicular to this lead frame and the faying surface 22 that is parallel to this lead frame, with first lead frame 10 establish the face of connecing 11 overlap joints, the other end is stretched and is provided with a pin D ', with the pin D overlap joint of first lead frame 10.Therefore, two power component Q1, Q2 are in fact in conjunction with parallel-connection structure of formation, and this first lead frame 10 and the upper and lower bimetallic plates of second lead frame, 20 overlap joint formation, utilize the upper strata metallic plate to enlarge the package surface of heat radiation.
To shown in Fig. 3 (E), the step of above-mentioned semiconductor power component device 1 method for packing comprises as Fig. 3 (A):
Step 1: shown in Fig. 3 (A), earlier the first power component Q1 and the second power component Q2 are fixed on symmetrically on first lead frame 10 and the second liang of lead frame 20, leak grade contact D1, D2 and be connected with the electric property of lead frame 10,20 formation respectively; Wherein an end of first lead frame 10 extends pin G, the S that a pin D separates with two; One end of second lead frame 20 includes sidewall 21 that extends perpendicular to this lead frame and the faying surface 22 that is parallel to this lead frame, and the other end extends a pin D '.
Step 2: shown in Fig. 3 (B), the grid G 1 of the first power component Q1 is formed electric property with pin G, S with source S 1 contact respectively with metal wire be connected.
Step 3: shown in Fig. 3 (C), by the tin stove, with tin ball shifting apparatus (not shown) tin ball 30 is implanted in grid G 1, G2 and source S 1, the S2 contact of first, second power component Q1, Q2 respectively, and on the faying surface 22 and pin D ' of the pin D of first lead frame 20 and second lead frame 10.
Step 4: shown in Fig. 3 (D), the upset of second lead frame 20 is connected on first lead frame 10, and the gate regions G2 that makes the second power component Q2 and source area S2 respectively with relative overlapping connection of contact of gate regions G1 and the source area S1 of the first power component Q1; By the baking box (not shown), heating and pressurization make 30 fusions of tin ball, and first, second power component Q1, Q2 and first, second lead frame 10,20 are welded together relatively again.
Step 5: shown in Fig. 3 (E),, make first and second lead frame 10,20 form upper and lower bimetallic plates, utilize the upper strata metallic plate to enlarge the package surface of heat radiation on semiconductor power component device 1 surface with 40 encapsulation of plastic cement molding material.
As mentioned above, utilize semiconductor power component device of the present invention and method for packing thereof, come down to two power components are formed a parallel-connection structure by the welding material of metal solder bond, and therefore can produce following effect:
When (1) electric current flow to source terminal S from leaking a level end D, the parallel circuits of flowing through, thereby can bear electric current I D and double, as shown in Figure 4.
(2) source electrode and the conduction resistance value R that leaks inter-stage
DS (ON)Diminish, be about original 1/2nd (as shown in Figure 5), i.e. the conduction resistance value of this two power component
, be the function of VG1), and
, be the function of VG2) the parallel resistance value.
(3) breakdown voltage is constant.
(4) encapsulation back constancy of volume.
(5) first and second lead frame forms upper and lower bimetallic plates on the semiconductor power component device surface, utilizes the upper strata metallic plate to enlarge the package surface of heat radiation, shown in Fig. 1 (A) and Fig. 1 (B), has improved radiating efficiency.
In addition, and for example shown in Figure 6, in response to the semiconductor power component device microminiaturization, in fact applicable space is extremely limited in trickle procedure for processing, metal wire is crossed over source S 1 district and is caused short circuit when avoiding grid G 1 to be connected with pin G, therefore the arrangement of power component Q1, Q2 can be arranged to grid G 1 district with pin G equidirectional and distance the shortest.
Fig. 7 is semiconductor power component device 1 another kind of encapsulation kenel of the present invention, the difference of this embodiment and other embodiment is, during encapsulation insulated with plastic cement molding material 40 in second lead frame 20 (upper strata metallic plate) surface, avoid this upper strata metallic plate by false touch, and can utilize this surface marking element model etc.
Fig. 8 is the encapsulation kenel of the present invention at the semiconductor power component device 1 of plane formula layout.The structure of present embodiment and method for packing are as the foregoing description, therefore repeat no more, the difference of present embodiment and other embodiment is, with the grid G 1 of the first power component Q1 on first lead frame 10, leak a level D1 and form electric property with metal wire with pin G, D, S respectively with source S 1 contact and be connected; With grid G 2, leakage level D2 and source S 2 contacts of the second power component Q2 on second lead frame 20, overlapping being connected on the corresponding grid G 1 of the first power component Q1 on first lead frame 10, leakage level D1 and source S 1 contact.So similarly can reach purpose of the present invention and effect.
In sum, utilize the present invention to be used to reduce conducting resistance, improve the conducting electric current and increase radiating efficiency, and save the semiconductor power component device and the method for packing thereof of encapsulated space, not only the research and development time can be shortened significantly, outside reducing production costs, more can make the conduction resistance value of semiconductor power component device reduce by 1/2nd, its parallel circuits bears the current value value of flowing through and doubles, two lead frames constitute upper and lower bimetallic plates, utilize the upper strata metallic plate to enlarge the package surface of heat radiation, improved radiating efficiency, and saved encapsulated space.
Above-mentioned only is preferred embodiment of the present invention, does not limit to encapsulation pattern of the present invention and practical range thereof, does not promptly depart from similar variation and modification that scope of the present invention is done, should still belong to covering scope of the present invention.
Claims (7)
1. one kind is used to reduce conducting resistance, improves the conducting electric current and increases the method for packing of the semiconductor power component device of radiating efficiency, and its step comprises:
First and second two rectilinear power components are fixed on first and second two lead frame symmetrically, and a leakage level contact forms electric property with lead frame respectively and is connected; Wherein an end of first lead frame forms the face of connecing of establishing that enlarges, and the other end extends a pin and two pins that separate; One end of second lead frame includes sidewall that extends perpendicular to this lead frame and the faying surface that is parallel to this lead frame, and the other end extends a pin faying surface;
The grid of first power component is formed electric property with two pins that separate with source contact respectively by metal wire to be connected;
By the tin stove, with tin ball shifting apparatus the tin ball is implanted in the grid and the source contact of first, second power component, and on the faying surface of the first lead frame pin and second lead frame;
Second lead frame upset is connected on first lead frame, and makes the grid and grid, relative overlapping connection of source electrode of second power component and first power component with source contact;
By baking box, heating and pressurization make the fusion of tin ball, and first, second power component and first, second lead frame are welded together relatively;
With the encapsulation of plastic cement molding material, make first and second lead frame form upper and lower bimetallic plates on the semiconductor power component device surface, utilize the upper strata metallic plate to enlarge the package surface of heat radiation.
2. the method for packing of semiconductor power component device as claimed in claim 1, wherein power component comprises: power diode, rectifier, rectilinear and plane formula power metal oxide semiconductor field-effect transistor, bipolarity junction transistor and insulated gate bipolar transistor.
3. one kind is used to reduce conducting resistance, improves the semiconductor power component device of conducting electric current and increase radiating efficiency, and it comprises:
First and second two rectilinear power components, the gate regions of described power component and gate regions, source area and source area are overlapping accordingly to link together, and connects and lead to pin; The leakage level of above-mentioned power component, be connected on first and second liang of conductive metal frames, wherein an end of first lead frame includes a pin, one end of second lead frame includes sidewall that extends perpendicular to this lead frame and the faying surface that is parallel to this lead frame, two lead frames are overlapped to form upper and lower bimetallic plates, utilize the upper strata metallic plate to enlarge the package surface of heat radiation.
4. semiconductor power component device as claimed in claim 3, wherein an end of second lead frame extends a pin, is overlapped on the pin of first lead frame.
5. semiconductor power component device as claimed in claim 3, wherein an end of first lead frame extend one be used for fixing establish the face of connecing.
6. semiconductor power component device as claimed in claim 3, wherein the grid of first, second power component and source contact reach on the faying surface of first and second lead frame, form parallel-connection structure by the welding material of metal welding.
7. semiconductor power component device as claimed in claim 3, wherein power component comprises: power diode, rectifier, rectilinear and plane formula power metal oxide semiconductor field-effect transistor, bipolarity junction transistor and insulated gate bipolar transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021269947A CN1472784A (en) | 2002-07-30 | 2002-07-30 | Semiconductor power component device and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021269947A CN1472784A (en) | 2002-07-30 | 2002-07-30 | Semiconductor power component device and packaging method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN1472784A true CN1472784A (en) | 2004-02-04 |
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| CNA021269947A Pending CN1472784A (en) | 2002-07-30 | 2002-07-30 | Semiconductor power component device and packaging method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI787111B (en) * | 2022-04-08 | 2022-12-11 | 強茂股份有限公司 | Packaged component with composite pin structure and its manufacturing method |
-
2002
- 2002-07-30 CN CNA021269947A patent/CN1472784A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI787111B (en) * | 2022-04-08 | 2022-12-11 | 強茂股份有限公司 | Packaged component with composite pin structure and its manufacturing method |
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