CN1466172A - Back side metallization technology for eutectic welding - Google Patents
Back side metallization technology for eutectic welding Download PDFInfo
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- CN1466172A CN1466172A CNA021141991A CN02114199A CN1466172A CN 1466172 A CN1466172 A CN 1466172A CN A021141991 A CNA021141991 A CN A021141991A CN 02114199 A CN02114199 A CN 02114199A CN 1466172 A CN1466172 A CN 1466172A
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- back side
- chip
- technology
- eutectic welding
- side metallization
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Abstract
This invention discloses a technology of an eutectic welding back moralization including positive protection, back thinner, back polish, cleaning evaporated alloy. This method is to coat by evaporation a layer of Au arsenate on the back of a tube core solving the problem of presenting rectification characteristic when contacting by ordinary metals with silicon utilizing the character of small resistance when contacting by Au with As to get good ohmic contact when leading-in wire. Chips processed by this technology suit the automatic welding technology without welding materials of 9000 series small signal tube cores.
Description
Technical field
The invention belongs to semiconductor device and integrated circuit processing technique, is the silicon device back side metallization technology.Back side metallization technology for eutectic welding particularly.
The back face metalization system is a transistorized important component part.It has two aspect functions, is bigger current path on the one hand, and it is again the path of a large amount of heat transferred heat radiations that transistor collector produced on the other hand, so the back face metalization system has very big influence to transistorized Performance And Reliability.It is little that good back face metalization system requirements has an ohmic contact resistance, the low and good reliability of contact heat resistance.From good electric property will be arranged,, require usually to select for use: the 1. lower metal material of schottky barrier height in order to form good Ohmic contact with silicon substrate; 2. the low metal of contact resistance; 3. high-dopant concentration backing material; 4. the substrate in high complex centre.In order to make the transistor back metal layer have good heat-conducting and reliability, reduce the thermal stress of silicon and back face metalization interlayer as far as possible.We know that when transistor was in the discontinuous operation state, device experienced periodic high temperature and chilling process, has formed thermal cycle.Because the coefficient of linear expansion difference between silicon, scolder and the base layers of material of transistor inside, in thermal cycle, internal system has produced thermal stress, and thermal resistance increases, and makes the transistor local overheating and loses efficacy.Because the difference of the coefficient of linear expansion between the stress of metal system and silicon substrate and each metal layer material is directly proportional.The back face metalization system that is used for practical devices at present, its structure generally are made up of three parts: ohmic contact layer, diffusion impervious layer and conductive layer (but this layer can be divided into layer and antioxidation coating again).
Summary of the invention
The purpose of this invention is to provide a kind of back side metallization technology for eutectic welding, solve common metal and be the problem of rectification characteristic, so that when lead-in wire, can obtain good Ohmic contact with the silicon contact.
The object of the present invention is achieved like this: back side metallization technology for eutectic welding is characterized in that it may further comprise the steps:
1, front protecting: be to stick layer protecting film in the front of silicon chip;
2, thinning back side: be that chip back is thinned to desired thickness;
3, polished backside: be that the affected layer that abrasive disc produces is removed;
4, clean: the chip after will polishing cleans up;
5, evaporation: under vacuum condition, make and plate one deck arsenic gold on the burnishing surface.
The present invention can also adopt the alloy technique step, promptly makes the arsenic gold carry out alloy with chip under certain temperature and nitrogen atmosphere condition.
The present invention utilizes arsenic gold and the little characteristics of silicon contact resistance, at the back side of tube core evaporation last layer arsenic gold, has solved common metal and has been the problem of rectification characteristic with the silicon contact, so that can obtain good Ohmic contact when lead-in wire.The chip that utilizes this technology to make simultaneously is suitable for the solderless automatic soldering technique of tube cores such as 9000 serial small-signals.
Embodiment
Back side metallization technology for eutectic welding is characterized in that it may further comprise the steps:
1, front protecting: be to stick layer protecting film in the front of silicon chip;
2, thinning back side: be that chip back is thinned to desired thickness;
3, polished backside: be that the affected layer that abrasive disc produces is removed;
4, clean: the chip after will polishing cleans up;
5, evaporation: under vacuum condition, make and plate one deck arsenic gold on the burnishing surface.
Present embodiment can also adopt the alloy technique step, promptly makes the arsenic gold carry out alloy with chip under certain temperature and nitrogen atmosphere condition.
Claims (2)
1, back side metallization technology for eutectic welding is characterized in that it may further comprise the steps:
(1), front protecting: be to stick layer protecting film in the front of silicon chip;
(2), thinning back side: be that chip back is thinned to desired thickness;
(3), polished backside: be that the affected layer that abrasive disc produces is removed;
(4), clean: the chip after will polishing cleans up;
(5), evaporation: under vacuum condition, make and plate one deck arsenic gold on the burnishing surface.
2, back side metallization technology for eutectic welding according to claim 1 is characterized in that it also comprises this alloy technique step, promptly makes the arsenic gold carry out alloy with chip under certain temperature and nitrogen atmosphere condition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021141991A CN100454492C (en) | 2002-06-13 | 2002-06-13 | Back side metallization technology for eutectic welding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021141991A CN100454492C (en) | 2002-06-13 | 2002-06-13 | Back side metallization technology for eutectic welding |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1466172A true CN1466172A (en) | 2004-01-07 |
| CN100454492C CN100454492C (en) | 2009-01-21 |
Family
ID=34141983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021141991A Expired - Fee Related CN100454492C (en) | 2002-06-13 | 2002-06-13 | Back side metallization technology for eutectic welding |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100454492C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070173045A1 (en) | 2006-01-23 | 2007-07-26 | Mitsubishi Electric Corporation | Method of manufacturing semiconductor device |
| CN102593010A (en) * | 2012-03-01 | 2012-07-18 | 长电科技（滁州）有限公司 | Chip back side drape tin eutectic technology and loading method thereof |
| CN103985646A (en) * | 2014-05-15 | 2014-08-13 | 中国电子科技集团公司第十三研究所 | Method for chip sintering by replacing hydrogen furnace |
| CN104766799A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Field effect transistor manufacturing method and corresponding field effect transistor |
| CN113299621A (en) * | 2020-01-02 | 2021-08-24 | 南京市产品质量监督检验院 | Lightly doped n-type silicon wafer back metallization structure and manufacturing process thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DD139498B1 (en) * | 1978-10-23 | 1984-12-05 | Lemke Heinz Dr Dipl Phys | METHOD FOR CONTACTING SEMICONDUCTOR MATERIALS |
| JPH0878337A (en) * | 1994-09-02 | 1996-03-22 | Fujitsu Ltd | Manufacture of semiconductor device |
-
2002
- 2002-06-13 CN CNB021141991A patent/CN100454492C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070173045A1 (en) | 2006-01-23 | 2007-07-26 | Mitsubishi Electric Corporation | Method of manufacturing semiconductor device |
| US8183144B2 (en) | 2006-01-23 | 2012-05-22 | Mitsubishi Electric Corporation | Method of manufacturing semiconductor device |
| CN102593010A (en) * | 2012-03-01 | 2012-07-18 | 长电科技（滁州）有限公司 | Chip back side drape tin eutectic technology and loading method thereof |
| CN104766799A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Field effect transistor manufacturing method and corresponding field effect transistor |
| CN104766799B (en) * | 2014-01-07 | 2018-07-06 | 北大方正集团有限公司 | A kind of preparation method of field-effect transistor and corresponding field-effect transistor |
| CN103985646A (en) * | 2014-05-15 | 2014-08-13 | 中国电子科技集团公司第十三研究所 | Method for chip sintering by replacing hydrogen furnace |
| CN103985646B (en) * | 2014-05-15 | 2017-05-03 | 中国电子科技集团公司第十三研究所 | Method for chip sintering by replacing hydrogen furnace |
| CN113299621A (en) * | 2020-01-02 | 2021-08-24 | 南京市产品质量监督检验院 | Lightly doped n-type silicon wafer back metallization structure and manufacturing process thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100454492C (en) | 2009-01-21 |
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| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: HENGYANG TRANSISTOR CO., LTD. Free format text: FORMER OWNER: HENGYANG KEJING MICROTRONICS CO., LTD. Effective date: 20090619 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20090619 Address after: Yanfeng District in Hunan province Hengyang City Baishazhou No. seven Jia Tang Yi Patentee after: Hengyang Transistor Co., Ltd. Address before: Hunan city in Hengyang province Yi Jia Tang No. seven Patentee before: Hengyang Kejing Microelectronic Co., Ltd. |
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090121 Termination date: 20100613 |