CN1466147A - Control time pulse generator and control time pulse generation method for high-speed sensing amplifier - Google Patents
Control time pulse generator and control time pulse generation method for high-speed sensing amplifier Download PDFInfo
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- CN1466147A CN1466147A CNA021402515A CN02140251A CN1466147A CN 1466147 A CN1466147 A CN 1466147A CN A021402515 A CNA021402515 A CN A021402515A CN 02140251 A CN02140251 A CN 02140251A CN 1466147 A CN1466147 A CN 1466147A
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Abstract
The invention is a kind of control pulse generator and the generating method for high-speed sensing amplifier. The generation of the control pulse not only uses RC delay and logic gate delay, but also combines the reference sensing delay generated by the reference sensing amplifier, so it has good tracing effect in high-speed sensing amplifier, in spite of the process dead angle, temperature and voltage alteration.
Description
Technical field
The present invention relates to control clock pulse generator (control clock generator), particularly about a kind of control clock pulse generator and control clock pulse generation methods that is used for high speed sensing amplifier (sense amplifierr).
Background technology
Typically, sensing amplifier is used to read the state (" 0 " or " 1 ") of storage unit (memory cell) in the memory array (for example ROM (read-only memory)).A read-only memory array may comprise millions of storage unit and be arranged in row and the row, the source electrode of each storage unit in delegation can be connected to a capable source electrode line, and sensing amplifier read selected storage unit during, selected the capable source electrode line of storage unit can be received reference potential or ground connection.The drain of each storage unit in delegation is connected to a bit line (bit line) independently, also claims row drain line, and sensing amplifier read selected storage unit during, selected the capable drain line of storage unit to be connected to the input of this sensing amplifier.The control grid of each storage unit in row is connected to a character line, and read selected storage unit during, this is selected the character line (word line) of storage unit to be connected to the voltage that is predetermined.
During read operation, flow through the electric current and the reference current that are selected storage unit and compare, selected storage unit whether by sequencing " 0 " or " 1 " with decision.Reference circuit is connected to the input of a current sense amplifier, and the output of this current sense amplifier is connected to a side of differential amplifier.When being selected storage unit to be read, this differential amplifier relatively output voltage of this current sense amplifier is connected the output voltage of the current sense amplifier that is selected storage unit with another.If reference circuit comprise a storage unit its in essence with to be read storage unit identical, for reaching a reference current between turned to being selected memory cell current and being turned to being selected between the memory cell current of " 1 " by formula of " 0 " by program, balance that usually must the break current sensing amplifier.
In sensing amplifier, the accurate control of the sequential (timing) of control clock pulse is one of condition that reaches high speed operation, yet, because different processing procedure dead angle, temperature and voltage makes the control clock pulse lack good trace ability and cause the speed of sensing amplifier to be difficult to promote.Giving the United States Patent (USP) of Yang Nianzhao with reference to promulgation is example No. 5771196, and its control circuit comprises three parts, and promptly pulse (AddressTransition Pulse is shifted in the address; ATP) generator, precharge (precharge) signal PCB generator and breech lock (latch) signal LATB generator, pulse signal ATP is shifted as the control clock pulse triggering source of precharging signal PCB, latch-up signal LATB and sensing amplifier enable signal SAB for example in its address, and its precharging signal PCB should draw high (pull-up) slower that in the middle of postponing for character wire delay and bit line.For dull and stereotyped ROM (read-only memory), its character wire delay draws high delay much larger than the bit line, therefore, usually by character wire delay master control precharging signal PCB, and the width of latch-up signal LATB should be greater than the width of precharging signal PCB, precharging signal PCB and the latch-up signal LATB mistiming between the two must select to make it to be enough to the correct data of breech lock, and it is relevant with the sensing time, and the sensing time directly is proportional to cell current.Latch-up signal LATB produces for added time delay by precharging signal PCB, be controlled by from childhood the cell current that displays (mini-array) this time delay, and, several nanoseconds (nanosecond) back of precharging signal PCB after latch-up signal LATB is high, to guarantee that correct data is by breech lock.In known techniques, control signal postpones to produce with reference to the cell current of little array for utilizing RC (being the character line) delay and logic gate.Because the trace ability of control clock pulse is not good under different processing procedure dead angle, temperature and voltage, therefore be difficult to improvement speed.
Summary of the invention
Purpose of the present invention, be to propose a kind of control clock pulse generator and control clock pulse generation methods that is used for the high speed sensing amplifier, the generation of its control clock pulse is in conjunction with RC delay, gate delay and come the reference sensing of self-reference sensing amplifier to postpone, thereby obtain good tracking effect, defy the change of processing procedure dead angle, temperature and voltage.
According to the present invention, a kind of clock pulse generator shifts pulse signal as the triggering source with the address, this clock pulse generator comprises that a RC delay circuit is to produce precharging signal, one circuit that postpones in conjunction with RC delay, gate delay and with reference to sensing is to produce latch-up signal, and bestow a gate delay from this latch-up signal generation sensing amplifier enable signal, wherein should postpone with reference to sensing be to produce from the reference sensing amplifier.In a preferred embodiment; the circuit of this generation latch-up signal comprises three paths; wherein main path is pulse signal to be shifted in this address postpone through RC; gate delay and postpone with reference to sensing; other two paths then are that the front and back of the delay of giving birth to for this predominating path add a guard time (guard time) at interval respectively; the latch-up signal that is produced to guarantee drops in the safe range; second path is that this precharging signal is postponed and gate delay through RC; make this latch-up signal be no more than a maximal value to the delay of precharging signal; the Third Road footpath then is pulse signal to be shifted in the address postpone and gate delay through RC, makes this latch-up signal be not less than a minimum value to the delay of precharging signal.
The present invention more provides a kind of sense amplifier of improvement, postpones to produce a sensing.This sensing amplifier comprises a reference line, to be coupled to the little array of analogue unit electric current.This sensing amplifier also separates precharge path and sense path, and with the MOS (Metal Oxide Semiconductor) of gate altogether to connecting precharge path and sense path respectively, adjust sensing time delay by changing the right dimension scale of this MOS.
The present invention also provides a kind of control clock pulse generation methods that is used for the high speed sensing amplifier, and it shifts pulse signal with the address is the triggering source, and this method comprises the following steps:
Pulse signal is shifted in this address bestow RC delay to produce a precharging signal;
Pulse signal is shifted in this address bestow that the 2nd RC postpones, first gate delay and postpones to determine a latch-up signal with reference to sensing; And
This breech lock is bestowed second gate delay to produce a sensing amplifier enable signal.
Said method more comprises bestows to this precharging signal that the 3rd RC postpones and the 3rd gate delay offers this latch-up signal at interval to produce first guard time.
Said method comprises that more pulse signal is shifted in this address bestows that the 3rd RC postpones and the 3rd gate delay offers this latch-up signal at interval to produce second guard time.
Said method comprises that more producing this postpones with reference to sensing, and more comprises the little array of sensing one analogue unit electric current.
Therefore, clock pulse generator of the present invention has very approximate actual sensing to postpone, and then provides good tracking effect for the high speed sensing amplifier with processing procedure dead angle, temperature or variation in voltage.
Description of drawings
Fig. 1 is the control circuit framework that produces control signal PCB, LATB and SAB in the sensing amplifier;
Fig. 2 is the preferred embodiment according to clock pulse generator of the present invention;
Fig. 3 is according to the preferred embodiment with reference to sensing amplifier of the present invention;
Fig. 4 is a typical R C delay circuit;
Fig. 5 is a typical gate delay circuit;
Fig. 6 is the sequential chart according to control signal of the present invention.
Embodiment
Fig. 1 is a calcspar, expression is used for the generation framework of the control signal of sensing amplifier, wherein the address is shifted pulse generator 10 and is produced address transfer pulse signal ATP according to wafer enable signal PCEB, produces three control signals such as precharging signal PCB, latch-up signal LATB and sensing amplifier enable signal SAB via clock pulse generator 20 again.
A preferred embodiment of clock pulse generator 20 is presented among Fig. 2, and it shifts pulse signal ATP with the address is that the triggering source produces required control clock pulse.In clock pulse generator 20, for producing precharging signal PCB, two input ends difference link addresses of Sheffer stroke gate (NAND gate) 21a shift pulse signal ATP and postpone the signal of 22a through RC, phase inverter (inverter) 23a is passed through in the output of Sheffer stroke gate 21a again, promptly produces precharging signal PCB.The circuit that produces latch-up signal LATB is comparatively complicated, it comprises three paths Path1, Path2 and Path3, determine by path P ath2 main time delay, after it shifts pulse signal ATP with the address and together passes through Sheffer stroke gate 21b and phase inverter 23b through the signal that RC postpones 22b, to export again through gate delay 26 and with reference to sensing and postpone 27, in addition, path P ath1 is with RC delay 24 of output signal process and the gate delay 25 of aforementioned phase inverter 23a, after path P ath3 shifts the address pulse signal ATP and postpones the signal process Sheffer stroke gate 21c and phase inverter 23c of 22c through RC, pass through gate delay 28 again, then in conjunction with three paths Path1, the delay that Path2 and Path3 produced, in detail, the above-mentioned reference sensing postpones 27 output through behind the phase inverter 29, together pass through rejection gate 30 and phase inverter 31 with the output of gate delay 28, together pass through Sheffer stroke gate 32 and phase inverter 33 with the output of aforementioned gate delay 25 again, to produce latch-up signal LATB.In aforesaid operation, the sequential of latch-up signal LATB is by path P ath2 master control, and two paths Path1 and Path3 make latch-up signal LATB guarantee to drop in the safe range for latch-up signal LATB adds guard time at interval in addition.In other words, the minimum delay of latch-up signal LATB is controlled by path P ath3, and maximum-delay is then controlled by path P ath1.Gate delay 34 is passed through in the output of aforementioned phase inverter 33 again, promptly produce sensing amplifier enable signal SAB.
For obtaining good tracking effect, above-mentionedly postpone 27 with reference to sensing and should be as far as possible postpone near the sensing of side circuit, Fig. 3 provides the sensing amplifier 40 of an improvement to reach this purpose.In sensing amplifier 40, precharge path and sense path are separated, sense path is set up to reference line DLref through MOS47,41 and 42 by power vd D and is formed, and precharge path is set up to reference line DLref through MOS48 and 42R by power vd D to form.Reference line DLref is connected to the little array of analogue unit electric current.NMOS42 is as transmission transistor, and is gate altogether with MOS42R, and by the output Vx institute bias voltage of rejection gate 43.Precharging signal PCB is applied on the gate of PMOS41 as the input IN of sensing amplifier 40.The voltage signal of sense node Vz is through by the inverter circuit that MOS44a, 44b, 45a and 45b formed, and the latch circuit of being made up of phase inverter 46a and 46b, and produces output signal OUT.In sense path, PMOS47 is connected to diode, so can reduce the voltage disturbance (swing) of sense node Vz and shorten the sensing time, and not disturb the precharge mechanisms of reference line DLref, and improve sensed speed by in safe range, increasing the size of NMOS42.PMOS (Positive MOS) 47 as diode also can use NMOS (Negative MOS) or vague and general type NMOS (Depletion mode NMOS) replacement instead.On the other hand, pre-charge current also can be adjusted, and it is reached by the size that changes NMOS48 and 42R, therefore, also can be subjected to good control to the precharge of reference line DLref, and not hinder sensed speed.The reference sensing of this sensing amplifier 40 can utilize the dimension scale that changes NMOS42 and 42R to adjust time delay.
RC among Fig. 2 postpones to use commercial or known any RC delay circuit is reached, and circuit shown in Figure 4 is an example.RC postpones 50 input IN and exports between the OUT to comprise a string phase inverter 51 and 52, resistance 53 and phase inverter 56 and 57, be connected MOS54 between the input end of phase inverter 56 and reference potential or the earth terminal, the latter's gate is connected to the input end of phase inverter 52, simultaneously, the input end of phase inverter 56 connects the electric capacity 55 that NMOS is connected into.
Gate delay among Fig. 2 also can use commercial or known any gate delay circuit is reached, and circuit shown in Figure 5 is an example.Comprise a string phase inverter 61,62,64 and 66 between the input IN of gate delay 60 and the output OUT, the input end of phase inverter 64 and output terminal respectively connect the electric capacity 63 and 65 that a NMOS is connected into.
Fig. 6 is a sequential chart, and its demonstration utilizes the relativeness between several signals that aforementioned circuit produces.At first, the address is shifted pulse signal ATP and is generated by response wafer enable signal PCEB and address signal ADD, and as previously described, other control signal is all this address transfer pulse signal of response ATP and generates.During T1, precharging signal PCB, latch-up signal LATB and sensing amplifier enable signal SAB are generated, and because the relation that postpones, the two width of latch-up signal LATB and sensing amplifier enable signal SAB is all long than the width of precharging signal PCB.During this period, the voltage of sense node Vz will be pulled up to the accurate position (because diode 47 cause between supply voltage VDD and PMOS41) that is lower than a diode turn-on voltage of supply voltage VDD, therefore, can be considered between precharge phase during this.Then, during T2, precharging signal PCB is high, and at this moment, the voltage of sense node Vz can be changed, and it will maintain high levle or reduce to predetermined accurate position according to the data that reads, and therefore, can be considered to during the sensing during this.During T3, latch-up signal LATB is high, and the latch circuit in the sensed amplifier 40 of data pins then, and sensing amplifier enable signal SAB is a little later high than latch-up signal LATB, is lockable to guarantee correct data.After during T3, sensing amplifier 40 can be closed reducing power consumption, and output driver is opened, thereby correct data appears on the data output bus, shown in the data output signal DOUT among the figure.
More than be in order to illustrate the present invention for the purpose of the narration that embodiment did, and unintentionally the present invention is limited, based on above explanation or to make an amendment or change from embodiments of the invention study be possible, therefore, technological thought attempt of the present invention should be decided by the claim scope and the equalization thereof of this case.
Claims (17)
1. control clock pulse generator that is used for the high speed sensing amplifier, it shifts pulse signal with an address is the triggering source, it is characterized in that: this control clock pulse generator comprises:
The one RC deferred mount produces a precharging signal to shift pulse signal according to this address;
The 2nd RC deferred mount with reference to the sensing deferred mount, produces a latch-up signal to shift pulse signal according to this address in conjunction with the first gate delay device and; And
The second gate delay device is to produce a sensing amplifier enable signal according to this latch-up signal.
2. clock pulse generator as claimed in claim 1 is characterized in that: more comprise the 3rd RC deferred mount and the 3rd gate delay device, offer this latch-up signal at interval to produce first guard time according to this precharging signal.
3. clock pulse generator as claimed in claim 1 is characterized in that: more comprise the 3rd RC deferred mount and the 3rd gate delay device, offer this latch-up signal at interval to produce second guard time according to this address transfer pulse signal.
4. clock pulse generator as claimed in claim 1 is characterized in that: wherein this first and second RC deferred mount is essentially identical.
5. clock pulse generator as claimed in claim 1 is characterized in that: wherein this first and second gate delay device is essentially identical.
6. clock pulse generator as claimed in claim 2 is characterized in that: wherein this first and the 3rd gate delay device is essentially identical.
7. clock pulse generator as claimed in claim 3 is characterized in that: wherein this first and the 3rd RC deferred mount is essentially identically, and this first and the 3rd gate delay device is essentially identical.
8. the sensing amplifier of an improvement, it is characterized in that: this sensing amplifier comprises:
One reference line is to be connected to the little array of an analogue unit electric current;
One sense path, be connected between first supply voltage and this reference line, this sense path connects this reference line via a side of a transmission transistor, the opposite side of this transmission transistor connects a sense node, this sense path comprises that more an input transistors connects this sense node, and this input transistors has a gate and connects an input signal;
One precharge path is connected between second source voltage and this reference line, and this precharge path is connected this reference line via one with the transistor of the common gate of this transmission transistor; And
One latch circuit connects this sense node, produces an output signal to respond this input signal.
9. sensing amplifier as claimed in claim 8 is characterized in that: comprise that more a bias voltage connects this transmission transistor and is total to the gate transistor.
10. sensing amplifier as claimed in claim 8 is characterized in that: wherein this sense path comprises that more a diode is between this first supply voltage and this input transistors.
11. sensing amplifier as claimed in claim 10 is characterized in that: wherein this diode is to be selected from the group that PMOS, NMOS and vague and general type NMOS form.
12. sensing amplifier as claimed in claim 8 is characterized in that: wherein this transmission transistor and altogether the transistorized dimension scale of gate determine sensing time delay.
13. a control clock pulse generation methods that is used for the high speed sensing amplifier, it shifts pulse signal with the address is the triggering source, and it is characterized in that: this method comprises the following steps:
Pulse signal is shifted in this address bestow RC delay to produce a precharging signal;
Pulse signal is shifted in this address bestow that the 2nd RC postpones, first gate delay and postpones to determine a latch-up signal with reference to sensing; And
This breech lock is bestowed second gate delay to produce a sensing amplifier enable signal.
14. method as claimed in claim 13 is characterized in that: more comprise and this precharging signal bestowed the 3rd RC postpones and the 3rd gate delay offers this latch-up signal at interval to produce first guard time.
15. method as claimed in claim 13 is characterized in that: comprise that more pulse signal is shifted in this address bestows that the 3rd RC postpones and the 3rd gate delay offers this latch-up signal at interval to produce second guard time.
16. method as claimed in claim 13 is characterized in that: comprise that more producing this postpones with reference to sensing.
17. method as claimed in claim 16 is characterized in that: the little array that more comprises sensing one analogue unit electric current.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021402515A CN100431038C (en) | 2002-07-02 | 2002-07-02 | Control time pulse generator and control time pulse generation method for high-speed sensing amplifier |
| CN 200610007376 CN100562940C (en) | 2002-07-02 | 2002-07-02 | A kind of sensing amplifier of improvement |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021402515A CN100431038C (en) | 2002-07-02 | 2002-07-02 | Control time pulse generator and control time pulse generation method for high-speed sensing amplifier |
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| CN 200610007376 Division CN100562940C (en) | 2002-07-02 | 2002-07-02 | A kind of sensing amplifier of improvement |
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| CN1466147A true CN1466147A (en) | 2004-01-07 |
| CN100431038C CN100431038C (en) | 2008-11-05 |
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| CN 200610007376 Expired - Lifetime CN100562940C (en) | 2002-07-02 | 2002-07-02 | A kind of sensing amplifier of improvement |
| CNB021402515A Expired - Lifetime CN100431038C (en) | 2002-07-02 | 2002-07-02 | Control time pulse generator and control time pulse generation method for high-speed sensing amplifier |
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| CN 200610007376 Expired - Lifetime CN100562940C (en) | 2002-07-02 | 2002-07-02 | A kind of sensing amplifier of improvement |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1904981B (en) * | 2005-06-16 | 2010-10-06 | 冲电气工业株式会社 | Display driver circuit |
| CN101359455B (en) * | 2007-08-03 | 2012-05-30 | 晨星半导体股份有限公司 | Priority control device |
| CN103137174A (en) * | 2011-12-01 | 2013-06-05 | 联华电子股份有限公司 | Voltage interpretation method of sense amplifier and bit line pair |
| CN103137174B (en) * | 2011-12-01 | 2016-12-14 | 联华电子股份有限公司 | Sensing amplifier and the voltage interpretation method of bit line pair |
| CN104217746B (en) * | 2013-05-30 | 2017-04-12 | 华邦电子股份有限公司 | Bias generator of reference storage cell and bias supply method |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090296506A1 (en) * | 2008-05-28 | 2009-12-03 | Macronix International Co., Ltd. | Sense amplifier and data sensing method thereof |
| US8315119B2 (en) * | 2009-02-26 | 2012-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sense amplifier scheme for low voltage SRAM and register files |
| CN101839941B (en) * | 2010-06-02 | 2012-03-14 | 西南交通大学 | Signal sensing amplifier |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5481500A (en) * | 1994-07-22 | 1996-01-02 | International Business Machines Corporation | Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories |
| JPH1186557A (en) * | 1997-09-11 | 1999-03-30 | Mitsubishi Electric Corp | Synchronous storage device and data reading method therefor |
-
2002
- 2002-07-02 CN CN 200610007376 patent/CN100562940C/en not_active Expired - Lifetime
- 2002-07-02 CN CNB021402515A patent/CN100431038C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1904981B (en) * | 2005-06-16 | 2010-10-06 | 冲电气工业株式会社 | Display driver circuit |
| CN101359455B (en) * | 2007-08-03 | 2012-05-30 | 晨星半导体股份有限公司 | Priority control device |
| CN103137174A (en) * | 2011-12-01 | 2013-06-05 | 联华电子股份有限公司 | Voltage interpretation method of sense amplifier and bit line pair |
| CN103137174B (en) * | 2011-12-01 | 2016-12-14 | 联华电子股份有限公司 | Sensing amplifier and the voltage interpretation method of bit line pair |
| CN104217746B (en) * | 2013-05-30 | 2017-04-12 | 华邦电子股份有限公司 | Bias generator of reference storage cell and bias supply method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100562940C (en) | 2009-11-25 |
| CN100431038C (en) | 2008-11-05 |
| CN1811979A (en) | 2006-08-02 |
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Granted publication date: 20081105 |