CN1462000A - Flash storage bridge connection, method and its application system - Google Patents

Flash storage bridge connection, method and its application system Download PDF

Info

Publication number
CN1462000A
CN1462000A CN 02121963 CN02121963A CN1462000A CN 1462000 A CN1462000 A CN 1462000A CN 02121963 CN02121963 CN 02121963 CN 02121963 A CN02121963 A CN 02121963A CN 1462000 A CN1462000 A CN 1462000A
Authority
CN
Grant status
Application
Patent type
Prior art keywords
memory
flash memory
buffer
instruction
read
Prior art date
Application number
CN 02121963
Other languages
Chinese (zh)
Inventor
唐迎华
韩文琪
沈璞如
Original Assignee
科统科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

A bridge device for NAND flash memory features that the buffer in said bridge device is used as cache for string part of address data in NAND flash memory and the cache control logic of said bridge device is used to judge if the data to be read is cache bit or cache miss. If it is cache hit, it can be directly responded. If it is cache miss, waiting is necessary. In the data reading procedure, the error in read data can be corrected by error correcting function in order to use NAND flash memory instead of NOR one for storing program and data, resulting in lower cost.

Description

闪存桥接装置、方法及其应用系统 Flash bridge device, method and application system

技术领域 FIELD

本发明涉及一种闪存桥接装置,且特别是涉及一种将NAND闪存仿真为NOR闪存使用的装置、方法及其应用系统。 The present invention relates to a flash bridge device, and more particularly relates to an apparatus for the simulation of a NAND flash memory using NOR flash memory, and application method.

为达上述及其它目的,本发明提供一种闪存桥接装置,适用于将一NAND闪存仿真为NOR闪存,以连接存储器接口,包括:缓冲区及控制逻辑。 To achieve the above and other objects, the present invention provides a flash memory bridge device, suitable for a NAND flash memory is a NOR flash emulation, the memory interface to be connected, comprising: a buffer and control logic. 其中,缓冲区用以储存对应于NAND闪存部分地址的数据。 Wherein the buffer corresponding to the NAND flash memory for storing a part of the address data. 控制逻辑耦接缓冲区,用以接收存储器指令,判断、执行及响应存储器指令的要求。 The control logic is coupled to the buffer for receiving an instruction memory, judgment, and execution of memory instructions required to respond.

本发明的较佳实施例中,控制逻辑还包括:第一缓冲存取(bufferaccess)单元、缓冲控制逻辑、第二缓冲存取单元、错误更正码(errorcorrection code)单元、区块地址转换(block address translation table)单元、NAND闪存控制单元及主控制逻辑单元。 Preferred embodiment of the present invention, the control logic further comprises: a first buffer access (bufferaccess) unit, a buffer control logic, the second buffer access unit, an error correction code (errorcorrection code) unit, address translation block (Block address translation table) unit, NAND flash memory control unit and main control logic unit. 其中,第一缓冲存取单元用以作为存储器接口与缓冲区的存取接口。 Wherein the first buffer unit is used as the memory access interface to access interface buffers. 缓冲控制逻辑耦接第一缓冲存取单元及缓冲区,用以控制读写缓冲区。 Buffer control logic coupled to the first buffer and the buffer access means, for controlling read and write buffers. 第二缓冲存取单元耦接缓冲控制逻辑,用以作为NAND闪存与缓冲区的存取接口。 The second buffer unit is coupled to the buffer access control logic, as for NAND flash memory and buffer access interface. 错误更正码单元耦接第二缓冲存取单元,用以更正自NAND闪存读取数据的错误。 ECC buffer unit is coupled to a second access unit for error correction of data read from the NAND flash memory. 区块地址转换单元耦接第二缓冲存取单元,用以将存储器指令之一逻辑地址,转换为实际地址。 Block address translation buffer means coupled to the second access unit to the memory, one instruction logical address into a real address. NAND闪存控制单元耦接错误更正码单元及区块地址转换单元,用以实际读写NAND闪存。 NAND flash memory unit is coupled to the control unit and the ECC block address translation unit for actual reading and writing a NAND flash memory. 主控制逻辑单元耦接第一缓冲存取单元、第二缓冲存取单元及区块地址转换单元,用以控制自NAND闪存读取未储存于缓冲区的数据、判断存储器指令欲读取的数据是否已储存于缓冲区及控制将暂存于缓冲区的数据逐步写入NAND闪存。 The main control logic unit coupled to the first buffer access unit, access unit and a second buffer block address translation unit for controlling reading data from the NAND flash memory is not stored in the buffer, it is determined to be a memory read instruction data It has been stored in the buffer and control data temporarily in the buffer gradually into the NAND flash memory.

其中,接收的存储器指令包括存储器读取指令、存储器写入指令及存储器配置(configure)指令。 Wherein the memory comprises a memory read instruction received instruction, the memory write instruction and memory configuration (Configure) instruction. 而此闪存桥接装置的控制逻辑支持8/16/32位的同步/异步存储器接口、及支持如4Mx8、16Mx8、32Mx8、64Mx8等不同的存储器配置(configuration),并支持其交错(interleave)及非交错(non-interleave)模式。 This logic controls the flash memory device supports 8/16/32 bit bridge synchronous / asynchronous memory interface, such as supports, and the like 4Mx8,16Mx8,32Mx8,64Mx8 different memory configuration (Configuration), which supports and interleaving (interleave) and non- interleaving (non-interleave) mode. 且于开机时,会将NAND闪存中储存的激活程序代码先行加载缓冲区中,以支持本地执行操作(execution inplace,简称XIP)。 And at the time of startup, the activation program code stored in the NAND flash memory will be loaded first buffer, performs an operation to support local (execution inplace, referred XIP).

本发明的较佳实施例中,将此闪存桥接装置应用于其应用系统中,此系统包括:存储器控制单元、NAND闪存及闪存桥接装置。 Preferred embodiment of the present invention, which is applied to this bridge device application flash system, the system comprising: a memory control unit, NAND flash memory and flash memory bridge device. 其中,存储器控制单元支持连接一NOR闪存的存储器接口。 Wherein the memory control unit is connected to a support NOR flash memory interface. NAND闪存用以储存系统使用的程序代码或数据。 Program code or NAND flash memory for storing data used by the system. 闪存桥接装置耦接存储器控制单元及NAND闪存,用以将NAND闪存仿真成为NOR闪存使用。 Flash memory device is coupled to the bridge control unit and a NAND flash memory, a NAND flash memory to the NOR flash emulation be used.

本发明另提供一种闪存桥接方法,适用于将一NAND闪存经由闪存桥接装置,仿真为NOR闪存,以连接存储器接口,包括下列步骤:首先接收一存储器指令;当此存储器指令为一存储器读取指令,且欲读取的数据已储存于闪存桥接装置中时,直接响应此存储器读取指令;当此存储器指令为一存储器读取指令,且欲读取的数据并未储存于闪存桥接装置中时,自NAND闪存读取数据,然后响应此存储器读取指令;当此存储器指令为一存储器写入指令时,将数据储存于闪存桥接装置中,再逐步转写入NAND闪存中;以及当此存储器指令为一存储器配置指令时,执行此存储器配置指令。 The present invention further provides a method of bridging a flash memory, a NAND flash memory applicable to the flash memory via a bridge device, NOR flash emulation, the memory interface to be connected, comprising the steps of: receiving a first instruction memory; read this memory when the instruction is a memory when the instruction to be read and the data stored in the flash memory in the bridge device, in response to this direct memory read instruction; when this memory is a memory read instruction command, and data to be read is not stored in the flash memory in the bridge device when, the data read from NAND flash memory, and responds to a memory read instruction; when this instruction is a memory write instruction memory, the data is stored in the flash memory in the bridge device, and then gradually turn written to the NAND flash memory; and when this The memory instruction is a memory instruction configuration, this execution configuration instruction memory. 其中当自NAND闪存读取数据时,会将读取数据的错误先行更正,以提高其可靠度。 Wherein when data is read from the NAND flash memory, a read error will be corrected first data, to improve its reliability.

本发明提供一种闪存桥接(bridge)装置、方法及其应用系统,是应用闪存桥接装置中提供的缓冲区作为高速缓存(cache),以储存NAND闪存中的部分地址数据,再以闪存桥接装置中提供的高速缓存控制逻辑(cache control logic),来判断欲读取的数据为高速缓存命中(cachehit),故可以直接响应,或高速缓存失败(cache miss),故必须等待,以及于数据读取过程中,运用错误更正码功能来更正读取数据的错误,以将NAND闪存仿真为NOR闪存来储存程序代码与数据,达到降低其制造成本,并维持其效能与可靠度的功效。 The present invention provides a flash bridge (Bridge) apparatus, method and system application, the application is provided a flash memory device bridge as a buffer cache (Cache), to store the address data portion of NAND flash memory, the flash and then to the bridge device cache control logic (cache control logic) are provided to determine the data to be read cache hit (CacheHit), it can be directly responsive or failed cache (cache miss), it is necessary to wait, and read the data taking process, the use of error correction codes to correct the error function read data to the NAND flash memory is a NOR flash emulation to store program code and data, to reduce manufacturing costs, and maintain their effectiveness and reliability of performance.

由上述的说明中可知,使用本发明提供的一种闪存桥接装置、方法及其应用系统,则可以使用NAND闪存,将其仿真成为NOR闪存,来储存程序代码与数据,不仅可降低其制造成本,更可维持其效能与可靠度。 From the above description, the use of a flash memory according to the present invention provides a bridging apparatus, methods and applications, you can use the NAND flash memory, the simulation will be NOR flash memory, to store program code and data, not only the manufacturing cost thereof can be reduced , but also to maintain its performance and reliability.

图中符号说明:110、210 存储器控制单元120 NOR闪存130、230 NAND闪存 DESCRIPTION OF REFERENCE NUMERALS: 110, 210, 120 NOR flash memory control unit 130,230 NAND flash

220、300 闪存桥接装置310 缓冲区320 控制逻辑325 第一缓冲存取单元330 缓冲控制逻辑335 第二缓冲存取单元340 错误更正码单元350 NAND闪存控制单元355 主控制逻辑单元S410~S480 方法步骤然而,因NOR闪存120与NAND闪存130相较,其价格昂贵许多,于是造成此种应用方式的制造成本无法降低,而若直接改以NAND闪存130来储存程序代码,则将影响系统的效能与可靠度。 Buffer control logic 220, 300 310 320 325 Flash bridging unit 330 accesses the first buffer 335 buffer control logic unit 340 accesses the second buffer ECC unit 350 NAND flash memory control unit 355 of the main control logic unit process steps S410 ~ S480 However, since the NOR flash and NAND flash memory 120 compared to 130, the price of much more expensive, thus causing the manufacturing cost can not be reduced to such an application mode, and if the direct change to the NAND flash memory to store program code 130, the system performance will be affected and reliability. 因此,本发明提供一种闪存桥接装置,以在微幅增加成本的情形下,大幅增进应用NAND闪存130来储存程序代码的应用的效能与可靠度。 Accordingly, the present invention provides a flash bridging device to a slight increase in cost in the case of significantly enhancing a NAND flash memory 130 to store the performance and reliability of the application program code.

请参看图2所示,其为根据本发明较佳实施例的闪存桥接装置应用示意图。 See Figure 2 shown, which is a schematic diagram of a flash memory application bridge device of the preferred embodiment of the present invention. 此应用除包括存储器控制单元210及用以储存程序代码的NAND闪存230外,还包括一闪存桥接(bridge)装置220。 This application includes, in addition to the memory control unit 210 and the NAND flash memory storing program codes outer 230, a flash memory further comprises a bridge (Bridge) 220. 此闪存桥接装置220耦接存储器控制单元210及NAND闪存230,用以将NAND闪存230仿真成为NOR闪存使用,以提供达到符合储存系统程序代码的效能与可靠度。 This flash memory bridge coupled to the memory device 220 the control unit 210 and the NAND flash memory 230, the NAND flash memory 230 to NOR flash emulation be used to provide the performance and reliability of the storage system to achieve compliance with the program code. 当然,本领域技术人员当可知晓,系统亦可经由适当的规划,将此NAND闪存230分别规划为储存程序代码的区域与储存数据的区域使用。 Of course, those skilled in the art may be aware of when the system can via a suitable programming, this programming NAND flash memory 230 are used as the area for storing the program code area with the stored data.

请参看图3所示,其为根据本发明较佳实施例的闪存桥接装置方块图。 See Figure 3, which is a bridge device according to a flash memory block diagram of one embodiment of the present invention. 此闪存桥接装置300包括:缓冲区310及控制逻辑320。 This flash memory bridge device 300 comprising: a buffer 310 and control logic 320. 其中,缓冲区310可以是由单一个或多个例如是FIFO或RAM的缓冲器所组成,其用以储存对应于NAND闪存230部分地址的数据,且当其由多个缓冲器组成时,并可交错使用(interleaved access),以增进系统效能。 Wherein, the buffer 310 may be a single or a plurality of, for example, a FIFO buffer RAM or the composition, which is used to store the address portion corresponding to the NAND 230 of the flash memory data, and when it is composed of a plurality of buffers, and can be staggered use (interleaved access), to enhance system performance. 控制逻辑320耦接缓冲区310,用以接收存储器指令,判断、执行及响应存储器指令的要求。 Control logic 320 is coupled to buffer 310 for receiving instruction memory, judgment, and execution of instruction memory required to respond.

其中控制逻辑320还包括:第一缓冲存取(buffer access)单元325、缓冲控制逻辑330、第二缓冲存取单元335、错误更正码(error correctioncode)单元340、区块地址转换(block address translation table)单元345、NAND闪存控制单元350及主控制逻辑单元355。 Wherein the control logic 320 further comprising: accessing a first buffer (buffer access) unit 325, buffer control logic 330, a second access buffer unit 335, the ECC (error correctioncode) unit 340, a block address translation (block address translation table) unit 345, NAND flash memory control unit 350 and the main control logic unit 355. 第一缓冲存取单元325用以作为图2的存储器控制单元210的存储器接口与缓冲区310的存取接口。 A first buffer memory access unit 325 of FIG. 2 is used as the memory interface unit 210 and buffer 310 of the interface access control. 缓冲控制逻辑330耦接第一缓冲存取单元325、第二缓冲存取单元335及缓冲区310,用以控制读写缓冲区310。 Buffer control logic 330 coupled to the first access buffer unit 325, the second buffer 335 and the buffer access unit 310, 310 for controlling the read and write buffers. 第二缓冲存取单元335耦接缓冲控制逻辑330,用以作为图2的NAND闪存230与缓冲区310的存取接口。 The second buffer unit 335 access the buffer control logic 330 is coupled to a NAND flash memory of FIG. 2 with the access interface 230 in the buffer 310. 错误更正码单元340耦接第二缓冲存取单元335,用以更正自图2的NAND闪存230读取数据的错误。 ECC buffer unit 340 is coupled to the second access unit 335 to correct the NAND 2 230 from FIG flash read data error. 区块地址转换单元345耦接第二缓冲存取单元335,用以将存储器指令之一逻辑地址,转换为实际地址。 Block address translation buffer unit 345 coupled to the second access unit 335 to the instruction memory, one logical address into a real address. NAND闪存控制单元350耦接错误更正码单元340及区块地址转换单元345,用以实际读写图2的NAND闪存230。 NAND flash memory control unit 350 is coupled to unit 340 and the ECC block address translation unit 345 to read the actual NAND flash memory 230 of FIG. 2. 主控制逻辑单元355耦接第一缓冲存取单元325、第二缓冲存取单元335及区块地址转换单元345,用以控制自图2的NAND闪存230读取未储存于缓冲区310的数据、判断存储器指令欲读取的数据是否已储存于缓冲区310及控制将暂存于缓冲区310的数据逐步写入图2的NAND闪存230。 Master control logic unit 355 coupled to the first access buffer unit 325, the second access unit 335 and buffer block address translation unit 345 for controlling the flash memory from FIG NAND 2 is not stored in the buffer 230 reads data 310 the data memory is determined whether the instruction to be read stored in the buffer 310 and temporarily stored in the control data buffer 310 gradually into the NAND flash memory 230 of FIG. 2. 当然,如本领域技术人员所知,其中的主控制逻辑单元355可以使用例如是微处理控制逻辑。 Of course, as those skilled in the art, where the main control logic unit 355 may use, for example, a microprocessor control logic.

其中因接收的存储器指令包括存储器读取指令、存储器写入指令及存储器配置(configure)指令,故可分为几种不同情况来加以说明。 Wherein the instructions received by the memory comprises a memory read instruction, the memory configuration and memory write instruction (Configure) instruction, it can be divided into several different situations will be described. 首先较佳地控制逻辑320于开机时,会将储存于NAND闪存230中的激活程序代码先行加载缓冲区310中,以提供支持本地执行操作(execution in place,简称XIP)功能,且于加载程序代码的过程中,会经错误更正码单元340更正数据的错误,以提高其可靠度。 Preferably the first program code to activate the control logic 320 to boot, will be stored in the NAND flash memory 230 is loaded in the first buffer 310 in order to provide local support to perform operations (execution in place, referred to the XIP) function, and in the loader the process code, the error will be corrected by the error correction code data unit 340 to improve its reliability.

当收到存储器读取指令时,主控制逻辑单元355会核对欲读取的数据是否已储存于缓冲区310中,如是则直接由缓冲区310中取出数据,以响应此存储器读取指令;如否则经区块地址转换单元345,将逻辑地址转换为实际对应的NAND闪存地址,并经NAND闪存控制单元350读取数据,于读取过程中,则经错误更正码单元340更正数据的错误,再经第二缓冲存取单元335及缓冲控制逻辑330存入缓冲区中310,然后才经由第一缓冲存取单元325响应欲读取的数据。 When a memory read command is received, the main control logic unit 355 will check whether the data to be read stored in the buffer 310, data is extracted directly from the case of the buffer 310, in response to this instruction a memory read; as otherwise, by the block address translation unit 345 converts a logical address to the actual address of the corresponding NAND flash memory, and NAND flash memory reads data 350 by the control unit, in the reading process, the error correction by the error correction decoding unit 340 of the data, buffer and then through the second access unit 335 and the buffer control logic 330 is stored in the buffer 310 before the response data buffer to be read via a first access unit 325. 此段等待过程可以有几种不同的作法,第一种为持续保留总线使用权至响应数据完成时;第二种为先行释放总线使用权,等待下次重试(retry)读取时即可快速响应数据;第三种为释放总线使用权,并于完成自NAND闪存230中读取数据,且储存于缓冲区310时,发出中断请求。 When the second bus use right is released first, waiting for the next retry (the retry) can be read; paragraph waiting process can have several different approaches, upon completion of a first duration in response to the bus use right reserved data fast response data; third bus use right is released, and the completion of the data read from the NAND flash memory 230, and stored in the buffer 310, an interrupt request. 本领域技术人员可配合需要,使用不同的等待方法,以增进系统的效能。 Those skilled in the art can be used with the need to use different methods to wait, to enhance system performance.

当收到存储器写入指令时,则经第一缓冲存取单元325及缓冲控制逻辑330,以将写入数据先行存入缓冲区310中,再经第二缓冲存取单元335及NAND闪存控制单元350逐步将数据存入NAND闪存230中。 When a memory write instruction is received, the access unit 325 via the first buffer and the buffer control logic 330, to write data stored in the first buffer 310, and then through the second buffer 335 and a NAND flash memory access control unit gradually unit 350 stores the data in the NAND flash memory 230. 而当收到存储器配置指令时,则由主控制逻辑单元355直接执行此存储器配置指令。 When the memory configuration command is received, the main control logic unit 355 by a direct memory configuration performs this instruction. 其中,此闪存桥接装置300支持8/16/32位的同步/异步存储器接口、及支持例如是4Mx8、16Mx8、32Mx8、64Mx8等不同的存储器配置,并支持其交错及非交错模式。 Wherein, the flash memory device 300 supports 8/16/32 bit bridge synchronous / asynchronous memory interface, and support, for example a different memory configuration 4Mx8,16Mx8,32Mx8,64Mx8 the like, and to support interlaced and non-interlaced mode.

由上述说明中,可归纳一种闪存桥接方法,适用于将一NAND闪存经由闪存桥接装置,仿真为NOR闪存,以连接存储器接口。 From the above description, the bridging method can be summarized A flash memory, a NAND flash memory is adapted to the bridge device via flash, NOR flash emulation, is connected to the memory interface. 此方法如图4的流程图所示,包括下列步骤:首先于S410步骤中接收一存储器指令;然后于步骤S420中判断存储器指令的种类,当此存储器指令为存储器读取指令,且于S430步骤中判断欲读取的数据已储存于闪存桥接装置中时,则至S450步骤直接响应此存储器读取指令;当此存储器指令为存储器读取指令,且于步骤S420中判断欲读取的数据并未储存于闪存桥接装置中时,则至步骤S440,以自NAND闪存读取数据,然后至S450步骤响应此存储器读取指令;当于步骤S420中判断存储器指令为存储器写入指令时,则至步骤S460,以将数据储存于闪存桥接装置中,再于步骤S470中,逐步将数据转写入NAND闪存中;以及当此存储器指令为存储器配置指令时,则至步骤S480执行此存储器配置指令。 This method flowchart shown in FIG. 4, comprising the steps of: receiving a first instruction in the memory in step S410; then determine the type of memory command in step S420, the memory when this instruction is a read instruction memory, and in step S430 when the read data is determined to be stored in the flash memory in the bridge device, the step S450 in response to this direct memory read instruction; when this instruction is a memory read instruction memory, and at step S420, the data to be read is determined and when the bridge is not stored in the flash memory device, then to the step S440, the NAND flash memory to read data from, and then to step S450 responds to a memory read instruction; determining when the memory is a memory write instruction command in step S420, to the step S460, the data stored in the flash memory to the bridge device, and then in step S470, the data is transferred gradually into the NAND flash memory; and when this instruction memory instructions are configured as a memory, then the step S480 to execute this instruction memory configuration. 其中当自NAND闪存读取数据时,会将读取数据的错误先行更正,以提高其可靠度。 Wherein when data is read from the NAND flash memory, a read error will be corrected first data, to improve its reliability.

由上述说明中可知,本发明应用闪存桥接装置中提供的快取控制逻辑,来判断欲读取的数据为储存区符合,可以直接响应,或储存区不符合,必须等待,以及运用错误更正码功能于数据读取过程中,更正读取数据的错误。 From the above description, the cache control logic of the present invention applied in a flash memory device of the bridge is provided to determine the data to be read is in line with the storage area can be directly in response, storage area or not, must wait, and the use of error correction code data read-in process, the data read error is corrected. 故其为将NAND闪存仿真为NOR闪存来储存程序代码与数据,不仅可降低其制造成本,更可维持其效能与可靠度。 Therefore, it is a NAND flash memory is a NOR flash emulation to store program code and data, can not only reduce the manufacturing costs, but also to maintain their effectiveness and reliability.

虽然本发明已以一较佳实施例揭露如上,然其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作各种的更动与润饰,因此本发明的保护范围当以权利要求书并结合说明书及附图所界定者为准。 While the invention has been disclosed a preferred embodiment of the above embodiment, they are not intended to limit the present invention, anyone skilled in the art, without departing from the spirit and scope of the present invention, may make various modifications and variations, Therefore, the scope of the present invention when in conjunction with the appended claims and their equivalents define the specification and drawings.

Claims (19)

  1. 1.一种闪存桥接装置,适用于将一NAND闪存仿真为一NOR闪存,以连接一存储器接口,包括:一缓冲区,用以储存对应于该NAND闪存部分地址的数据;以及一控制逻辑,耦接该缓冲区,用以接收一存储器指令,执行及响应该存储器指令的要求。 1. A flash memory bridge device, suitable for a NAND flash memory is a NOR flash emulation, is connected to a memory interface, comprising: a buffer for storing portion corresponding to the NAND flash memory address of the data; and a control logic, coupled to the buffer memory for receiving an instruction execution and instruction memory in response to the request.
  2. 2.如权利要求1所述的闪存桥接装置,其特征在于:该控制逻辑还包括:一第一缓冲存取单元,用以作为该存储器接口与该缓冲区的存取接口;一缓冲控制逻辑,耦接该第一缓冲存取单元及该缓冲区,用以控制读写该缓冲区;一第二缓冲存取单元,耦接该缓冲控制逻辑,用以作为该NAND闪存与该缓冲区的存取接口;一错误更正码单元,耦接该第二缓冲存取单元,用以更正自该NAND闪存读取数据的错误;一区块地址转换单元,耦接该第二缓冲存取单元,用以将该存储器指令的一逻辑地址,转换为一实际地址;一NAND闪存控制单元,耦接该错误更正码单元及该区块地址转换单元,用以实际读写该NAND闪存;以及一主控制逻辑单元,耦接该第一缓冲存取单元、该第二缓冲存取单元及该区块地址转换单元,用以控制自该NAND闪存读取未储存于该缓冲区的数据、判断 A buffer control logic; a first buffer access unit, the memory interface configured as a buffer with the access agent: a flash memory as claimed in claim bridging apparatus of claim 1, wherein: the control logic further comprises coupled to the first buffer and said buffer access means, for controlling the write buffer; buffer a second access unit, the buffer control logic coupled to the NAND flash memory as the buffer access interface; an error correction code unit, a second buffer coupled to the access unit for error correction from the NAND flash memory to read data; a tile address translation unit, coupled to the second buffer access unit, a memory instruction for the logical address is converted into a physical address; a NAND flash memory control unit, coupled to the error correction code block unit and the address translation unit for the actual reading and writing a NAND flash memory; and a main a control logic unit, coupled to the first buffer access unit, the access unit and the second buffer block address translation unit for controlling the read data is not stored in the buffer from the NAND flash memory, is determined 存储器指令欲读取的数据是否已储存于该缓冲区及控制将暂存于该缓冲区的数据逐步写入该NAND闪存。 Whether the data has been read memory instructions to be stored in the buffer and the control data stored temporarily in the buffer is written to the NAND flash gradually.
  3. 3.如权利要求1所述的闪存桥接装置,其特征在于:该存储器指令包括存储器读取指令、存储器写入指令及存储器配置指令。 Flash bridging device according to claim 1, wherein: the instruction comprises a memory read instruction memory, write instruction memory and instruction memory configuration.
  4. 4.如权利要求1所述的闪存桥接装置,其特征在于:该控制逻辑支持8/16/32位的同步/异步接口。 Flash memory bridge 4. The apparatus according to claim 1, wherein: the control logic supports synchronous / asynchronous interfaces 8/16/32 bits.
  5. 5.如权利要求1所述的闪存桥接装置,其特征在于:该控制逻辑支持如4Mx8、16Mx8、32Mx8、64Mx8等不同的存储器配置,并支持交错及非交错模式。 5. The flash memory device of the bridge according to claim 1, wherein: the control logic and the like to support such 4Mx8,16Mx8,32Mx8,64Mx8 different memory configurations and supports interlaced and non-interlaced mode.
  6. 6.如权利要求1所述的闪存桥接装置,其特征在于:该控制逻辑于开机时,会将该NAND闪存中储存的激活程序代码加载该缓冲区中。 6. The flash memory device of the bridge according to claim 1, wherein: the control logic at the time of power ON, the activator code stored in the NAND flash memory is loaded in the buffer.
  7. 7.如权利要求1所述的闪存桥接装置,其特征在于:该缓冲区是由多个缓冲器所组成,并可交错使用。 7. The flash memory device of the bridge according to claim 1, wherein: the buffer is composed of a plurality of buffers, and staggered use.
  8. 8.一种闪存桥接装置应用系统,包括:一存储器控制单元,该存储器控制单元支持连接一NOR闪存的一存储器接口;一NAND闪存,用以储存系统使用的程序代码;以及一闪存桥接装置,耦接该存储器控制单元及该NAND闪存,用以将该NAND闪存仿真成为该NOR闪存使用。 A flash memory application bridge device, comprising: a memory control unit, the memory control unit is connected to a support of a NOR flash memory interface; a NAND flash memory for storing program codes used by the system; flash memory and a bridge device, control means coupled to the memory and the NAND flash memory, the NAND Flash memory for the simulation of the NOR flash memory used.
  9. 9.如权利要求8所述的闪存桥接装置应用系统,其特征在于:该闪存桥接装置包括:一缓冲区,用以储存对应于该NAND闪存部分地址的数据;以及一控制逻辑,耦接该缓冲区,用以接收该存储器控制单元发出的一存储器指令,判断、执行及响应该存储器指令的要求。 9. The flash memory device of the bridge application system according to claim 8, wherein: the flash memory bridge device comprising: a buffer for storing portion corresponding to the NAND flash memory address of the data; and a control logic, coupled to the buffer, for receiving the memory control unit issues a command to the memory, judgment, and required to perform in response to the instruction memory.
  10. 10.如权利要求9所述的闪存桥接装置应用系统,其特征在于:该控制逻辑还包括:一第一缓冲存取单元,用以作为该存储器接口与该缓冲区的存取接口;一缓冲控制逻辑,耦接该第一缓冲存取单元及该缓冲区,用以控制读写该缓冲区;一第二缓冲存取单元,耦接该缓冲控制逻辑,用以作为该NAND闪存与该缓冲区的存取接口;一错误更正码单元,耦接该第二缓冲存取单元,用以更正自该NAND闪存读取数据的错误;一区块地址转换单元,耦接该第二缓冲存取单元,用以将该存储器指令的一逻辑地址,转换为一实际地址;一NAND闪存控制单元,耦接该错误更正码单元及该区块地址转换单元,用以实际读写该NAND闪存;以及一主控制逻辑单元,耦接该第一缓冲存取单元、该第二缓冲存取单元及该区块地址转换单元,用以控制自该NAND闪存读取未储存于该缓冲区的数 10. The flash memory device of the bridge application system according to claim 9, wherein: the control logic further comprises: buffering a first access unit, the memory interface configured as a buffer with the access agent; a buffer control logic, coupled to the first buffer and said buffer access means, for controlling the write buffer; buffer a second access unit, the buffer control logic coupled to the NAND flash memory as the buffer access interface region; an error correction code unit, a second buffer coupled to the access unit, configured to correct the errors from the NAND flash memory to the read data; a tile address translation unit, coupled to the second buffer access unit, a memory instruction for the logical address is converted into a physical address; a NAND flash memory control unit, coupled to the error correction code block unit and the address translation unit for the actual reading and writing a NAND flash memory; and a main logic control unit, coupled to the first buffer access unit, the access unit and the second buffer block address translation unit for controlling reading from the NAND flash memory is not stored in the buffer number 、判断该存储器指令欲读取的数据是否已储存于该缓冲区及控制将暂存于该缓冲区的数据逐步写入该NAND闪存。 Determining whether the instruction memory to be read has been stored in the data buffer and the data stored temporarily in the control of the buffer is written to the NAND flash gradually.
  11. 11.如权利要求9所述的闪存桥接装置应用系统,其特征在于:该存储器指令包括存储器读取指令、存储器写入指令及存储器配置指令。 11. The flash memory device of the bridge application system according to claim 9, wherein: the instruction comprises a memory read instruction memory, write instruction memory and instruction memory configuration.
  12. 12.如权利要求8所述的闪存桥接装置应用系统,其特征在于:该闪存桥接装置支持8/16/32位的同步/异步接口。 12. The flash memory device of the bridge application system according to claim 8, wherein: the flash bridge device supports synchronous / asynchronous interfaces 8/16/32 bits.
  13. 13.如权利要求8所述的闪存桥接装置应用系统,其特征在于:该闪存桥接装置支持如4Mx8、16Mx8、32Mx8、64Mx8等不同的存储器配置,并支持交错及非交错模式。 13. The flash memory device of the bridge application system according to claim 8, wherein: the support means such as a flash memory bridge 4Mx8,16Mx8,32Mx8,64Mx8 other variety of memory configurations, and support interleaved and non-interleaved mode.
  14. 14.如权利要求8所述的闪存桥接装置应用系统,其特征在于:该闪存桥接装置于开机时,会将该NAND闪存中储存的激活程序代码先行加载。 14. The flash memory device of the bridge application system according to claim 8, wherein: the bridge device to boot flash memory, will activate the program code stored in first NAND flash memory loading.
  15. 15.一种闪存桥接方法,适用于将一NAND闪存经由一闪存桥接装置,仿真为一NOR闪存,以连接一存储器接口,包括下列步骤:接收一存储器指令;当该存储器指令为一存储器读取指令,且欲读取的数据已储存于该闪存桥接装置中时,响应该存储器读取指令;当该存储器指令为该存储器读取指令,且欲读取的数据并未储存于该闪存桥接装置中时,自该NAND闪存读取数据,然后响应该存储器读取指令;当该存储器指令为一存储器写入指令时,将该数据储存于该闪存桥接装置中,再逐步转写入该NAND闪存中;以及当该存储器指令为一存储器配置指令时,执行该存储器配置指令。 15. A method for bridging a flash memory, a NAND flash memory is adapted to the bridge device via a flash memory, a NOR flash emulation, is connected to a memory interface, comprising the steps of: receiving a memory command; when the memory is a memory read instruction when the instruction to be read and the data stored in the flash memory bridge device in response to the memory read instruction; instruction memory when the memory read instruction, and is not to be read for the data stored in the flash memory bridge device when, the data read from the NAND flash memory, and in response to the memory read instruction; memory when the instruction is a memory write instruction, the data stored in the flash memory in the bridge device, and then gradually turn written to the NAND flash memory ; and a storage configuration when the instruction is a memory instruction, execute the instruction memory configuration.
  16. 16.如权利要求15所述的闪存桥接方法,其特征在于:当自该NAND闪存读取数据时,会将读取数据的错误先行更正。 16. The flash memory bridging method according to claim 15, wherein: when data is read from the NAND flash memory, the erroneous data correction will be read first.
  17. 17.一种闪存桥接方法,适用于将一NAND闪存经由一闪存桥接装置,仿真为一NOR闪存,以连接一存储器接口,包括下列步骤:接收一存储器指令;当该存储器指令为一存储器读取指令,且欲读取的数据已储存于该闪存桥接装置中时,响应该存储器读取指令;以及当该存储器指令为该存储器读取指令,且欲读取的数据并未储存于该闪存桥接装置中时,自该NAND闪存读取数据,然后响应该存储器读取指令。 17. A method for bridging a flash memory, a NAND flash memory applicable to the flash memory via a bridge device, a NOR flash emulation, is connected to a memory interface, comprising the steps of: receiving a memory command; when the memory is a memory read instruction when the instruction to be read and the data stored in the flash memory bridge device in response to the memory read instruction; and when the memory read instruction memory instructions to be read and that data is not stored in the flash memory bridge when the apparatus, data read from the NAND flash memory, and in response to the memory read instruction.
  18. 18.如权利要求17所述的闪存桥接方法,其特征在于:当自该NAND闪存读取数据时,会将读取数据的错误先行更正。 18. The flash memory bridging method according to claim 17, wherein: when data is read from the NAND flash memory, the erroneous data correction will be read first.
  19. 19.一种闪存桥接方法,适用于将一NAND闪存经由一闪存桥接装置,仿真为一NOR闪存,以连接一存储器接口,包括下列步骤:接收一存储器指令;当该存储器指令为一存储器写入指令时,将该数据储存于该闪存桥接装置中,再逐步转写入该NAND闪存中;以及当该存储器指令为一存储器配置指令时,执行该存储器配置指令。 19. A method for bridging a flash memory, a NAND flash memory applicable to the flash memory via a bridge device, a NOR flash emulation, is connected to a memory interface, comprising the steps of: receiving a memory command; when the memory is a memory write instruction instruction, the bridging data is stored in the flash memory device, and then gradually turn written to the NAND flash memory; and a storage configuration when the instruction is a memory instruction, execute the instruction memory configuration.
CN 02121963 2002-05-29 2002-05-29 Flash storage bridge connection, method and its application system CN1462000A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 02121963 CN1462000A (en) 2002-05-29 2002-05-29 Flash storage bridge connection, method and its application system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 02121963 CN1462000A (en) 2002-05-29 2002-05-29 Flash storage bridge connection, method and its application system

Publications (1)

Publication Number Publication Date
CN1462000A true true CN1462000A (en) 2003-12-17

Family

ID=29743097

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 02121963 CN1462000A (en) 2002-05-29 2002-05-29 Flash storage bridge connection, method and its application system

Country Status (1)

Country Link
CN (1) CN1462000A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100595738C (en) 2008-09-28 2010-03-24 东南大学 Software controllable Cache implementing method facing flush type application
WO2010148922A1 (en) * 2009-11-24 2010-12-29 中兴通讯股份有限公司 Method and device for accessing data in nand flash memory
CN102103566A (en) * 2009-12-18 2011-06-22 Nxp股份有限公司 Flash memory-interface

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100595738C (en) 2008-09-28 2010-03-24 东南大学 Software controllable Cache implementing method facing flush type application
WO2010148922A1 (en) * 2009-11-24 2010-12-29 中兴通讯股份有限公司 Method and device for accessing data in nand flash memory
CN101702139B (en) 2009-11-24 2011-11-30 中兴通讯股份有限公司 A method and apparatus for accessing data in the FLASH Nand
CN102103566A (en) * 2009-12-18 2011-06-22 Nxp股份有限公司 Flash memory-interface

Similar Documents

Publication Publication Date Title
US7055000B1 (en) Disk drive employing enhanced instruction cache management to facilitate non-sequential immediate operands
US6370611B1 (en) Raid XOR operations to synchronous DRAM using a read buffer and pipelining of synchronous DRAM burst read data
US6374337B1 (en) Data pipelining method and apparatus for memory control circuit
US4763242A (en) Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility
US6098190A (en) Method and apparatus for use of a host address to validate accessed data
US7296143B2 (en) Method and system for loading processor boot code from serial flash memory
US6772281B2 (en) Disk drive for selectively satisfying a read request from a host computer for a first valid data block with a second valid data block
US5909592A (en) Method in a basic input-output system (BIOS) of detecting and configuring integrated device electronics (IDE) devices
US4942519A (en) Coprocessor having a slave processor capable of checking address mapping
US5150465A (en) Mode-selectable integrated disk drive for computer
US5634099A (en) Direct memory access unit for transferring data between processor memories in multiprocessing systems
US20090049222A1 (en) PCI Express-Compatible Controller And Interface For Flash Memory
US20060195650A1 (en) Method to detect NAND-flash parameters by hardware automatically
US6230259B1 (en) Transparent extended state save
US20040230738A1 (en) Apparatus and method for controlling execute-in-place (XIP) in serial flash memory, and flash memory chip using the same
US7234049B2 (en) Computer system with NAND flash memory for booting and storage
US6073206A (en) Method for flashing ESCD and variables into a ROM
US20040068644A1 (en) Booting from non-linear memory
US6182207B1 (en) Microcontroller with register system for the indirect accessing of internal memory via auxiliary register
US20020184579A1 (en) System and method for recognizing and configuring devices embedded on memory modules
US20040059848A1 (en) Device for automatically switching endian order
JP2003015929A (en) Control method for nonvolatile memory
US20090150588A1 (en) Hard Disk Drive Cache Memory and Playback Device
CN101271396A (en) Electronic device and method for on-line updating firmware
US6049852A (en) Preserving cache consistency in a computer system having a plurality of memories with overlapping address ranges

Legal Events

Date Code Title Description
C06 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)