CN1453844A - Ferroelectric capacitor with gap - Google Patents
Ferroelectric capacitor with gap Download PDFInfo
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- CN1453844A CN1453844A CN 02118154 CN02118154A CN1453844A CN 1453844 A CN1453844 A CN 1453844A CN 02118154 CN02118154 CN 02118154 CN 02118154 A CN02118154 A CN 02118154A CN 1453844 A CN1453844 A CN 1453844A
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Abstract
The present invention discloses one kind of ferroelectric capacitor with gap and its making process. The ferroelectric capacitor has one diffusion barrier, and during high temperature process, the barrier protects tungsten plug by preventing high temperature oxygen from diffusing and reacting with tungsten plug to form tungsten oxide layer. On the other hand, the conductor gap in the structure of the present invention makes the present invention possess self-aligning effect. That is, by means of the electric connection with the conductor layer via the gap structure, the conductor layer is made to connect with the contact window without affecting the electric performance.
Description
Technical field
The present invention system relates to a kind of semiconductor subassembly and manufacturing technology, and it is special relevant with the manufacturing of a kind of ferroelectric capacitor (Ferroelectric capacitor).
Background technology
In recent years, non-volatility ferroelectric internal memory (FRAM) causes the attention of all circles at large, and constantly develops its manufacturing technology.In non-volatility ferroelectric internal memory, the capacitor of each ferroelectric storage cell all has the dielectric layer of one deck ferroelectric thin film as capacitor, in order to store data.
Along with the progress that semi-conductor industry continues, the ferroelectric internal memory assembly is widely used in the integrated circuit.Generally speaking, an arbitrary access ferroelectric internal memory has many memory cell (memorycell), and its memory cell is made of a ferroelectric capacitor and transistor usually, in order to store the signal of (bit).Wherein, transistor drain or source electrode are connected with an end of ferroelectric capacitor, and the other end of ferroelectric capacitor then is connected with reference potential, then are connected with bit line (bit line) and character line (word line) respectively with grid as for the transistorized other end.Therefore when making the memory cell of arbitrary access ferroelectric internal memory, the technology that has often also comprised the transistor AND gate ferroelectric capacitor, and contact with the electrical of transistorized source area or drain region by capacitor, digital information is stored in the capacitor, utilizes transistor, bit line and character line array to come the numerical data of access ferroelectric condenser again.
Yet along with the development of very lagre scale integrated circuit (VLSIC) (ULSI), for trying to achieve tool competition electric capacity that is worth and the balance that occupies minimum space, the improvement of technology is just indispensable.Wherein a kind of mode be with capacitor architecture on higher position, so, then general electric pole plate just and storage node reel (warp) mutually each other and form generally alleged stack capacitor (stackedcapacitor).
The capacitor of the ferroelectric storage cell of tradition stacking-type as shown in Figure 1.Structure with a transistor/ferroelectric condenser (1T/1C) is an example, its formation method generally is to form after transistorized grid 12, gate dielectric 14 and the source/drain regions 16 on the semiconductor-based end 10 earlier, cover last layer dielectric layer 20 again, in dielectric layer 20, form contact hole tungsten plug (W-plug) 22 then and be connected to one of source/drain regions 16, on contact hole tungsten plug 22, form ferroelectric capacitor more at last.Traditional ferroelectric capacitor system forms ferroelectric material film 26, and form top electrode 28 on ferroelectric thin film 26 with " planar fashion " storehouse from bottom to top on bottom electrode 24, wherein above-mentioned ferroelectric material film 26 is generally Pb/Zr/TiO
3Alloy.
Though the ferroelectric capacitor of this kind stacking-type is to economize area most; but it needs a high-temperature technology when forming ferroelectric material film 26, this technological temperature can be higher than 500 ℃ usually; because if this technological temperature is not high enough, the crystalline quality of ferroelectric material film 26 can be influenced.Yet under this high-temperature technology, because ferroelectric material film 26 comprises TiO
3, when carrying out this high-temperature technology, can suffer from the problem that the high temperature oxygen diffusion causes tungsten plug 22 oxidations.To this solution, have the polysilicon plug of use to replace tungsten plug traditionally, reduce the oxidation possibility, but because the polysilicon plug resistance is higher, therefore formed ferroelectric internal memory will be not as using tungsten plug in general performance.And another kind of method is to reduce technological temperature, to avoid producing the high temperature oxygen diffusion, still with the method, can cause the characteristic variation of ferroelectric capacitor.Therefore, the utmost point needs the invention of an improvement method to solve above-mentioned problem.
Summary of the invention
In above-mentioned background of invention; plane stack capacitor structure usually can be supervened the high temperature oxygen diffusion in forming process; and cause the problem of tungsten plug oxidation; though can use polysilicon plug to replace tungsten plug; reduce the oxidation possibility; but, can cause whole electrical performance variation because the polysilicon plug resistance is higher.Therefore, the invention provides a kind of ferroelectric capacitor structure and manufacture method thereof, reduce the problem that produces the high temperature oxygen diffusion in the manufacture process and cause the tungsten plug oxidation.
The invention provides a kind of ferroelectric capacitor, its framework is in the semiconductor substrate.The structure of this ferroelectric capacitor comprises a conductor gap, and gap architecture and comes to electrically connect with transistorized source/drain regions by this conductor layer and contact hole tungsten plug on a conductor layer between this conductor, by the electrical operation of transistor controls electric capacity.Simultaneously, accompany a diffusion impervious layer, when carrying out high-temperature technology, can protect tungsten plug above the conductor layer and between capacitor lower electrode, prevent that high temperature oxygen from diffusing into and with the tungsten plug reaction, form one deck tungsten oxide layer.
The present invention also provides the manufacture method of a kind of tool conductor gap ferroelectric capacitor.At first form first conductor layer, one deck barrier layer, lower electrode layer and ferroelectric material layer on the semiconductor-based end in regular turn, this ferroelectric material layer is such as being lead zirconium titanate (PZT), as the dielectric layer of capacitor.Then on ferroelectric material layer, form a patterning photoresist layer, and serve as a cover curtain etch stop layer, lower electrode layer and ferroelectric material layer with this layer.Then deposit second conductor layer, utilize dry ecthing to carry out the anisotropic etching of this layer simultaneously, form a conductor clearance layer.Then comprehensive deposition one layer insulating in the surface utilizes another patterning photoresist layer for the cover curtain carries out etching to this insulating barrier simultaneously, exposes the ferroelectric material laminar surface, then deposits the top electrode of the 3rd conductive layer as ferroelectric capacitor.
Utilize method of the present invention and structure, can solve institute's high temperature oxygen of supervening diffusion in the ferroelectric capacitor manufacture process traditionally, and cause the problem of tungsten plug oxidation.Use method of the present invention and structure simultaneously and can not need use polysilicon plug to replace tungsten plug,, therefore can't influence the electrical performance of whole ferroelectric internal memory to reduce the oxidation possibility.
Description of drawings
Details by preferred embodiment among following the present invention is described, and can better understanding be arranged to purpose of the present invention, viewpoint and advantage.Simultaneously with reference to following graphic being illustrated of the present invention:
Fig. 1 is existing a kind of ferroelectric capacitor with stack architecture;
Fig. 2 A to Fig. 2 E is the technology generalized section with conductor gap ferroelectric capacitor of the present invention;
Fig. 2 F is the another kind of structural representation with conductor gap ferroelectric capacitor of the present invention; And
Fig. 3 is used in the middle of the resistive internal memory for structure of the present invention.
Figure number is to as directed: 10 12 grids, 14 gate dielectrics, 16 source/drain regions, 20 insulating barriers, 22 contact hole connectors, 24 bottom electrodes, 26 ferroelectric layers, 28 top electrodes, 30 insulating barriers, the 100 semiconductor-based end, 102 grids, 104 gate dielectrics, 106 source/drain regions, 108 tungsten adhesion layers, 110 insulating barriers, 112 contact hole connectors, 114 conductor layers of the semiconductor-based end
116 diffusion retaining layers, 118 bottom electrode
120 ferroelectric material layers, 122 conductor gaps
124 dielectric layers, 126 conductor layers
128 openings, 130 chalcogenides
Embodiment
Not limiting under spirit of the present invention and the range of application, below use an embodiment, introduce enforcement of the present invention; Those skilled in the art, after understanding spirit of the present invention, should be in various ferroelectric memory cells with the manufacture method of this kind ferroelectric capacitor and structure applications thereof.Utilize method of the present invention and structure, can solve institute's high temperature oxygen of supervening diffusion in the ferroelectric capacitor manufacture process traditionally, and cause the problem of tungsten plug oxidation.Use method of the present invention and structure simultaneously and can not need use polysilicon plug to replace tungsten plug,, therefore can't influence the electrical performance of whole ferroelectric internal memory to reduce the oxidation possibility.Application of the present invention should be not limited only to the embodiment of the following stated.
Fig. 2 A to Fig. 2 E is the technology generalized section with conductor gap ferroelectric capacitor of the present invention.Please refer to Fig. 2 A, semiconductor substrate 100 at first is provided, for example is to have＜100〉structure P type silicon base.In substrate 100, finished the making of the semiconductor subassembly of part, on the active area of substrate 100, produce transistor, generally include grid 102, the grid oxic horizon 104 between grid 102 and substrate 100, and the source/drain regions 106 that is positioned at grid 102 both sides.On transistor, be coated with a layer insulating 110, such as being silicon dioxide, spin-on glasses (SOG), low dielectric (Low-k) material or its combination.In insulating barrier 110, have a contact hole connector 112 and be coupled to source/drain regions 106, contact hole connector 112 employed materials are tungsten such as being tungsten (W), compound crystal silicon (Poly-Si) or doping compound crystal silicon (Doped poly-Si) etc. with this most preferred embodiment.Its manufacture method generally is to utilize little shadow and etching technique, at first forming one deck patterning photoresist layer (not shown) on insulating barrier 110, serves as the cover curtain with this patterning photoresist layer then, etching isolation layer 110, in insulating barrier 110, to form contact window, remove the patterning photoresist layer afterwards.
In contact window, insert before the electric conducting material, be preferably elder generation and form one deck tungsten adhesion layer 108 at the bottom and the sidewall of contact window, its material is such as being titanium (Ti), titanium nitride (TiN) etc., its manufacture method generally is to utilize the mode of sputter to form the conformal tungsten adhesion layer 108 of one deck on the surface of insulating barrier 110, so can promote the follow-up adhesive force that forms tungsten plug in contact window.Then in contact window, insert electric conducting material and form contact hole connector 112,, be to use tungsten to be used as this electric conducting material according to this most preferred embodiment.
Then please refer to Fig. 2 B, on tungsten adhesion layer 108 and tungsten plug 112, deposit one deck conductor layer 114 and one deck diffusion retaining layer 116 in regular turn, according to this most preferred embodiment, the material of conductor layer 114 is titanium nitride (TiN).The material of diffusion retaining layer 116 is silicon nitride (Si
3N
4).Wherein this conductor layer 114 mainly is in final finishing in the structure, and the usefulness of ferroelectric capacitor lower floor pole plate and tungsten plug 112 electric connections is provided.And the main purpose of diffusion retaining layer 116 is the barrier layers as high temperature oxygen, that is when carrying out high-temperature technology, is used for protecting tungsten plug 112, prevent that high temperature oxygen from diffusing into and with the tungsten plug reaction, form one deck tungsten oxide layer.Conductor layer 114 its manufacture methods generally are to utilize the mode of sputter to form in above-mentioned, and the silicon nitride layer of diffusion retaining layer 116 can use traditional chemical vapour deposition (CVD) (chemical vapor deposition; CVD) mode, for example electricity slurry enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) etc., formed.
Still consult Fig. 2 B, on diffusion retaining layer 116, form bottom electrode 118.Then form one deck ferroelectric material layer 120 on bottom electrode 118, the ferroelectric material of ferroelectric material layer 120 for having perovskite (perovskite) structure is such as being lead zirconium titanate (Pb/Zr/TiO
3, PZT), barium strontium (BST) or strontium bismuth tantalate (SBT) etc.The method that forms ferroelectric material layer 120 is such as being chemical vapour deposition technique (CVD) or organic chemical vapor deposition method (MOCVD) etc.In this technical process; in order to allow ferroelectric material layer 120 that a well-crystallized degree is arranged; typical temperature is all greater than 500 ℃; usually can supervene the high temperature oxygen diffusion, and cause the problem of tungsten plug 112 surface oxidations, but because in structure of the present invention; on conductor layer 114, can form one deck diffusion retaining layer 116 in addition; be used for protecting tungsten plug 112, prevent that high temperature oxygen from diffusing into and with tungsten plug 112 reactions, form one deck tungsten oxide layer.
See also Fig. 2 C figure definition bottom electrode 118, be coated with a photoresist layer (not demonstrating among the figure) on ferroelectric material layer 120, follow this photoresist layer of patterning, make it have required bottom electrode 118 patterns, serve as the cover curtain with this patterning photoresist layer then, the part ferroelectric material layer 120 of etch exposed, bottom electrode 118 and diffusion retaining layer 116.The last definition of again the photoresist layer removal being finished bottom electrode 118.
See also Fig. 2 D, then deposit one deck conductor layer from the teeth outwards comprehensively, be used for making conductor gap 122, its conductor material can be polysilicon, tungsten silicide or tungsten etc., according to most preferred embodiment of the present invention, be to adopt tungsten to be used as this conductor material, its manufacture method generally is to utilize the mode of chemical vapour deposition technique (CVD) to form.Then utilize dry ecthing method, to etching mode, carry out the gap etching with non-grade, simultaneously also can be in this step simultaneously with conductor layer 114 etching offs.According to most preferred embodiment of the present invention, the dry etching process that it makes conductor gap 122 and conductor layer 114 can use dry etching process, for example reactive ion etching (reactive ion etch with anisotropic; RIE) etc.Conductor gap 122 figures after its etching is finished are shown in Fig. 2 D, wherein, bottom electrode 118 couples with conductor gap 122, and electrically connects with transistorized source/drain regions 106 by conductor layer 114 and contact hole tungsten plug 112, by the electrical operation of transistor controls electric capacity.According to method of the present invention, its lower electrode plate 118 is to electrically connect by this conductor gap 122 and transistorized source/drain regions 106, therefore structure of the present invention has autoregistration (Self-Align) advantage, that is lower electrode plate 118 of the present invention must not be positioned at contact hole tungsten plug 112 directly over, even it is offset a segment distance, because of it is to do electric connection by conductor layer 114,, promptly can not influence its electrical performance as long as this conductor layer 114 can couple with contact hole tungsten plug 112.On the other hand, tool one deck diffusion retaining layer 116 on conductor layer 114, can prevent that high temperature oxygen from diffusing into and with tungsten plug 112 reactions, form one deck tungsten oxide layer.
See also Fig. 2 E, after having formed conductor gap 122, comprehensive deposition one dielectric layer 124 on the surface is used for isolating the top electrode and the conductor gap 122 of follow-up made.Dielectric layer 12 can be silicon nitride layer or silicon oxide layer in above-mentioned, uses traditional chemical vapour deposition (CVD) (chemical vapor deposition; CVD) mode, for example electricity slurry enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) etc. are formed.Be connected to and form one deck patterning photoresist layer (not shown) on the dielectric layer 124, have in this patterning photoresist layer and form the required pattern of opening 128, serve as the cover curtain then with this patterning photoresist layer, the part dielectric layer 124 of etch exposed, ferroelectric material layer 120 under exposing forms opening 128.At last, form top electrode 126 in the surface of dielectric layer 124, with upper electrode plate as the internal memory capacitor.This conductive layer 126 can adopt the material of the polysilicon of doping, also can replace with metal level or metal silicide layer.
Consult Fig. 2 F, be another kind of structural representation of the present invention, this structure is with the different of above-mentioned described structure maximum, when carrying out ferroelectric material layer 120, when bottom electrode 118 and diffusion keep off the etching of layer 116, carry out the etching of conductor layer 114 simultaneously, that is in this structure, conductor clearance layer 122 is not to be built on the conductor layer 114, and it is to be built on the tungsten adhesion layer 108.But,, therefore still can do electric connection by conductor layer 114 and contact plunger 112 because conductor gap 122 still contacts with conductor layer 114 tools according to this structure.
Therefore, in sum, clearly, conductor of the present invention gap 122 structures can have a lot of distortion, that is to say, conductor clearance layer 122 is not must be built on the conductor layer 114, as long as this conductor clearance layer 122 can be done electric connection with conductor layer 114.Therefore, if carry out ferroelectric material layer 120, during the etching of bottom electrode 118 and diffusion retaining layer 116, carry out conductor layer 114 simultaneously, stick layer 108 etching with tungsten, allow conductor clearance layer 122 directly be built on the surface at the semiconductor-based end 100, still can not influence electrical performance of the present invention.
In sum, the present invention has plurality of advantages compared to prior art.Ferroelectric capacitor structure at first provided by the present invention can solve in the manufacturing process, because of high temperature oxygen spreads, and causes the problem of tungsten plug oxidation.And the present invention on the other hand special conductor gap 122 structures that have, can make the present invention have the autoregistration effect, that is do electric connection by conductor layer 114, as long as this conductor layer 114 can couple with contact hole tungsten plug 112, promptly can not influence its electrical performance.
Structure of the present invention also can be applicable in another kind of the application, and in the middle of a kind of resistive internal memory, it is to use a kind of chalcogenide to be used as memory material, utilize different phase change, this kind material resistance value size has very big difference, remembers different data, and its structure please refer to Fig. 3.Chalcogenide 130 is positioned over 126 of conductor gap 122 and conductive layers, and dielectric layer 124 is also used spaced conductors gap 122 and conductive layer 126, utilizes the different resistance values that homophase did not present of chalcogenide 130 to come memory document.
Understand as the person skilled in the art, the above only is preferred embodiment of the present invention, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the following claim.
Claims (23)
1. manufacture method with the ferroelectric capacitor in gap is characterized in that comprising:
The semiconductor substrate is provided;
On the semiconductor-based end, form first conductor layer;
On first conductor layer, form a diffusion retaining layer;
On diffusion retaining layer, form second conductor layer;
On second conductor layer, form a ferroelectric material layer;
On ferroelectric material layer, form a patterning photoresist layer, to expose ferroelectric capacitor bottom electrode size;
With the patterning photoresist layer is cover curtain etching diffusion retaining layer, ferroelectric material layer and second conductor layer;
Remove the patterning photoresist layer;
Finish formation one the 3rd conductive layer at the etched semiconductor-based end at this;
The 3rd conductor layer is carried out the dry ecthing of anisotropic, with the upper surface that exposes ferroelectric material layer and form a gap;
On gap, ferroelectric material layer and semiconductor-based basal surface, form an insulating barrier gap, and have an opening that only exposes the ferroelectric material layer upper surface in this insulating barrier; And
On opening and insulating barrier, form the 4th conductor layer, with top electrode as ferroelectric capacitor.
2. the method for claim 1 is characterized in that: the method that forms opening comprises:
Form a patterning photoresist layer on insulating barrier, this patterning photoresist layer has the pattern of opening;
With the patterning photoresist layer is the cover curtain, and etching isolation layer is to form opening; And
Remove the patterning photoresist layer.
3. the method for claim 1, it is characterized in that: the size of opening only can expose the upper surface of ferroelectric material layer.
4. the method for claim 1, it is characterized in that: ferroelectric material comprises lead zirconium titanate (PZT).
5. the method for claim 1 is characterized in that: have a transistor at semiconductor-based the end, and connect this transistorized contact hole connector.
6. method as claimed in claim 5 is characterized in that: the contact hole plug material comprises tungsten.
7. the method for claim 1, it is characterized in that: first conductive comprises titanium nitride.
8. the method for claim 1 is characterized in that: spread the retaining layer material and comprise silicon nitride.
9. the method for claim 1, it is characterized in that: the 3rd conductive comprises tungsten.
10. ferroelectric capacitor with gap, framework is characterized in that in the semiconductor substrate: have a transistor in this semiconductor-based end, and the contact hole connector that connects this transistor source or drain electrode, this structure comprises:
One island structure is formed at at semiconductor-based the end, and wherein this island structure comprises:
First conductor layer is positioned at at semiconductor-based the end, and is connected with the contact hole connector;
One diffusion retaining layer is positioned on first conductor layer;
Second conductor layer is positioned on the diffusion retaining layer, as the bottom electrode of ferroelectric capacitor; And
One ferroelectric material layer is positioned on second conductor layer;
One conductor gap is formed at the side of island structure;
One insulating barrier is positioned on conductor gap, ferroelectric material layer and the semiconductor-based basal surface, and has the opening that only exposes the ferroelectric material layer upper surface in this insulating barrier; And
One the 3rd conductor layer is formed on opening and the insulating barrier, with the top electrode as ferroelectric capacitor.
11. electric capacity as claimed in claim 10 is characterized in that: the size of opening only can expose the upper surface of ferroelectric material layer.
12. electric capacity as claimed in claim 10 is characterized in that: ferroelectric material comprises lead zirconium titanate (PZT).
13. electric capacity as claimed in claim 10 is characterized in that: the contact hole plug material comprises tungsten.
14. electric capacity as claimed in claim 10 is characterized in that: first conductive comprises titanium nitride.
15. electric capacity as claimed in claim 10 is characterized in that: diffusion retaining layer material comprises silicon nitride.
16. electric capacity as claimed in claim 10 is characterized in that: conductor clearance layer material comprises tungsten.
17. the transistor internal memory with gap, framework is characterized in that in the semiconductor substrate: have a transistor in this semiconductor-based end, and the contact hole connector that connects this transistor source or drain electrode, this structure comprises:
One island structure is formed at at semiconductor-based the end, and wherein this island structure comprises:
First conductor layer is positioned at at semiconductor-based the end, and is connected with the contact hole connector;
One diffusion retaining layer is positioned on first conductor layer; And
One internal memory material layer is positioned on the diffusion retaining layer;
One conductor gap is formed at the side of island structure;
One insulating barrier is positioned on conductor gap, internal memory material layer and the semiconductor-based basal surface, and has the opening that only exposes internal memory material layer upper surface in this insulating barrier; And
One second conductor layer is formed on opening and the insulating barrier.
18. internal memory as claimed in claim 17 is characterized in that: the size of opening only can expose the upper surface of internal memory material layer.
19. internal memory as claimed in claim 17 is characterized in that: the internal memory material comprises chalcogenide.
20. internal memory as claimed in claim 17 is characterized in that: the contact hole plug material comprises tungsten.
21. internal memory as claimed in claim 17 is characterized in that: first conductive comprises titanium nitride.
22. internal memory as claimed in claim 17 is characterized in that: diffusion retaining layer material comprises silicon nitride.
23. internal memory as claimed in claim 17 is characterized in that: conductor clearance layer material comprises tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02118154 CN1453844A (en) | 2002-04-23 | 2002-04-23 | Ferroelectric capacitor with gap |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02118154 CN1453844A (en) | 2002-04-23 | 2002-04-23 | Ferroelectric capacitor with gap |
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| Publication Number | Publication Date |
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| CN1453844A true CN1453844A (en) | 2003-11-05 |
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| CN 02118154 Pending CN1453844A (en) | 2002-04-23 | 2002-04-23 | Ferroelectric capacitor with gap |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378949C (en) * | 2004-04-06 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Stable metal structure with tungsten plug |
| CN101197256B (en) * | 2007-12-28 | 2012-06-06 | 上海集成电路研发中心有限公司 | Method for forming interlaminar capacitor |
-
2002
- 2002-04-23 CN CN 02118154 patent/CN1453844A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378949C (en) * | 2004-04-06 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Stable metal structure with tungsten plug |
| CN101197256B (en) * | 2007-12-28 | 2012-06-06 | 上海集成电路研发中心有限公司 | Method for forming interlaminar capacitor |
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