CN1441579A - TCAM high-speed search method and system supporting multiple nexthop - Google Patents
TCAM high-speed search method and system supporting multiple nexthop Download PDFInfo
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Abstract
Supporting multiple nexthops TCAM high speed find method and its system characterizes in storing the multiple nexthops in the route list in the way of block based on the index method in TCAM and finding the image list composed of addrsses and ports quickly to set up a first and second steps nexthop index list refer to the law of its number lower than 4 and 8 as the top limit.
Description
Technical field
Support TCAM high-speed searching method and the system thereof of many nexthop to belong to high speed IP address search field, the Internet.
Background technology
Router is the visual plant in the Internet network, and it is responsible for routing forwarding is carried out in grouping in the network.When transmitting grouping, router need carry out route querying based on the purpose IP address of each packet header in routing table, finds correct next of grouping to jump out mouth.Because router all carries out the route querying operation for each grouping, the performance of route querying directly affects the router overall performance.The nineties, IETF proposes CIDR (Classless Inter-Domain Routing CIDR) address structure in order to solve problems such as address waste and routing table increase in size be too fast.CIDR allows the network address prefix of random length to exist, and the route querying process becomes the longest matched and searched process, and this has increased the complexity of route querying greatly.Internet of future generation adopts the IPv6 technology, and address size expands to 128 from 32, and the routing table scale further increases, and the route querying difficulty also further improves.At present, in order to satisfy the demand of the network bandwidth, router has to adopt the interface of two-forty.The interface of OC48 (2.5Gbps) and OC192 speed such as (10Gbps) is applied in router.Under OC192 speed, router need be transmitted 3,000 ten thousand groupings each second, and need carry out 3,000 ten thousand times route querying each second.Route querying technology at a high speed becomes the key of high-performance router design.
In recent years, the researcher has proposed many mechanism and algorithm solution high speed route lookup problem.These algorithm great majority are based on traditional memory devices such as DRAM, SRAM.For example: Degermark proposes a kind ofly to search algorithm fast based on what compression was transmitted.For a big routing table with 40,000 list items, algorithm can be compressed into transmitting of 150K-160Kbytes size to it.Because transmitting after the compression is very little, it can be stored with memory device at a high speed.If realize this algorithm with hardware, carrying out the required minimum internal storage access number of times of a route querying is 2, and the maximum memory access times are 9.Gupta proposes a 24-8 multiple-limb Tries tree route querying algorithm based on big DRAM storage.When carrying out a route querying, algorithm at most only needs twice access memory.The required DRAM memory space of algorithm is about 33MBytes.Can be reduced to 9MBytes to algorithm to the demand of internal memory by increasing middle table, but the maximum memory access times that algorithm is searched once will reach 3.This class generally can obtain higher speed of route lookup based on the algorithm of searching of DRAM, SRAM, but has poor performance at aspects such as memory space, renewal speed and autgmentabilities.
TCAM (Ternary Content Addressable Memory Ternary Content Addressable Memory) technology is a kind of hardware searching technology that occurs in recent years, and it can realize route querying at a high speed.The TCAM chip internal uses concurrent technique, can obtain the complexity of searching of O (1).Obtainable in the market TCAM chip seek rate is the fastest to reach 100M time/second.TCAM has good performance equally aspect memory space and the autgmentability.The TCAM chip internal adopts tristate logic, can reach the storage complexity of O (1) for route prefix.The TCAM technology also has favorable expansibility for IPv6, by the memory of configuring chip inside, can realize IPv6 route querying at a high speed.As seen, compare with other route querying technology, the TCAM technology has apparent in view advantage aspect speed of route lookup, memory space and the autgmentability.But the shortcoming of TCAM technology also is that significantly mainly there are following three shortcomings in it: 1, cost height.The TCAM chip is than the SRAM of same memory space, and DRAM is expensive a lot.2, power consumption is big.The TCAM chip internal adopts concurrent technique to carry out the comparison of keyword, and inner power consumption is very big.3, routing update complexity.When realizing that with the TCAM technology longest-prefix is searched, route prefix needs to sort in a certain order in the TCAM chip, and this makes routing update operate relative complex.Inefficient routing update meeting influences the route querying performance of TCAM greatly.Means such as three shortcomings of TCAM technology can be compressed by route, effective routing update are resolved to a certain extent.As a whole, though the TCAM technology exists shortcoming, it is still a kind of reasonable Route Lookup Scheme.
Routing table is a data cell important in the router, and it is the foundation that route querying is transmitted.We examine or check routing table actual among the Internet, find to have a considerable amount of route table items in the routing table, they have a plurality of nexthops (next jumping), as seen the existence of many nexthops route is the key character of routing table, but this feature all is not mentioned in introducing nearly all article of route querying algorithm and scheme and considers.The existence of many nexthops route has increased the complexity of Route Lookup Scheme design.Also do not have the researcher to propose one at present and both satisfied the high-speed searching requirement, support the Route Lookup Scheme of many nexthops again.
Summary of the invention
The object of the present invention is to provide a kind of TCAM high-speed searching method and system thereof that supports many nexthop.
The lookup method that the present invention proposes is characterised in that, it is that a kind of indexed mode that adopts is stored with the form of piece (Block) the composition of a plurality of next jumping (Nexthop) in the route list item, again the method that Nexthop mapping table index carries out high-speed searching is formed in next hop address, port and next jumping accordingly simultaneously, it at next of almost used route table items jump number all be lower than 4 these rules simultaneously with the number of next jumping be 8 as the upper limit, next jumps concordance list to have set up one, two two-stages; It is to realize on the basis of the memory of the ternary content addressable with high speed route lookup performance (TCAM), contains successively with following step:
(1) initialization:
In TCAM, press unit k storage route prefix information;
In SRAM1, corresponding one by one mutually with the memory cell k of TCAM, next jumps index information by following three class data structure storage one-levels, forms the one-level concordance list;
The a class: totally 16, the 1st is 0, and expression has only next jumping; All the other 15 is the mapping table index of this next jumping;
The b class: totally 16, the 1st is 1, represents that next jumping number is greater than 1; The 2nd～3 is piece number (Block number), and there are 2,3 or 4 next jumpings in the route table items in the expression piece; Next jumps the piece bias internal (Block offset) of concordance list the 4th～16 bit representation secondary; Next jumps block number in concordance list to represent secondary with BN, and BN=0,1,2 is representing in the corresponding piece successively 2,3 or 4 next jumpings respectively;
The c class: totally 16, the 1st is 1, represents that next jumping is more than one; The 2nd～3 bit representation piece BN=3, meaning is the same; Next jumping figure (Nexthop number) in this piece of the 4th～6 bit representation numbers 3, its value is between 2～8; The 7th～16 bit representation piece bias internal, meaning is the same, represents with BO;
The index of next jumping mapping table of storage in SRAM2, next jumps concordance list to form secondary; This concordance list is divided into 4, and first three piece is stored next respectively and jumped the mapping table index that number is 2,3 or 4 route table items, the 4th storage next to jump number be the mapping table index of the route table items between 2～8; Wherein, the mapping table index of a plurality of next jumping of route table items storage continuously in the secondary index table;
Store forwarding information in SRAM3, content is the IP address of next jumping and outbound port number, forms next and jumps mapping table, and setting next degree of depth of jumping mapping table is 256;
At the scene in the programmable gate array (FPGA) store secondary next jump 4 pieces in concordance list the base address (BA, baseaddress), i.e. the first address of first next jumping in each piece;
(2) source address of input grouping and the destination address of grouping;
(3) according to purpose IP address search TCAM chip, obtain longest matching prefix place unit k;
(4) the unit k of next jumping concordance list of visit one-level;
(5) the 1st of judging unit k the:
If the 1st is 0, then from unit k, obtain next and jump the mapping table index, jump to step (9);
If the 1st be 1, execution in step (6) then;
(6) BN, BO among the one-level concordance list unit k and NN are sent to FPGA storage and control circuit;
(7) FPGA calculates the secondary that will visit according to BN, BO and NN next jumps the cell position of concordance list, and it contains following step successively:
7.1, obtain the base address BA of relevant block by BN;
7.2 judge the value of BN:
If BN＜3, then obtain corresponding N N, i.e. BN=0,1,2 corresponding NN=2 respectively, 3,4;
If BN=3 then obtains NN in the c class data structure from next jumping concordance list of one-level, i.e. next jumping figure order;
7.3 next jumping mapping table index according to following policy selection forwarding:
7.3.1 the index (index) of next jumping that obtains selecting according to following formula:
(destination address of the source address+grouping of grouping)/NN;
7.3.2 by calculating the cell position that (BA+BO+index) obtains the secondary index table that will visit;
(8) according to FPGA result calculated visit secondary index table, obtain next and jump the mapping table index;
(9) jump the mapping table index according to next, the access map table obtains forwarding information.The system of searching that the present invention proposes is characterised in that it contains:
TCAM: be input as grouping purpose IP address;
SRAM1: the longest matching prefix place unit k that is input as TCAM output;
FPGA: storage and controller, next jumps BN, BO and the NN of concordance list SRAM1 output to be input as one-level;
SRAM2: be input as the cell position that to visit among the secondary index table SRAM2 of FPGA storage and controller output;
SRAM3: the mapping table of next jumping, input are next jumping mapping table index of SRAM1 output, or next jumping mapping table index of SRAM2 output.
Evidence: the present invention have support a plurality of next jump, seek rate can reach 100M time/second, less memory space, route querying has the advantage of favorable expansibility to IPv6.
Description of drawings
Fig. 1. the schematic diagram of the high-speed searching method that the present invention proposes.
Fig. 2. next jumps the data structure diagram of indexing units one-level:
A: the 1st is 0 o'clock;
B: the 1st is 1, and 2～3 less than 3 o'clock;
C: the 1st is 1, and 2～3 equal at 3 o'clock;
Fig. 3. the program flow diagram of lookup method
Fig. 4. two example schematic of searching
Fig. 5. search the circuit theory diagrams of system.
Embodiment
Fig. 1 is the master-plan of scheme.Fig. 1 comprises five parts: TCAM chip, one-level nexthop concordance list, secondary nexthop concordance list, nexthop mapping table and FPGA storage and controller.Successively various piece is described below:
TCAM chip-stored route prefix information, i.e. (prefix IP, prefix mask).TCAM finishes the longest matched and searched of route prefix.
One-level nexthop index table stores unit is corresponding one by one with the memory cell of TCAM chip.Such as: k the unit of the route prefix information stores of certain bar route table items in the TCAM chip, then corresponding one-level index information is stored in k unit of one-level concordance list.The memory cell width of one-level concordance list is 16bits (this width can be adjusted according to the size of secondary index table), and it has three class formations as shown in Figure 2.Unit shown in Fig. 2 (a) represents that only there is a nexthop in this route table items, and 15bits stores the index of nexthop mapping table behind the unit, can obtain the forwarding information of (next-hop IP, outbound port) in the nexthop mapping table according to this index.Unit shown in Fig. 2 (b) represents that there are 2,3 or 4 nexthops in this route table items.The value of BN is respectively 0,1, and 2.BN is the block number of secondary nexthop concordance list.BO is the piece bias internal of secondary index table.Unit shown in Fig. 3 (b) represents that there is the nexthops more than 2 or 2 in this route table items.The value of BN is 3, and NN indicates the number of route table items nexthop, and its value can be 2 to 8, and BO is the piece bias internal of secondary index table.
The index of secondary nexthop index table stores nexthop mapping table, cell data width are 8bits (what back can be interpreted as and select 8bits).The secondary index table is divided into 4 pieces.First three piece is stored the mapping table index that the nexthop number is 2,3,4 route table items respectively.Can store the mapping table index that the nexthop number is the route table items between 2 to 8 for the 4th.It is 2,3,4 route table items that piece 4 is not generally stored the nexthop number.When having only the no clearance spaces of piece 1, piece 2 and piece 3, just can store corresponding route table items.The mapping table index of a plurality of nexthop of route table items is storage continuously in the secondary index table.Such as: certain route table items has k nexthops, the mapping table index stores of first nexthop the secondary index table n unit, then all the other k-1 mapping table index are stored in n+1 successively, n+2 ..., in the k-1 of the n+k-1 sequential cells.
Secondary nexthop concordance list is the key component that realizes that many nexthops support.The secondary index table is divided into 4 pieces, and this mainly is because by the actual routing table of examination, and we find that next jumping number of nearly all route table items all is no more than 4.Piece 1, piece 2 and piece 3 just can meet the demands in the reality, and reserved block 4 mainly is in order to satisfy special requirement in the design.The big I of piece 1, piece 2, piece 3 is determined according to the statistical law of many nexthops route table items in the actual routing table in the secondary index table, is that 2,3,4 the shared percentage of route table items is r such as: nexthop number
2%, r
3%, r
4%, the degree of depth of one-level nexthop concordance list is N, and then piece 1, and the size of piece 2 and piece 3 is respectively N*2*r
2%, N*3*r
3%, N*4*r
4%.Big I for piece 4 decides according to actual needs.
The forwarding information of nexthop mapping table unit storage (next-hop IP, outbound port).The degree of depth of nexthop mapping table is 256.The degree of depth is 256 mainly to be because the number of ports of real router all is fewer, and different (next-hop IP, outbound port) right number is also just less.We go up real routing table to Internet and examine or check, and find that different (next-hop IP, outbound port) right numbers are far smaller than 256, and the while degree of depth is elected 256 as and also can be reduced memory space.Because the degree of depth of mapping table is 256, secondary nexthop index table stores the index of mapping table, so the designing requirement that the data width of 8bits just can the meeting tier 2 concordance list.
FPGA storage and controller are finished logical calculated all in the route querying process, are also storing the base address (BA, base address) of 4 pieces of secondary nexthop concordance list simultaneously.The FPGA storage is to calculate the secondary nexthop concordance list cell position that will visit by BN, BO in the one-level nexthop concordance list unit and NN territory with a critical function of controller, and the concrete computational process of FPGA control module is as follows:
1. by BN, obtain the base address BA of relevant block;
2., then obtain corresponding NN by BN if BN is less than 3; Specifically, BN=0, the corresponding NN=2 of 1,2 difference, 3,4; If BN=3, NN can obtain from one-level nexthop concordance list unit;
3. according to forwarding strategy, from a plurality of nexthops, select one as next jumping of transmitting; Simple strategy can be according to the index (index) of (destination address of the source address+grouping of grouping)/nexthop that NN obtains selecting;
4. the cell position (BA+BO+index) of the secondary index table that last calculating acquisition will be visited;
This programme search procedure can be divided into 4 stages: the TCAM chip is searched, one-level nexthop concordance list is visited, secondary nexthop concordance list is visited, the visit of nexthop mapping table.4 stages are independent mutually, do not have the shared resource conflict, can use pipelining further to improve seek rate.Such as: the TCAM chip adopts 100M time/second the storage of searching chip, other parts all to adopt the SRAM of 10ns, uses pipelining so, can obtain 100M time/second seek rate.
Scheme has favorable expansibility to IPv6.Because one-level concordance list and secondary index table all adopt indexed mode that route is stored, index and agreement have nothing to do, so scheme is upgraded to IPv6 from IPv4, only needs to expand nexthop mapping table cell data width and just can require.
Nexthop storage area requisite space is smaller in the scheme.We mainly are the forms that adopts index to the storage of many nexthops, and this has reduced the demand to memory space greatly.
Whole search procedure can be with flowcharting shown in Figure 3.
Fig. 4 is the example of two concrete route queryings.Example one is searching destination address 1.1.1.2.At first in the TCAM chip according to longest match principle, find the prefix 1.0.0.0/8 that matches.According to the position of unit, prefix 1.0.0.0/8 place, the one-level nexthop concordance list unit that visit is corresponding.The content of one-level concordance list unit is (0,14), and first bit position, unit is 0, so the content of 15 bits is the index (14) of nexthop mapping table behind the unit.The 14th unit of access index table obtains the forwarding information (1.1.1.2,2) of (next-hop IP, outbound port).Example two is searching destination address 10.9.1.2.At first in the TCAM chip, find with it the prefix 10.9.1.0/24 of long coupling.According to the position of unit, prefix 10.9.1.0/24 place, the one-level nexthop concordance list unit that visit is corresponding.One-level concordance list location contents is (1,0,50), and first bit of unit is 1, so latter two territory, unit is respectively BN (0), and BO (50).Give FPGA module BN and BO.The FPGA module is by source address, destination address and the BN of grouping, the nexthop index index (1) that obtains selecting, and finally calculate and will visit secondary index table unit position (BA+BO+1), visit secondary index table corresponding unit obtains the index (26) of nexthop mapping table.The 26th unit of access map table obtains the forwarding information of (3.1.1.1,4).
The present invention has following several characteristic: 1, support many nexthops; 2, support route querying at a high speed (can reach 100M time/second seek rate at present); 3, less memory space; 4, the IPv6 route had favorable expansibility.
Claims (2)
1. support the TCAM high-speed searching method of many nexthop, it is characterized in that it is that a kind of indexed mode that adopts is stored with the form of piece (Block) the composition of a plurality of next jumping (Nexthop) in the route list item, again the method that Nexthop mapping table index carries out high-speed searching is formed in next hop address, port and next jumping accordingly simultaneously, it at next of almost used route table items jump number all be lower than 4 these rules simultaneously with the number of next jumping be 8 as the upper limit, next jumps concordance list to have set up one, two two-stages; It is to realize on the basis of the memory of the ternary content addressable with high speed route lookup performance (TCAM), contains successively with following step:
(1) initialization:
In TCAM unit k storage route prefix information;
In SRAM1, corresponding one by one with the memory cell k of TCAM, next jumps index information by following three class data structure storage one-levels, forms the one-level concordance list;
The a class: totally 16, the 1st is 0, and expression has only next jumping; All the other 15 is the mapping table index of this next jumping;
The b class: totally 16, the 1st is 1, represents that next jumping number is greater than 1; The 2nd～3 is piece number (Block number), and there are 2,3 or 4 next jumpings in the route table items in the expression piece; Next jumps the piece bias internal (Block offset) of concordance list the 4th～16 bit representation secondary; Next jumps block number in concordance list to represent secondary with BN, and BN=0,1,2 represents to exist successively in the corresponding piece 2,3 or 4 next jumpings respectively;
The c class: totally 16, the 1st is 1, represents that next jumping is more than one; The 2nd～3 bit representation piece BN=3, meaning is the same; Next jumping figure (Nexthop number) in this piece of the 4th～6 bit representation numbers 3, its value is between 2～8; The 7th～16 bit representation piece bias internal, meaning is the same, represents with BO;
The index of next jumping mapping table of storage in SRAM2, next jumps concordance list to form secondary; This concordance list is divided into 4, and first three piece is stored next respectively and jumped the mapping table index that number is 2,3 or 4 route table items, the 4th storage next to jump number be the mapping table index of the route table items between 2～8; Wherein, the mapping table index of a plurality of next jumping of route table items storage continuously in the secondary index table;
Store forwarding information in SRAM3, content is the IP address of next jumping and outbound port number, forms next and jumps mapping table, and setting next degree of depth of jumping mapping table is 256;
At the scene in the programmable gate array (FPGA) store secondary next jump 4 pieces in concordance list the base address (BA, baseaddress), i.e. the first address of first next jumping in each piece;
(2) source address of input grouping and the destination address of grouping;
(3) according to purpose IP address search TCAM chip, obtain longest matching prefix place unit k;
(4) the unit k of next jumping concordance list of visit one-level;
(5) the 1st of judging unit k the:
If the 1st is 0, then from unit k, obtain next and jump the mapping table index, jump to step (9);
If the 1st be 1, execution in step (6) then;
(6) BN, BO among the one-level concordance list unit k and NN are sent to FPGA storage and control circuit;
(7) FPGA calculates the secondary that will visit according to BN, BO and NN next jumps the cell position of concordance list, and it contains successively
Following step is arranged:
7.1, obtain the base address BA of relevant block by BN;
7.2 judge the value of BN:
If BN＜3, then obtain corresponding N N, i.e. BN=0,1,2 corresponding NN=2 respectively, 3,4;
If BN=3 then obtains NN in the c class data structure from next jumping concordance list of one-level, i.e. next jumping figure order;
7.3 next jumping mapping table index according to following policy selection forwarding:
7.3.1 the index (index) of next jumping that obtains selecting according to following formula:
(destination address of the source address+grouping of grouping)/NN;
7.3.2 by calculating the cell position that (BA+BO+index) obtains the secondary index table that will visit;
(8) according to FPGA result calculated visit secondary index table, obtain next and jump the mapping table index;
(9) jump the mapping table index according to next, the access map table obtains forwarding information.
2. the TCAM high-speed searching method of the many nexthop of support according to claim 1 and the system of proposition is characterized in that it contains:
TCAM: be input as grouping purpose IP address;
SRAM1: the longest matching prefix place unit k that is input as TCAM output;
FPGA: storage and controller, next jumps BN, BO and the NN of concordance list SRAM1 output to be input as one-level;
SRAM2: be input as the cell position that to visit among the secondary index table SRAM2 of FPGA storage and controller output;
SRAM3: the mapping table of next jumping, input are next jumping mapping table index of SRAM1 output, or next jumping mapping table index of SRAM2 output.
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