CN1440217A - FPGA 5.1 channel virtual speech reproducing method and device - Google Patents
FPGA 5.1 channel virtual speech reproducing method and device Download PDFInfo
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Abstract
This invention discloses a method for replaying virtual sound of the 5.1 sound channel based on the FPGA (Field Programmable Gate Array) and the apparatus thereof. This method and apparatus can perform the de-correlation of the surround sound using the ways of the amplitude random and delay random, use the FPGA Field Programmable Gate Array) as the platform for implementing the algorithm of the virtual surround sound and realize it in a single chip FPGA. In order to add the reverberation into the surround sound channel using the way of delay, this method adopts the discrete random delay and amplitude random to decrease the correlation between the prior surround sound channel and the newly composed one so as to obtain better effect of the reverberation.
Description
Technical field
The present invention relates to implementation and device that a kind of sound field acoustic image is handled, be a kind of 5.1 channel virtualized low voice speaking method and devices put based on FPGA (gate array can be edited in the scene), this method and device can adopt amplitude to carry out the surround sound decorrelation with the method for delay random at random and handle, and adopt FPGA (Field Programmable Gate Array), and on monolithic FPGA, realize as the platform of realizing the virtual surround sound algorithm.
Technical background
At present, the mode of realization virtual surround sound has a variety of, but the method for general real-time implementation all is to adopt the DSP treatment system, or the dedicated IC chip that designs.(comprise the Dolby Headphone system) in these implementations, major part all is to adopt the method for number of people transfer function to realize, but effect has nothing in common with each other.
Wherein, for eliminating orientation effect in the head, the Dolby Headphone system proposes: simulate left and right loud speaker, central loudspeakers and the left and right surround sound loud speaker time-domain pulse response to ears, to use earphone repeat after the above-mentioned signal processing again, just can be simultaneously five loudspeaker virtuals of 5.1 transit systems be come out.But above processing mode has only been considered the direct sound wave of loud speaker to ears, does not consider the reflected sound of listening room, has therefore caused: when actual surround sound was retransmitted, the reflected sound of listening room can destroy the acoustic space information of the original sound field of surround sound signal; If simulate the reflected sound of listening room fully, then need a large amount of signal frequency collection points, this is difficult to realize in existing signal processing, all simulates the former secondary reflection sound of listening room in the reality, this simulation also can influence the effect of repeating transmission.
Therefore, someone has proposed new processing mode, requirement at the 5.1 path surround sound signals processing that will reach, situation in conjunction with practical application, handling a left side, right path signal, in the time of the center channel signal, emphasis is handled a left side well, right surround sound signal (this signal generally includes the reflected sound information of original sound field), with a left side, after right surround sound carries out the decorrelation processing, retransmit with a series of virtual speaker again, and (number of patent application is 02134416.7, and denomination of invention is a kind of signal processing method of earphone repeat of 5.1 path surround sounds to have proposed patent application; Number of patent application is 02134415.9, and denomination of invention is the signal processing method of two-loudspeaker virtual 5.1 path surround sounds).
Problem is that above-mentioned mode is when directly adopting the method adding reverberation sound of time-delay handling left and right surround sound signal, the reverberation sound that obtains has pectination frequency response (when the odd-multiple of the half-wavelength of the frequency of delay time correspondence), can not reach treatment effect fully.
Summary of the invention
After the objective of the invention is to have carried out certain improvement and conversion on the basis of two applications in the above, employing be the time at random with the method for amplitude surround sound decorrelation at random, make that the reverberation sound correlation of virtual playback is very low, can not form acoustic image.
Another object of the present invention is to realize above-mentioned function by FPGA (Field Programmable GateArrays field programmable gate array), does not need external memorizer spare simultaneously, and external equipment is few.
The present invention is achieved in that
The method of delaying time for the employing of surround channel adds reverberation, it is characterized in that adopting discrete random delay and amplitude to reduce the relevant of original surround channel and the new surround channel that synthesizes at random, obtains better reverberation effect.
Time-delay at random, i.e. the module that the left and right sides surround sound of voice signal is postponed to handle, the voice signal of its input is the voice signal of 5.1 paths, time-delay is a benchmark with 5ms, randomized jitter, in the scope of ± 0.25ms according to even distribution change at random; Also can adopt 11ms is the time-delay of benchmark, randomized jitter, in ± 0.5ms scope according to even distribution change at random.
Amplitude at random, be above-mentioned module, when time-delay was benchmark with 5ms, amplitude weighting was a benchmark with 0.5, scope changes between 0.25-0.75, randomized jitter, in ± 0.25 scope according to similar Gaussian Profile change at random, owing to realize accurately relatively difficulty of Gaussian Profile, so adopt the distribution mode of similar Gaussian Profile, make that amplitude weighting is 0.5 probability maximum, depart from 0.5 more, then probability of occurrence is more little; When time-delay was benchmark with 11ms, amplitude weighting changed between 0-0.5, taked above-mentioned mode to make that amplitude weighting is is average equally distributed stochastic variable in the scope of 0-0.5 with 0.25 equally.
Reasonable mode is to adopt two above-mentioned modules simultaneously, realizes simultaneously with 5ms being the time-delay of benchmark and being the time-delay of benchmark with 11ms, and corresponding amplitude weighting.
In a word, for amplitude at random with time-delay the getting a little of benchmark at random, one or more point all is feasible, gets a little manyly more, effect is good more.
In order to represent the voice signal of 5.1 paths, represent L channel with L, R represents R channel, Ls represents left surround sound sound channel, Rs represents right surround sound sound channel, C is a center channel, and LFE is that the low-frequency effect sound channel (if the voice signal of input is a stereophony, then import by center channel and low-frequency effect sound channel no signal; Left and right surround sound sound channel is the left and right acoustic channels voice signal of input stereo audio respectively), concrete implementation is:
A is with the sampled value of the central corridor (C) of 5.1 path voice signals of same sampling instant and the sampled value addition of bass effect passage (LFE);
B is with above-mentioned additive value convolution or multiply each other, and makes it to enlarge 1.414 times, and then is input in the L channel;
The voice signal of C left and right sound channels is through the MS conversion;
The signal plus of left channel signals after the D conversion and B step input carries out the Sigma_1 convolution again;
Right-channel signals after the E conversion is through the Sigma_r convolution;
The left and right surround sound sound channel of F is provided with three modules that the left and right sides surround sound of voice signal is postponed to handle simultaneously, and respectively voice signal is carried out the MS conversion; Wherein two (corresponding left and right surround sound sound channel respectively) do not carry out any processing to the voice signal of 5.1 paths, when the voice signal of input is the stereophony voice signal, then postpones the processing of decorrelation; Two in addition (corresponding left and right surround sound sound channel respectively) postpones the decorrelation processing to the voice signal of 5.1 paths of input, and the delay reference time is 5ms; In addition two (corresponding left and right surround sound sound channels respectively) then postpone decorrelation to the voice signal of 5.1 paths of input and handle, and the delay reference time is 11ms;
The voice signal of 5.1 paths that the module that G postpones to handle through left and right sides surround sound does not postpone to handle, the signal of left surround sound sound channel carries out the Delta_11 convolution, and the signal of right surround sound sound channel carries out the Delta_r1 convolution;
The module that H postpones to handle through left and right sides surround sound is carried out the voice signal that be the delay processing of 5ms fiducial time, and the signal of left surround sound sound channel carries out the Delta_12 convolution, and the signal of right surround sound sound channel carries out the Delta_r2 convolution;
The module that I postpones to handle through left and right sides surround sound is carried out the voice signal that be the delay processing of 11ms fiducial time, and the signal of left surround sound sound channel carries out the Delta_13 convolution, and the signal of right surround sound sound channel carries out the Delta_r3 convolution;
Left and right surround sound sound channel signal addition respectively after the J convolution, and correspondence is input in the left and right sound channels;
The left surround sound sound channel signal of addition and the left channel signals addition after the convolution after the K convolution; Simultaneously, the right surround sound sound channel signal of addition and the right-channel signals addition after the convolution after the convolution;
The above-mentioned K step added signal of L is input to the output balance module through the MS conversion;
The M balance module carries out the tone color equilibrium treatment to the signal of input, and retransmits by left and right acoustic channels.
The MS conversion, promptly input signal is a two-way up and down, output signal also is a two-way up and down, wherein Shu Chu top one road signal be input two paths of signals and, the bottom one tunnel of output is the poor of the top one tunnel the imported bottom one tunnel that deducts input; The signal of input is the audio sample signal, and then the operation of top is carried out once each audio sample point.
The module that the above-mentioned voice signal left and right sides surround sound to 5.1 paths postpones to handle except that the voice signal to 5.1 paths postpones to handle, in other cases, does not have the voice signal input.
The module that the above-mentioned voice signal left and right sides surround sound to 5.1 paths postpones to handle, wherein the voice signal of 5.1 paths is not postponed the module handled, when input audio signal is the voice signal of 5.1 paths, this module is not carried out any processing, is equivalent to lead directly to; Only the stereophony voice signal to input carries out the delay decorrelation processing that the delay reference time is 5ms.
The coefficient of equalizing wave filter of equilibrium treatment is to handle in a manner mentioned above with white noise signal, and the signal that obtains does not carry out equilibrium treatment, but carries out that inverse filtering obtains.
Above-mentioned scheme can be with reference to shown in Figure 1.Among the figure:
(1) for addition, with the sampled value of the central corridor (C) of 5.1 path voice signal kinds of same sampling instant and the sampled value addition of bass effect passage (LFE).
(2) symbolic representation is multiplied each other or convolution, and the individual digit on next door is represented the multiplier of a multiplication, and the vector of convolution is carried out in the sign symbolic representation on symbol next door.1.414 expression is extended 1.414 times through the data of this symbol, Sigma_1, Sigma_r (annotating 1) are two convolution vectors, and expression is passed through the data of this symbol by Sigma_1, Sigma_r (annotating 1) convolution.
(3) expression is passed through the data of this convolution symbol by Delta_11, Delta_r1 (annotating 1) convolution.
(4) expression is passed through the data of this convolution symbol by Delta_12, Delta_r2 (annotating 1) convolution.
(5) expression is passed through the data of this convolution symbol by Delta_13, Delta_r3 (annotating 1) convolution.
(6) box indicating is carried out the MS conversion to the two paths of data of passing through, and input signal is a two-way up and down, output signal also be about two-way.Wherein Shu Chu top one road signal be input two paths of signals and, the bottom one tunnel of output is bottom one tunnel poor that the top one tunnel of input deducts input.The signal of input is the audio sample signal, and then the operation of top is carried out once each audio sample point.
(7) D11, D12 are the modules that the left and right sides surround sound to voice signal postpones to handle.If input audio signal is the voice signal of 5.1 paths, then this module is not carried out any processing, is equivalent to lead directly to.When the voice signal of input is the stereophony voice signal, then postpone the processing of decorrelation, the delay reference time is 5ms.
(8) D21, D22 are the modules that the left and right sides surround sound to voice signal postpones to handle.If the voice signal of input is the voice signal of 5.1 paths, then these two modules postpone the decorrelation processing, and the delay reference time is 5ms.Under other the situation, these two paths do not have the voice signal input.
(9) D31, D32 are the modules that the left and right sides surround sound to voice signal postpones to handle.If the voice signal of input is the voice signal of 5.1 paths, then these two modules postpone the decorrelation processing, and the delay reference time is 11ms.Under the situation of other input signal, this path voiceless sound signal input.
(10) be the balance module of output, the voice signal after virtual sound image is handled carries out the tone color equilibrium.The coefficient of equalization filter obtains with following mode, now input audio signal is replaced with white noise, and after handling by the structure (not comprising equilibrium) of Fig. 1, the signal that obtains carries out inverse filtering, obtains the parameter of equalization filter.
What (11) indicated is 5.1 path voice signals, and L is a L channel, and R is a R channel, and Ls is left surround sound sound channel, and Rs is right surround sound sound channel, and C is a center channel, and LFE is the low-frequency effect sound channel.If the voice signal of input is a stereophony, then center channel and low-frequency effect sound channel are imported no signal; Left and right surround sound sound channel is the left and right acoustic channels voice signal of input stereo audio respectively.
(12) L ' and R ' are the output result of system handles, if the algorithm of handling is an earphone virtual surround sound Processing Algorithm, then this signal after the earphone power amplifier amplifies directly by Headphone reproducing; If Processing Algorithm is the surround sound Processing Algorithm of two-loudspeaker virtual 5.1 paths, then this signal after power amplification by a pair of low-angle speaker playback.
Annotate 1:Sigma_1, Sigma_r, Delta_11, Delta_r1, Delta_12, Delta_r2, Delta_13 and Delta_r3 represent to represent the number of people transfer function of different angles directional information.About application point of view in number of people transfer function and the algorithm, prior art has had relevant argumentation, in two mentioned patent applications of the present invention description is arranged also, be not described at this.
For time-delay at random: the time-delay of D21, D22 is benchmark with 5ms, randomized jitter, in the scope of ± 0.25ms according to even distribution change at random.The time-delay of D31, D32 is benchmark with 11ms, randomized jitter, in the scope of ± 0.5ms according to even distribution change at random.
For amplitude at random: the amplitude weighting of D21, D22 (scope changes between 0.25～0.75) is a benchmark with 0.5, randomized jitter, in ± 0.25 scope according to similar Gaussian Profile change at random, owing to realize that Gaussian Profile is relatively more difficult accurately, so used the distribution mode of a similar Gaussian Profile here, make that amplitude weighting is 0.5 probability maximum, it is approximately little to depart from 0.5 probability of occurrence more.The amplitude weighting value of D31, D32 changes between 0～0.5, is with the 0.25 equally distributed stochastic variable that is average in [0,0.5] scope.
An object of the present invention is to have adopted EPGA (gate array can be edited in the scene), the FPGA device is mainly used in fields such as communication, image acquisition, automatic control, because the difference of industry and the restriction of other condition can't be applied in the processing procedure of voice signal always.
The inventive system comprises: control signal module, bit clock, left and right sides clock, data reception module, Ls, Rs inhibit signal memory module, decorrelation address generation module, FIR filter coefficient storage, processing module, adder, data outputting module, wherein:
The control signal module, comprise two parts: processing mode control section and processing Synchronization Control part, the control signal of the module samples outside of processing mode control section, they are stored in the control signal register, this module determines that according to the value decoding of control signal register sample rate, signal type, the processing mode handled are selected, suitable coefficient is also selected in system reset.Control signal is provided by the audio frequency Play System that system served, and this module is at external control signal buffer status of each LRCLK cyclic polling, and according to the resetting of the state decision systems of control signal, parameter loading, processing mode change etc.; Handle synchronization control module and be responsible for the system handles Synchronization Control, it comprises up counter, counting clock, the rising edge counting;
Left and right sides clock is called sampling clock again, and its frequency equals the sample frequency of voice signal;
Data reception module is with multichannel I
2The S signal by serial to parallel conversion, latch, after the MS conversion, send into processing module after adjusting form; Serial to parallel conversion is realized that by SI PO shift register CLK is as the shift clock of shift register, and rising edge triggers; Latch is realized by register; The MS conversion module is made up of position adder and position subtracter, if LRCLK is low, input data in three shift registers be L channel, a left side around with the voice signal of center channel, otherwise the input data in three shift registers be R channel, right around with the voice signal of bass effect passage;
Ls, Rs inhibit signal memory module by base address register (addr_base), are deposited the base address, this address correspondence be the sample value of a up-to-date left and right sides surround channel in the memory space; The address offset register, address in the register is the address of the corresponding time-delay surround sound of reverberation time-delay, each LRCLK cycle, this memory module is upgraded a sampling point, base address register adds 1 simultaneously, address institute how in the register of address has surpassed the memory space of memory module, register returns zero, the cheap register value in address that must make new advances according to the base address simultaneously (adds fixed value on the base address, if cross the border, value after calculating is crossed the border), sends the decorrelation address offset here from the decorrelation address generator in addition, obtain postponing the surround sound sample value with address offset and base address addition;
Decorrelation address generation module, the hardware that it comprises has, base address register, offset address register; Base address register points to the surround sound sampling point of latest update, be zero when base address register powers in system, after system starts working, each LRCLK cycle adds 1, when being added to inhibit signal length, make zero, the address offset amount that the offset address register is deposited, what reality was corresponding is different time of delay, this delay time is fixed, and is determined by the signals sampling frequency; The function of this module also is to generate an address offset, this is offset on the basis of the base address of Ls, Rs inhibit signal memory module and offset address and has added a random address, surround sound signal in these three addresses and the address pointed, the inhibit signal of LS, RS all leaves in Ls, the Rs inhibit signal memory module, passes through the reverberation sound signal of random delay exactly; The generation of random address adopts the M sequencer on 11 rank and one 7 the shift register that seals in and go out to realize; When adopting serial FIR filter to realize, the shift register of M sequencer and its back is clock with CLK; When the summation realization is multiplied each other in employing, adopting MCLK4 is that the M sequence produces clock and shift register shift clock, the rising edge of each clock with the worthwhile work of shift register have the symbol offset address to deliver to Ls, Rs inhibit signal memory module is asked the location;
The FIR filter coefficient storage, depositing many group FIR filter coefficients in this memory, each group all is with the fixed coefficient of number of people transfer function through equalization weights, corresponding different processing modes (earphone, loud speaker) and many groups filter coefficient of two kinds of different signal formats (5.1 sound channels and stereophony) and corresponding different sample frequencys, when system powered on, default loud speaker processing mode with 5.1 sound channels FIR coefficient accordingly was loaded in the FIR bank of filters;
Processing module, the mode that adopts serial FIR filter to realize.Each FIR filter is made up of the serial filter of a plurality of four taps, each four tap serial filter can be realized a sampling point processing (a sample value input, a sample value output) of FIR filter at maximum 24 CLK in the clock cycle, when powering in system, loads the coefficient of each FIR filter, the appearance of reset signal also can allow system's FIR coefficient of reloading, because in the filtering, filter will use these filter coefficients simultaneously, so these coefficients will be moved to the register of filter coefficient storage; The FIR filter of this part also can adopt the mode of phase multiply accumulating to realize, also has MCLK in the input signal, its frequency is 4 times of bit clock CLK frequency, a lot of fpga chips all has DLL circuit (clock multiplier circuit), MCLK is after twice frequency multiplication, frequency is 1024 (MCLK4) times of LRCLK, adopt the mode of phase multiply accumulating, use single multiplier, realize the FIR filter of 8 128 length, when the method that adopts the phase multiply accumulating realized: each MCLK4 cycle once took advantage of and adds calculating, and filter coefficient needn't load, in the FIR filter coefficient storage, the phase is read a coefficient weekly; When needs reset and change processing mode and algorithm, as long as coefficient address is pointed to new coefficient address.
Circuit logic in data outputting module and the data reception module is opposite substantially, now to get and after two 24 binary number carry out the MS conversion, send into (32 of latchs then, high-order sign extended) rising edge and the trailing edge at LRCLK respectively has a load signal, when the data shift of serial shift output register outputs to last, the trailing edge of bit clock with the data load in the latch to serial shift output register (loading synchronously).
In the common processing mode, when realizing virtual sound effective value, introduced RMR room reverb sound, make that reverberation effect is the replaying effect in certain room, the virtual surround sound that the present invention realizes is then different, when realizing virtual sound image, adopt be the time at random with the method for amplitude surround sound decorrelation at random, make that the reverberation sound correlation of virtual playback is very low, can not form acoustic image, when the acoustical signal that adopts after loud speaker and Headphone reproducing the present invention handle, the surround sound nature that fictionalizes, true; The most of DSP of employing of similar system realizes, more complicated all, to the requirement of system than higher, the present invention uses the monolithic fpga chip to realize, has utilized the ram in slice among the FPGA, does not need external memorizer spare, external equipment is few, 4 frequencys multiplication that adopt the voice signal master clock need not external clock as work clock, the convenient use; In the application of the present invention,, just can transform to ASIC (application-specific integrated circuit (ASIC)) easily as long as certain processing procedure is solidificated among the FPGA.
When the method that directly adopts time-delay added reverberation sound, the reverberation sound that obtains had pectination frequency response (when the odd-multiple of the half-wavelength of the frequency of delay time correspondence).The present invention adopts the decorrelation of removing original surround channel and the new surround channel that synthesizes at random of discrete random delay and amplitude here simultaneously, makes it to have better output effect.
Description of drawings
Fig. 1 is a theory diagram of the present invention,
Fig. 2 is a hardware system block diagram of the present invention,
Fig. 3 is the structure chart of one embodiment of the present invention,
Fig. 4 is the I that the embodiment of the invention adopted
2S data format schematic diagram.
Embodiment
Figure 2 shows that the hardware structure diagram of implementation algorithm on FPGA, the circuit in this structure chart is FPGA and goes up corresponding signal transmssion line, and the module among this figure is the circuit set that realizes this function among the FPGA.Among the figure:
(1) Con1, Con2 and Con3 are three tunnel control signals, provide source type to system, sampling rate and signal format information and repositioning information.After treatment system enters running status, according to sampled signal frequency (LRCLK), periodically this signal is read in control signal register (with the register of FPGA realization), and according to the decision of the value in control register processing mode, details is as follows: sample rate manner of playback channel number Con3, Con2, Con148KHz earphone 2 visual 00048KHz loud speakers 2 visual 00148KHz earphones 2 downmix 01048KHz loud speakers 4 visual 01144.1KHz earphones 2 visual 10044.1KHz loud speakers 2 visual 10144.1KHz earphones 2 straight-through 11044.1KHz loud speakers 2 straight-through 111
That (2) indicate is three road I
2S (inter-IC SOUND, a kind of data format of chip chamber transmission voice signal) voice signal (I
2S signal format is by shown in Figure 4, M among the figure is the abbreviation of MSB, the highest order of expression signal encoding, SWS among the figure is LRCLK herein, SCL among the figure is CLK herein, SDA among the figure is SDIN1, SDIN2 and SDIN3 herein, and the form of three circuit-switched data signals is identical, has only drawn a data path signal among the figure).SDIN1 is first via I
2The S signal when being low level, is the L channel sampled voice signal at LRCLK, when LRCLK is the R channel sampled voice signal during for high level, L channel preceding R channel after.SDIN2 is the second road I
2The S signal when being low level, is left surround channel sampled voice signal at LRCLK, when LRCLK is right surround channel sampled voice signal during for high level, left surround channel preceding right surround channel after.SDIN3 is Third Road I
2The S signal when being low level, is the center channel sampled voice signal at LRCLK, when LRCLK is a bass effect sound channel sampled voice signal during for high level, center channel preceding bass effect sound channel after.
(3) CLK is a bit clock, and when sample frequency was 48KHz, CLK was 3.072MHz, and when sample frequency was 44.1KHz, CLK was 2.8224MHz, and when sample frequency was 32KHz, CLK was 2.048MHz, and alignment thereof is seen shown in Figure 4.
(4) LRCLK is a left and right sides clock, is called sampling clock again, and its frequency equals the sample frequency of voice signal, and 32KHz, 44.1KHz and 48KHz etc. are arranged.The alignment thereof of sampling clock is seen shown in Figure 4.
(5) control signal module comprises two parts: processing mode control module and processing synchronization control module.The outside control signal of processing mode control module sampling is stored in them in the control signal register.This module determines that according to the value decoding of control signal register sample rate, signal type, the processing mode handled are selected, suitable coefficient is also selected in system reset.Control signal is provided by the audio frequency Play System that system served; This module is at external control signal buffer status of each LRCLK cyclic polling, and according to the resetting of the state decision systems of control signal, parameter loading, processing mode change etc.
(also special reset signal can be set when being decoded as reset signal, the cited execution mode of the present invention does not have special reset signal, be when value in the control signal register changes, just produce reset signal) time, this module produces reset signal, when being reset to low level, all registers, latch and the memory that participate in work among the FPGA are reset to power-up state.
And this module is delivered to the signal sampling frequency signal that decoding obtains, and in (7) (8), is calculated the offset address of time delayed signal by them.Simultaneously with sample rate flag register (2bit, the signals sampling frequency that sign is being handled, b01:32KHz; B10:44.1KHz; B11:48KHz, initial value are 48KHz) in value relatively, if different, first resetting system suspends and handles, and reloads filter coefficient.Trailing edge at LRCLK restarts to handle then.Con3 sample rate flag register value 48KHz 1144.1KHz 10 (other state need not)
Above-mentioned execution mode can be handled two kinds of different manner of playback: earphone and loud speaker, the coefficient difference of the filter of this dual mode, if employing Headphone reproducing, then the control signal kind can decode processing mode and select signal, with him and processing mode register (2bit, b10: loud speaker, b01: earphone, b11: straight-through) value in compares, if different, processing mode is the same.Con3, Con2, Con1 manner of playback register value 0 earphone 011 loud speaker 10010 downmix 0011x straight-through 11
Above-mentioned execution mode can be handled the voice signal of two kinds of different forms, be 5.1 sound channels and two channel stereo signal, in the control signal module, signal format register (2bit, b01:5.1 sound channel are arranged, b10: stereophony), in control signal, can decode, the information source format information, with the value in it and the signal format register relatively, if different, processing mode is the same.Coded system is with the sample rate register.
Handle synchronization control module and be responsible for the system handles Synchronization Control, comprise, 5 up counter COUNTER5, counting clock is CLK, the rising edge counting, with the variation of LRCLK be 0 along corresponding Counter Value.When COUNTER5 is b11000, produce the high level signal Lat_Sig of a CLK clock cycle, send into the latch signal of data reception module as latch.
(6) data reception module.It is with multichannel I
2The S signal by serial to parallel conversion, latch, after the MS conversion, send into processing module after adjusting form.
Wherein, (shift_1, shift_2 realize that shift_3) CLK is as the shift clock of shift register to serial to parallel conversion, and rising edge triggers by three 32 SI PO shift registers;
(latch1, latch2 latch3), are realized by three 24 bit registers, because I latch
2The valid data code length of data is generally 24bit in the S signal, so as long as 24bit.At the rising edge of Lat_Sig, [31,8] position of shift register is latched in [23,0] of latch;
The MS conversion module is made up of two 24 adders and two 24 subtracters.If LRCLK is low, the input data in three shift registers be L channel, a left side around with the voice signal of center channel, otherwise the input data in three shift registers be R channel, right around with the voice signal of bass effect passage.When COUNTER5 is b11001, if LRCLK is low, deposit the data in latch 1 and 2 in 24bit buffer memory (temp1, temp2, temp3), if LRCLK is a high level, then there are adder and subtracter to realize the MS conversion of left and right acoustic channels and left and right sides surround channel respectively, with temp3 and latch_3 addition, itself and take advantage of 1.414 after, deposit latch_3 in.Transformation results deposit in 24 of four latchs (latch_L, latch_R, latch_Ls, latch_Rs), with data among the latch_L and latch_3 addition, the result deposits latch_L in.
For form adjustment and output: if adopt serial FIR filter form to realize, then should be with the displacement of the data serial in latch output, the shift register of going here and there out incorporating into of 24bit is added in superincumbent latch back, end position zero padding, clock adopts CLK, loads during for b00000 at COUNTER5; If adopt the method for phase multiply accumulating to realize, then adopt and line output.
(7) be Ls, Rs inhibit signal memory module, coexistence storage 2*768*24=36864 position.Left and right sides surround channel is respectively stored 768 points.By one 10 base address register (addr_base), deposit the base address, this address correspondence be the sample value of a up-to-date left and right sides surround channel in the memory space.One 10 address offset register, the address in the register are the addresses of the corresponding time-delay surround sound of reverberation time-delay.In each LRCLK cycle, this memory module is upgraded a sampling point, and base address register adds 1 simultaneously, and the address institute how in the register of address has surpassed the memory space of memory module, and register returns zero.The cheap register value in address that while must make new advances according to the base address (on the base address, add fixed value,, calculate the value after crossing the border) if cross the border.Send the decorrelation address offset here from the decorrelation address generator in addition, obtain postponing the surround sound sample value with address offset and base address addition.
Corresponding different execution modes, this module provides different output interfaces.Serial FIR: module is in each LRCLK cycle during in fixation of C OUNTER5 value (b00001), read time-delay surround sound sampling point from memory space, take advantage of weighted value (realizing) to send into buffer (buffer1 by multiplier, buffer2), adopt with (6) in identical hardware configuration carry out the MS conversion, when COUNTER5 is b00000, gone here and there out in the shift register displacement output incorporating into of the data load to 24 among buffer1 and the buffer2; If adopt the method for phase multiply accumulating to realize, then adopt and line output.
(8) decorrelation address generation module, this module are finished the function of D11, D12 among the figure one, D21, D22, D31, D32 part.The hardware that it comprises has, base address register, offset address register.
Base address register points to the surround sound sampling point of latest update, and base address register (10bit) is zero when powering in system, and after system started working, each LRCLK cycle added 1, and make zero (1024) when being added to inhibit signal length.Two offset address registers (10bit), the storage addresses side-play amount, what reality was corresponding is different time of delay, this delay time is fixed, and is determined by the signals sampling frequency.
When the signal sampling frequency is respectively 240 and 538 for the offset address register value during for 48KHz, when sample frequency is 44.1KHz, be 220 and 485.
The function of module (8) also is to generate an address offset, this is offset on the basis of the base address of (7) and offset address and has added a random address, surround sound signal in these three addresses and the address pointed, the inhibit signal of LS, RS all leaves in (7), passes through the reverberation sound signal of random delay exactly.
The generation of random address adopts the M sequencer on 11 rank and one 7 the shift register that seals in and go out to realize; When adopting serial FIR filter to realize, the shift register of M sequencer and its back is clock with CLK; When the summation realization was multiplied each other in employing, adopting MCLK4 was that the M sequence produces clock and shift register shift clock.Have the symbol offset address to deliver to (7) in the worthwhile work of shift register at the rising edge of each clock and ask the location to calculate, if this offset address first place of 7 is 1, then address offset is for negative, and the first place is 0 address offset for just.For D21 and D22, back 6 that get shift register are the random address skew, and the first place is a sign bit.
(9) be the FIR filter coefficient storage, depositing 8 groups of FIR filter coefficients in this memory, each group all is with the fixed coefficient of number of people transfer function through equalization weights, corresponding different processing modes (earphone, loud speaker) and 8 groups of filter coefficients of two kinds of different signal formats (5.1 sound channels and stereophony) and corresponding different sample frequencys.When system powered on, default loud speaker Processing Algorithm with 5.1 sound channels FIR coefficient accordingly was loaded in the FIR bank of filters.
Coefficient sets is stored among the BRAM (block storage) of FPGA, and each BRAM has 4096bit, and each BRAM can 16bit value of access in the monocycle.In the memory filter coefficient, realize one section continuous memory space with the BRAM in the sheet of FPGA, filter coefficient is stored to high-end sequence of addresses from the low side address.
(10) being processing module, is the mode that adopts serial FIR filter to realize shown in Fig. 2.Each FIR filter is made up of the serial filter of a plurality of four taps, each four tap serial filter can be realized a sampling point processing (a sample value input, a sample value output) of FIR filter at maximum 24 CLK in the clock cycle, can draw the sum of products of four sampled points and four filter coefficients.Each FIR filter 128 rank is realized by 32 four tap filters.After 24 clock cycle, the output addition with 32 four tap filters obtain obtains the output of 128 rank filters.When powering in system, loads the coefficient of each FIR filter, the appearance of reset signal also can allow system's FIR coefficient of reloading, the FIR filter coefficient is the integer of 16bit, because in the filtering, filter will use these filter coefficients simultaneously, so these coefficients will be moved to the register of filter coefficient storage.The FIR filter of this part also can adopt the mode of phase multiply accumulating to realize.Also has MCLK in the input signal, its frequency is 4 times of bit clock CLK frequency, a lot of fpga chips all has DLL circuit (clock multiplier circuit), MCLK is after twice frequency multiplication, frequency is 1024 (MCLK4) times of LRCLK, adopt the mode of phase multiply accumulating, use single multiplier, realize the FIR filter of 8 128 length.
When the method that adopts the phase multiply accumulating realizes, each MCLK4 cycle once takes advantage of and adds calculating, filter coefficient needn't load, in (9), phase is read a coefficient weekly, when needs reset and change processing mode and algorithm, as long as coefficient address is pointed to new coefficient address.
The generation of address: generated by the value sum in base address register and the address offset register, the address value correspondence of generation specific filter coefficient value among the BRAM of memory filter coefficient sets.When the method that adopts the phase multiply accumulating realizes, a base address table of being realized by registers group will be arranged, the first address of the FIR groups of filter coefficients that the value in the address table is corresponding different, when handling operation, to corresponding address in the table of base address be loaded in the base address register according to different external control signal values (seeing (5)).The address offset register is realized that by an increment register initial address is 0, and register value adds 1 in each MCLK4 cycle, makes zero when the address offset register is increased to 1024.
The storage of input data when employing takes advantage of add mode to realize: the input data are through the input of the filter after the MS conversion, and each FIR filter (128 rank) needs 128 continuous signal histories input.They also adopt the BRAM storage, and that need store in BRAM has four sections, MS_L, and MS_R, MS_Ls, MS_Rs, every segment data has 128 points, upgrades a sampling point in each LRCLK cycle, and each all sampling point of LRCLK cycle is read out once.Read/write address is all produced by corresponding address register, and four base address registers are realized by increment register, wherein deposit the up-to-date sampling point address of corresponding four segment datas, and each LRCLK cycle adds 1; The address offset register also realizes that by increment register each MCLK4 cycle adds 1, makes zero when being added to 128.
In each MCLK4 cycle, take advantage of and add processing module and read data from the coefficient storage space and the data space of coefficient address and data address correspondence respectively, restore in the output buffers with the data addition in the output buffers in the back of multiplying each other, per 128 all after dates, data latching in the output buffers is arrived corresponding latch, wait for MS conversion, alignment and output, upgrade the base address in data address register and the coefficient address register simultaneously, carry out the calculating of next FIR filter.
(11) this part is made up of a plurality of multibit adders, is combinational logic, realizes the function with the sampled value addition of the sampled value of the central corridor of 5.1 path voice signals of same sampling instant and bass effect passage.
(12) data outputting module, opposite substantially in its circuit logic and (6), now to get and after two 24 binary number carry out the MS conversion, send into (32 of latchs then, high-order sign extended) rising edge and the trailing edge at LRCLK respectively has a load signal, when the data shift of serial shift output register outputs to last, the trailing edge of bit clock with the data load in the latch to serial shift output register (loading synchronously).
(13) SDOUT is a binaural signal of handling back output, also is I
2S form, L channel are preceding, and be high-order preceding.The trailing edge of CLK in the voice signal form alignment (14) is at LRCLK output L channel during for low level, output R channel when LRCLK is high level.
(14) CLK output and LRCLK output are for synchronous I
2The clock output of S signal.This clock also can be synchronously unified by external clock, just do not need to have exported here.
Fig. 3 is the structure chart of one embodiment of the present invention.Corresponding module all is parts on the circuit board and interface etc.Among the figure:
(1) be fpga chip, what the present invention adopted is the XC2s200 Series FPGA of Xilinx company.This chip power supply voltage is 3.3V, core work voltage 2.5V,
(2) PROM, serial PROM (One-Time Programmable ConfigurationPROM), the config memory of Xilinx company, model is XC17S200.When system powered on, the data among the PROM were configured among the FPGA automatically.
(3) jtag interface, the test of standard and debugging interface, the fpga chip of Xilinx company is supported this interface.When PROM does not have data, can pass through parallel cable-jtag interface, download net table and initialization data to FPGA.The holding wire of mainly using is TDI, TDO, TMS, TCK.
(4) digital audio input interface is an interface for the treatment of deal with data.Requiring the data of audio signal is I
2The S form, and bit clock (CLK) and sampling clock (LRCLK) will be provided.The present invention does not do requirement to the hardware interface form of audio input interface.
(5) the testing needle function is that test intermediate treatment result is for the system of practical application in debugging, and testing needle is useless.
(6) controlling and reply interface, is the interface of FPGA harmony Play System communication.System provides switching signal, and whether control FPGA works; Provide number of people transfer function to select signal, carry out the selection of treatment effect;
Whether normally FPGA also can export some state informations, as the operation etc. of: current processing mode, system.
(7) the digital audio output interface is to speaker playback unit output I
2The digital audio signal of S form, this signal have passed through twin loudspeaker virtual reproduction algorithm process.
(8) be the power management module of FPGA treatment system, for the consuming parts on the plate provides power supply.Main supply power voltage is+5V, obtains+3.3V through TPS318 (+5V-+3.3V voltage regulator), and+5V voltage obtains+2.5V voltage through 1117 (+5V-+2.5V voltage regulators).Device on the plate, FPGA XC2S200 need operating voltage+3.3V and+2.5V; The supply power voltage of PROM is+3.3V; The worker of D/A converter organizes voltage and is+5V; The supply power voltage of earphone power amplifier part is ± 12V.
(9) the D/A converter is selected CS4340KS for use, changes one road I
2The digital audio signal of S form is the two-way analog signal.
(10) this power amplifier is specialized in the Headphone reproducing use, and the earphone power amplifier has had a lot of ripe circuit, and many special chips are also arranged, and is not core of the present invention here, does not describe in detail.
(11) the digital audio pattern of the input is seen Fig. 4.
(12) digital audio signal of output also is I herein
2The S form, with (7) locate different, road I herein
2S is the dual track data through earphone virtual surround sound algorithm process that are fit to Headphone reproducing.Owing to can not use earphone repeat again simultaneously, use loud speaker to retransmit again, can not occur simultaneously so the signal that (12) are located is exported the signal output of locating with (7), and determine this two those dateouts of port, determine by control signal.
(13) dual track analog signal.
(14) through the dual track analog signal of power amplification, have the standard earphone interface.
The execution mode that the present invention is cited; only be to realize a kind of concrete scheme of the present invention; do not represent and to realize all technical schemes of the present invention; everyly can take the method identical or approximate with the present invention; reach the technical scheme of identical effect, all should be within protection scope of the present invention.
Claims (24)
1, a kind of 5.1 channel virtualized low voice speaking methods of putting based on FPGA, its method for the employing time-delay of surround channel adds reverberation, it is characterized in that adopting discrete random delay and amplitude to remove the relevant of original surround channel and the new surround channel that synthesizes at random.
2, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 1, it is characterized in that delaying time is that left and right sides surround sound to voice signal postpones to handle at random.
3, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 2, at random the datum mark of it is characterized in that delaying time can be taked one or more.
4, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 3, it is characterized in that the voice signal to input is the voice signal of 5.1 paths, time-delay can be benchmark with 5ms, randomized jitter, in the scope of ± 0.25ms according to even distribution change at random.
5, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 3, it is characterized in that the voice signal to input is the voice signal of 5.1 paths, also can to adopt 11ms be the time-delay of benchmark in time-delay, randomized jitter, in ± 0.5ms scope according to even distribution change at random.
6, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 1 is characterized in that amplitude datum mark at random, can take one or more.
7, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 6, when it is characterized in that time-delay is benchmark with 5ms, amplitude weighting is a benchmark with 0.5, and scope changes between 0.25-0.75, randomized jitter, in ± 0.25 scope according to similar Gaussian Profile change at random.
8, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 6, when it is characterized in that time-delay is benchmark with 11ms, amplitude weighting changes between 0-0.5, makes that amplitude weighting is is average equally distributed stochastic variable in the scope of 0-0.5 with 0.25.
9, as claim 2 or the 6 described 5.1 channel virtualized low voice speaking methods of putting based on FPGA, it is characterized in that reasonable mode is can adopt simultaneously with 5ms to be the time-delay of benchmark and to be the time-delay of benchmark with 11ms, and corresponding amplitude weighting.
10, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 1, it is characterized in that concrete implementation is that (L represents L channel, R represents R channel, Ls represents left surround sound sound channel, Rs represents right surround sound sound channel, C is a center channel, and LFE is that the low-frequency effect sound channel (if the voice signal of input is a stereophony, then import by center channel and low-frequency effect sound channel no signal; Left and right surround sound sound channel is the left and right acoustic channels voice signal of input stereo audio respectively)):
A is with the sampled value of the central corridor (C) of 5.1 path voice signals of same sampling instant and the sampled value addition of bass effect passage (LFE);
B is with above-mentioned additive value convolution or multiply each other, and makes it to enlarge 1.414 times, and then is input in the L channel;
The voice signal of C left and right sound channels is through the MS conversion;
The signal plus of left channel signals after the D conversion and B step input carries out the Sigma_1 convolution again;
Right-channel signals after the E conversion is through the Sigma_r convolution;
The left and right surround sound sound channel of F is provided with three modules that the left and right sides surround sound of voice signal is postponed to handle simultaneously, and respectively voice signal is carried out the MS conversion; Wherein two (corresponding left and right surround sound sound channel respectively) do not carry out any processing to the voice signal of 5.1 paths, when the voice signal of input is the stereophony voice signal, then postpones the processing of decorrelation; Two in addition (corresponding left and right surround sound sound channel respectively) postpones the decorrelation processing to the voice signal of 5.1 paths of input, and the delay reference time is 5ms; In addition two (corresponding left and right surround sound sound channels respectively) then postpone decorrelation to the voice signal of 5.1 paths of input and handle, and the delay reference time is 11ms;
The voice signal of 5.1 paths that the module that G postpones to handle through left and right sides surround sound does not postpone to handle, the signal of left surround sound sound channel carries out the Delta_11 convolution, and the signal of right surround sound sound channel carries out the Delta_r1 convolution;
The module that H postpones to handle through left and right sides surround sound is carried out the voice signal that be the delay processing of 5ms fiducial time, and the signal of left surround sound sound channel carries out the Delta_12 convolution, and the signal of right surround sound sound channel carries out the Delta_r2 convolution;
The module that I postpones to handle through left and right sides surround sound is carried out the voice signal that be the delay processing of 11ms fiducial time, and the signal of left surround sound sound channel carries out the Delta_13 convolution, and the signal of right surround sound sound channel carries out the Delta_r3 convolution;
Left and right surround sound sound channel signal addition respectively after the J convolution, and correspondence is input in the left and right sound channels;
The left surround sound sound channel signal of addition and the left channel signals addition after the convolution after the K convolution; Simultaneously, the right surround sound sound channel signal of addition and the right-channel signals addition after the convolution after the convolution;
The above-mentioned K step added signal of L is input to the output balance module through the MS conversion;
The M balance module carries out the tone color equilibrium treatment to the signal of input, and retransmits by left and right acoustic channels.
11, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 10, it is characterized in that the module that the above-mentioned voice signal left and right sides surround sound to 5.1 paths postpones to handle, except that the voice signal to 5.1 paths postpones to handle, in other cases, there is not the voice signal input.
12, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 10, it is characterized in that the module that the above-mentioned voice signal left and right sides surround sound to 5.1 paths postpones to handle, wherein the voice signal of 5.1 paths is not postponed the module handled, when input audio signal is the voice signal of 5.1 paths, this module is not carried out any processing, is equivalent to lead directly to; Only the stereophony voice signal to input carries out the delay decorrelation processing that the delay reference time is 5ms.
13, the 5.1 channel virtualized low voice speaking methods of putting based on FPGA as claimed in claim 10, the coefficient of equalizing wave filter that it is characterized in that equilibrium treatment is to handle in a manner mentioned above with white noise signal, the signal that obtains does not carry out equilibrium treatment, but carries out that inverse filtering obtains.
14, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 1 is characterized in that having adopted EPGA (gate array can be edited in the scene), as realizing the 5.1 channel virtualized low voice speaking devices of putting.
15, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 2, it is characterized in that above-mentioned device comprises: control signal module, bit clock, left and right sides clock, data reception module, Ls, Rs inhibit signal memory module, decorrelation address generation module, FIR filter coefficient storage, processing module, adder, data outputting module, wherein:
The control signal module, comprise two parts: processing mode control section and processing Synchronization Control part, the control signal of the module samples outside of processing mode control section, they are stored in the control signal register, this module determines that according to the value decoding of control signal register sample rate, signal type, the processing mode handled are selected, suitable coefficient is also selected in system reset; Handle synchronization control module and be responsible for the system handles Synchronization Control, it comprises up counter, counting clock, the rising edge counting;
Left and right sides clock is called sampling clock again, and its frequency equals the sample frequency of voice signal;
Data reception module is with multichannel I
2The S signal by serial to parallel conversion, latch, after the MS conversion, send into processing module after adjusting form; Serial to parallel conversion is realized that by SI PO shift register CLK is as the shift clock of shift register, and rising edge triggers; Latch is realized by register; The MS conversion module is made up of position adder and position subtracter;
Ls, Rs inhibit signal memory module by base address register (addr_base), are deposited the base address, this address correspondence be the sample value of a up-to-date left and right sides surround channel in the memory space; Address offset register, the address in the register are the addresses of the corresponding time-delay surround sound of reverberation time-delay;
Decorrelation address generation module, the hardware that it comprises has, base address register, offset address register; Base address register points to the surround sound sampling point of latest update, be zero when base address register powers in system, after system starts working, each LRCLK cycle adds 1, when being added to inhibit signal length, make zero, the address offset amount that the offset address register is deposited, what reality was corresponding is different time of delay, this delay time is fixed, and is determined by the signals sampling frequency;
The FIR filter coefficient storage, depositing many group FIR filter coefficients in this memory, each group all is with the fixed coefficient of number of people transfer function through equalization weights, corresponding different processing modes (earphone, loud speaker) and many groups filter coefficient of two kinds of different signal formats (5.1 sound channels and stereophony) and corresponding different sample frequencys;
Processing module, the mode that adopts serial FIR filter to realize;
Circuit logic in data outputting module and the data reception module is opposite substantially, now to get and after two 24 binary number carry out the MS conversion, send into (32 of latchs then, high-order sign extended) rising edge and the trailing edge at LRCLK respectively has a load signal, when the data shift of serial shift output register outputs to last, the trailing edge of bit clock with the data load in the latch to serial shift output register (loading synchronously).
16, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 15, the control signal that it is characterized in that above-mentioned device is provided by the audio frequency Play System that system served, and this module is at external control signal buffer status of each LRCLK cyclic polling, and according to the resetting of the state decision systems of control signal, parameter loading, processing mode change etc.
17, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 15, it is characterized in that above-mentioned data reception module, if LRCLK is low, input data in three shift registers be L channel, a left side around with the voice signal of center channel, otherwise the input data in three shift registers be R channel, right around with the voice signal of bass effect passage.
18, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 15, it is characterized in that above-mentioned Ls, Rs inhibit signal memory module, in each LRCLK cycle, this memory module is upgraded a sampling point, base address register adds 1 simultaneously, address institute how in the register of address has surpassed the memory space of memory module, register returns zero, the cheap register value in address that must make new advances according to the base address simultaneously (adds fixed value on the base address, if cross the border, value after calculating is crossed the border), sends the decorrelation address offset here from the decorrelation address generator in addition, obtain postponing the surround sound sample value with address offset and base address addition.
19, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 15, it is characterized in that above-mentioned decorrelation address generation module generates an address offset, this is offset on the basis of the base address of Ls, Rs inhibit signal memory module and offset address and has added a random address, surround sound signal in these three addresses and the address pointed, the inhibit signal of LS, RS all leaves in Ls, the Rs inhibit signal memory module, passes through the reverberation sound signal of random delay exactly.
20, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 16 is characterized in that the generation of above-mentioned random address, adopt the M sequencer on 11 rank and one 7 the shift register that seals in and go out to realize; When adopting serial FIR filter to realize, the shift register of M sequencer and its back is clock with CLK; When the summation realization is multiplied each other in employing, adopting MCLK4 is that the M sequence produces clock and shift register shift clock, the rising edge of each clock with the worthwhile work of shift register have the symbol offset address to deliver to Ls, Rs inhibit signal memory module is asked the location.
21, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 15, it is characterized in that above-mentioned FIR filter coefficient storage when system powers on, default loud speaker processing mode with 5.1 sound channels FIR coefficient accordingly is loaded in the FIR bank of filters.
22, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 15, it is characterized in that above-mentioned processing module, its each FIR filter is made up of the serial filter of a plurality of four taps, each four tap serial filter can be realized a sampling point processing (sample value input of FIR filter at maximum 24 CLK in the clock cycle, a sample value output), when powering in system, loads the coefficient of each FIR filter, the appearance of reset signal also can allow system's FIR coefficient of reloading, because in the filtering, filter will use these filter coefficients simultaneously, so these coefficients will be moved to the register of filter coefficient storage.
23, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 22, the FIR filter that it is characterized in that processing module also can adopt the mode of phase multiply accumulating to realize, also has MCLK in the input signal, its frequency is 4 times of bit clock CLK frequency, a lot of fpga chips all has DLL circuit (clock multiplier circuit), MCLK is after twice frequency multiplication, frequency is 1024 (MCLK4) times of LRCLK, adopt the mode of phase multiply accumulating, use single multiplier, realize the FIR filter of 8 128 length.
24, the 5.1 channel virtualized low voice speaking devices of putting based on FPGA as claimed in claim 23, it is characterized in that when the method that adopts the phase multiply accumulating realizes: each MCLK4 cycle once takes advantage of and adds calculating, filter coefficient needn't load, in the FIR filter coefficient storage, the phase is read a coefficient weekly; When needs reset and change processing mode and algorithm, as long as coefficient address is pointed to new coefficient address.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100396162C (en) * | 2004-07-14 | 2008-06-18 | 华南理工大学 | Signal processing method for three-loudspeaker virtual 5.1 channel surround sound |
| CN101064974B (en) * | 2006-04-28 | 2012-05-23 | 雅马哈株式会社 | Sound field controlling device |
| CN102760437A (en) * | 2011-04-29 | 2012-10-31 | 上海交通大学 | Audio decoding device of control conversion of real-time audio track |
| CN103970693A (en) * | 2014-05-22 | 2014-08-06 | 三星半导体(中国)研究开发有限公司 | Integral integrated circuit sound circuit |
| CN106231489A (en) * | 2016-07-25 | 2016-12-14 | 深圳市米尔声学科技发展有限公司 | The treating method and apparatus of audio frequency |
| CN109644315A (en) * | 2017-02-17 | 2019-04-16 | 无比的优声音科技公司 | Device and method for the mixed multi-channel audio signal that contracts |
| WO2020087678A1 (en) * | 2018-11-01 | 2020-05-07 | 华南理工大学 | Surround-sound virtual playback method in multi-channel three-dimensional space |
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| CN100396162C (en) * | 2004-07-14 | 2008-06-18 | 华南理工大学 | Signal processing method for three-loudspeaker virtual 5.1 channel surround sound |
| CN101064974B (en) * | 2006-04-28 | 2012-05-23 | 雅马哈株式会社 | Sound field controlling device |
| CN102760437A (en) * | 2011-04-29 | 2012-10-31 | 上海交通大学 | Audio decoding device of control conversion of real-time audio track |
| CN102760437B (en) * | 2011-04-29 | 2014-03-12 | 上海交通大学 | Audio decoding device of control conversion of real-time audio track |
| CN103970693A (en) * | 2014-05-22 | 2014-08-06 | 三星半导体(中国)研究开发有限公司 | Integral integrated circuit sound circuit |
| CN103970693B (en) * | 2014-05-22 | 2017-02-22 | 三星半导体(中国)研究开发有限公司 | Integral integrated circuit sound circuit |
| CN106231489A (en) * | 2016-07-25 | 2016-12-14 | 深圳市米尔声学科技发展有限公司 | The treating method and apparatus of audio frequency |
| CN109644315A (en) * | 2017-02-17 | 2019-04-16 | 无比的优声音科技公司 | Device and method for the mixed multi-channel audio signal that contracts |
| WO2020087678A1 (en) * | 2018-11-01 | 2020-05-07 | 华南理工大学 | Surround-sound virtual playback method in multi-channel three-dimensional space |
| US11962995B2 (en) | 2018-11-01 | 2024-04-16 | South China University Of Technology | Virtual playback method for surround-sound in multi-channel three-dimensional space |
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