CN1438702A - Metal washer structure on semiconductor substrate - Google Patents
Metal washer structure on semiconductor substrate Download PDFInfo
- Publication number
- CN1438702A CN1438702A CN02105015A CN02105015A CN1438702A CN 1438702 A CN1438702 A CN 1438702A CN 02105015 A CN02105015 A CN 02105015A CN 02105015 A CN02105015 A CN 02105015A CN 1438702 A CN1438702 A CN 1438702A
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- metal gasket
- dielectric layer
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- pattern dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The structure of the pad comprises a first pattern dielectric layer and a first metal pad unit. The first pattern dielectric layer is formed on the semiconductor substrate, and the metal pad is located inside the first pattern dielectric layer to connect to the modules in the substrate electrically. The borderline shape of the first metal pad unit is polygons with each internal angle larger than 90 degrees in order to prevent chaps at corner angles of the polygon in dielectric layers around the first metal pad caused by stress concentration in period of chemical mechanical polishing process.
Description
Technical field
The invention relates to a kind of structure of semiconductor integrated circuit, particularly, low dielectric layer is caused damage in order to reduce mechanical stress about the structure of a kind of metal gasket (pad).
Background technology
In the semiconductor fabrication now, along with the development of size of components downsizing and the demand that improves assembly operation speed, have the copper metal of low resistance constant and high electron mobility impedance, be used to material gradually, replace aluminum metal processing procedure technology in the past as the metal inside line.Wherein cooperate inserted (damascene) interconnector technology of copper metal not only can reach the downsizing of interconnector and can reduce time delay (RC delay), also solve simultaneously the problem that the copper metal etch is difficult for, therefore become the main development trend of multiple now interconnector.
When the main circuit zone forms the mosaic copper interconnector, also form large-area copper metal structure in joint sheet (bonding pad) zone of above-mentioned periphery.Its generation type be by lithography behind the groove that defines square or rectangle on the dielectric layer, then with chemical vapour deposition (CVD) (chemicalvapor deposition, CVD) method forms copper metal layer on dielectric layer and in the groove, remove unnecessary copper metal on the dielectric layer with cmp (CMP) method at last, only stay the copper metal in the groove, as metal gasket.Yet metal gasket is generally square or rectangle, so when carrying out the CMP program, the mechanical stress of generation is easily damaged the dielectric layer around the metal gasket, and particularly at the corner of metal gasket, the phenomenon of can chap (crack).
In order further to understand above-mentioned problem, below cooperate Fig. 1 and Fig. 2 that known metal pad structure is described.At first, please refer to Fig. 1, it expresses the profile of known metal pad structure.Wherein, label 100 is the semiconductor substrate, is formed with the several semiconductor assembly on it, is simplicity of illustration herein, only expresses a smooth substrate.One first pattern dielectric layer 102 is formed in this substrate 100 with as metal intermetallic dielectric layer (inter-metal dielectric, IMD), it for example is low dielectric material layer, and one first metal gasket unit 101, external form is square or rectangle, be formed in this metal intermetallic dielectric layer 102, with lead as above-mentioned semiconductor subassembly.Afterwards, on the first pattern dielectric layer 102 and the first metal gasket unit 101, be formed with one second pattern dielectric layer 104, and the dielectric layer 104 that is positioned at 101 tops, the first metal gasket unit is formed with interlayer hole (via hole) 104a, copper metal plug (plug) 104b is arranged, in order to electrically connect the first metal gasket unit 101 in the interlayer hole 104a.Then, be formed with one the 3rd pattern dielectric layer 106 and the second metal gasket unit 105 on the second pattern dielectric layer 104.These metal gasket unit 105 external forms are similarly square or rectangle, are to do to electrically connect also as the connection pad (bonding pad) that is connected external circuit with the semiconductor subassembly in the substrate 100 in order to pass through the connector 104b and the first metal gasket unit 101.At last, above the second metal gasket unit, 105 peripheries, be formed with a passive state (passivation) protective layer 108, in follow-up encapsulation (package) process, do not suffer damage with protection connection pad 105.
Yet, please refer to Fig. 2, it is expressed according to the first pattern dielectric layer 102 of Fig. 1 and the vertical view of the first metal gasket unit 101.As mentioned above, carrying out the CMP program when forming this metal gasket unit 101, since the first pattern dielectric layer, 102 mechanical strengths a little less than, therefore under the effect of grinding stress, in the corner of the first metal gasket unit 101 stress taking place and concentrate and dielectric layer 102 generation be full of cracks, badly influences the electrical characteristics of assembly and the quality of product easily.
Summary of the invention
In view of this, the object of the present invention is to provide the structure of the suprabasil metal gasket of a kind of semiconductor, it is polygon and each interior angle greater than 90 ° metal gasket, make during carrying out cmp (CMP) program, can discharge the stress in metal gasket corner, prevent that the phenomenon of dielectric layer be full of cracks from taking place.
According to above-mentioned purpose, the invention provides the structure of the suprabasil metal gasket of a kind of semiconductor, comprising: one first pattern dielectric layer is formed at at semiconductor-based the end; And one first metal gasket unit, be arranged in the first pattern dielectric layer, wherein the peripheral shape of the first metal gasket unit is that polygon and each interior angle are greater than 90 °.Moreover the structure of above-mentioned metal gasket also comprises: one second pattern dielectric layer be formed on the first pattern dielectric layer and the first metal gasket unit, and the second pattern dielectric layer that is positioned at above first metal gasket has several interlayer holes; Several metal plugs are arranged in the interlayer hole, in order to electrically connect the first metal gasket unit; One the 3rd pattern dielectric layer is formed on the second pattern dielectric layer; One second metal gasket unit is arranged in the 3rd pattern dielectric layer and is positioned on the metal plug, in order to electrically connect with the first metal gasket unit by metal plug; And a protective layer, around periphery top, the second metal gasket unit, protecting this second metal gasket unit, and on this second metal gasket cell surface, form an opening.
This first pattern dielectric layer is a low dielectric material layer.
This first metal gasket unit is a bronze medal metal gasket.
This second pattern dielectric layer is an oxide layer.
These metal plugs are copper metal plugs.
The 3rd pattern dielectric layer is an oxide layer.
This second metal gasket unit is a bronze medal metal gasket.
This polygon is a kind of of a pentagon, hexagon, octagon and circle.
The peripheral shape of this second metal gasket unit is that polygon and each interior angle are greater than 90 °.
This protective layer is a kind of of silicon nitride and silica.
This polygon is a kind of of a pentagon, hexagon, octagon and circle.
Identical and the size of the peripheral shape of this opening of this protective layer is less than the peripheral shape of this second metal gasket unit.
Adopt structure of the present invention during carrying out cmp (CMP) program, can discharge the stress in metal gasket corner, can prevent effectively that metal gasket from causing the concentrated dielectric layer that causes of stress and chapping during making, and then improve the quality of product.
Description of drawings
Fig. 1 is the section of structure of known metal gasket;
Fig. 2 is according to the first pattern dielectric layer of Fig. 1 and the vertical view of the first metal gasket unit;
Fig. 3 is the section of structure according to the metal gasket of the embodiment of the invention;
Fig. 4 is according to the first pattern dielectric layer of Fig. 3 and the vertical view of the first metal gasket unit;
Fig. 5 is the vertical view of the 3rd pattern dielectric layer, the second metal gasket unit and protective layer according to Fig. 3.The number in the figure explanation:
100, the 300～semiconductor-based end;
101,301～the first metal gasket unit;
102,302～the first pattern dielectric layers;
104,304～the second pattern dielectric layers;
104a, 304a～interlayer hole;
104b, 304b～connector;
105,305～the second metal gasket unit (connection pad);
106,306～the 3rd pattern dielectric layers;
108,308～protective layer;
308a～opening.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperation Fig. 3-Fig. 5 are described in detail below:
At first, please refer to Fig. 3, it expresses the section of structure according to the metal gasket of the embodiment of the invention.Wherein, label 300 is the semiconductor substrate, and for example a silicon base is formed with the several semiconductor assembly on it, is reduced graph herein, only shows a smooth substrate.One first pattern dielectric layer 302 is formed in this substrate 300 with as metal intermetallic dielectric layer (IMD), for example is low dielectric material layer: FSG, HSQ and BD etc.Use these dielectric materials can reduce time delay (RC delay) effect, yet the mechanical strength of these materials is low, easily causes processing problems, will illustrate after a while at this paper.Then, one first metal gasket unit 301, for example a bronze medal metal is arranged in the metal intermetallic dielectric layer 302, with the lead as above-mentioned semiconductor subassembly.Afterwards, on the metal intermetallic dielectric layer (IMD) 302 and the first metal gasket unit 301, be formed with one second pattern dielectric layer 304, silicon oxide layer for example, and the second pattern dielectric layer 304 that is positioned at 301 tops, the first metal gasket unit has several interlayer holes (via hole) 304a.In these interlayer holes 304a, be provided with metal plug (plug) 304b, copper metal for example is in order to electrically connect the first metal gasket unit 301.Then, on the second pattern dielectric layer 304, be formed with one the 3rd pattern dielectric layer 306, for example silicon oxide layer.Wherein, the second metal gasket unit 305, for example a bronze medal metal is arranged in the 3rd pattern dielectric layer 306.This metal gasket unit 305 is in order to electrically connect with semiconductor subassembly in the first metal gasket unit 301 and the substrate 300 by connector 304b.Simultaneously, as the connection pad that connects external circuit.At last, a passive state (passivation) protective layer 308, for example silicon nitride and silica is a kind of, on second metal gasket unit connection pad 305 peripheries, does not suffer damage in follow-up encapsulation (package) process to protect the second metal gasket unit connection pad 305.This protective layer 308 forms an opening 308a on connection pad 305 surfaces, the second metal gasket unit, to expose connection pad 305 surfaces, the second metal gasket unit, electrically connect with external circuit by routing (bonding) program with convenient.
In the present embodiment, the peripheral shape that is in the first metal gasket unit 301 that is different from known metal pad structure be polygon and each interior angle greater than 90 °, for example be pentagon, hexagon, octagon and circular or the like.Its reason is as follows: as discussed previously, metal gasket unit generation type is after defining the groove of square or rectangle by the lithography program, then form copper metal layer on dielectric layer, to reach in the groove with the chemical vapor deposition (CVD) method, remove unnecessary copper metal on the dielectric layer with cmp (CMP) method at last, the copper metal that only stays in the groove is used as metal gasket.Yet, being subject to the external form of groove, metal gasket is generally square or rectangle, so when carrying out the CMP program, the mechanical stress of generation is easily damaged the dielectric layer around the metal gasket, particularly in the corner of metal gasket, can the chap phenomenon of (crack) of dielectric layer.Therefore, in the present embodiment, be to form earlier to have after polygon and the first pattern dielectric layer 302 of each interior angle greater than 90 ° groove (not indicating), then, please refer to Fig. 4, it shows according to the first pattern dielectric layer 302 of Fig. 3 and the vertical view of the first metal gasket unit 301, forms polygon and each interior angle greater than 90 ° the first metal gasket unit 301 by known CVD program and CMP program, be an octagon, as shown in the figure herein.Because the first metal gasket unit 301 that forms, its periphery is gone up each drift angle and is obtuse angle (＞90 °), so be able to being released of appropriateness at the stress that carries out being produced during the CMP program, therefore can not cause the first relatively poor pattern dielectric layer 302 of mechanical strength (that is, low dielectric material layer) that the situation of be full of cracks takes place.
Moreover, please refer to Fig. 5, it expresses the vertical view according to the 3rd pattern dielectric layer 306, the second metal gasket unit 305 and the protective layer 308 of Fig. 3.In the present embodiment, because the generation type of the second metal gasket unit 305 is identical with the first metal gasket unit 301, so its peripheral shape is to form polygon and each interior angle greater than 90 °, for example an octagon produces the problem of above-mentioned be full of cracks to prevent stress from concentrating.In addition, in order to cooperate the second metal gasket unit, 305 peripheral shapes, the identical and size of the opening 308a peripheral shape of protective layer 308 is less than the peripheral shape of the second metal gasket unit 305, as shown in the figure.Therefore, can prevent effectively that according to the present invention metal gasket from causing the concentrated dielectric layer that causes of stress and chapping during making, and then improve the quality of product.
In addition, in the present embodiment, only be formed with two metal gasket unit, yet be not limited in the metal pad structure that only has two metal gasket unit herein.That is, all can utilize the present invention to solve the problem of be full of cracks at metal pad structure with multi-metal pad unit.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; can do to change and retouching, so protection scope of the present invention should be as the criterion with claims of present patent application.
Claims (25)
1. the structure of the suprabasil metal gasket of semiconductor comprises one first pattern dielectric layer and one first metal gasket unit, it is characterized in that:
This first pattern dielectric layer was formed on this semiconductor-based end; And
This first metal gasket unit is arranged in this first pattern dielectric layer, and wherein the peripheral shape of this first metal gasket unit is that polygon and each interior angle are greater than 90 °.
2. the structure of the suprabasil metal gasket of semiconductor according to claim 1 is characterized in that, also comprises:
One second pattern dielectric layer is formed on this first pattern dielectric layer and this first metal gasket unit, and this second pattern dielectric layer that is positioned at above this first metal gasket unit has several interlayer holes;
Several metal plugs are arranged in this interlayer hole, and they are to electrically connect this first metal gasket unit;
One the 3rd pattern dielectric layer is formed on this second pattern dielectric layer;
One second metal gasket unit is arranged in the 3rd pattern dielectric layer and is positioned on these metal plugs, and this metal plug and this first metal gasket unit are with electric connection; And
The protective layer of one this second metal gasket unit of protection around periphery top, the second metal gasket unit, and forms an opening on this second metal gasket cell surface.
3. the structure of the suprabasil metal gasket of semiconductor according to claim 1 is characterized in that, this first pattern dielectric layer is a low dielectric material layer.
4. the structure of the suprabasil metal gasket of semiconductor according to claim 1 is characterized in that, this first metal gasket unit is a bronze medal metal gasket.
5. the structure of the suprabasil metal gasket of semiconductor according to claim 1 is characterized in that, wherein this polygon is a kind of of a pentagon, hexagon, octagon and circle.
6. the structure of the suprabasil metal gasket of semiconductor according to claim 2 is characterized in that, this second pattern dielectric layer is an oxide layer.
7. the structure of the suprabasil metal gasket of semiconductor according to claim 2 is characterized in that, these metal plugs are copper metal plugs.
8. the structure of the suprabasil metal gasket of semiconductor according to claim 2 is characterized in that, the 3rd pattern dielectric layer is an oxide layer.
9. the structure of the suprabasil metal gasket of semiconductor according to claim 2 is characterized in that, this second metal gasket unit is a bronze medal metal gasket.
10. the structure of the suprabasil metal gasket of semiconductor according to claim 2 is characterized in that, the peripheral shape of this second metal gasket unit is that polygon and each interior angle are greater than 90 °.
11. the structure of the suprabasil metal gasket of semiconductor according to claim 2 is characterized in that, this protective layer is a kind of of silicon nitride and silica.
12. the structure of the suprabasil metal gasket of semiconductor according to claim 10 is characterized in that, this polygon is a kind of of a pentagon, hexagon, octagon and circle.
13. the structure of the suprabasil metal gasket of semiconductor according to claim 10 is characterized in that, the identical and size of the peripheral shape of the opening of this protective layer is less than the peripheral shape of this second metal gasket unit.
14. a structure that is used for the suprabasil metal gasket of semiconductor comprises one first pattern dielectric layer, one second pattern dielectric layer; one the 3rd pattern dielectric layer, one first metal gasket unit, one second metal gasket unit; one protective layer and several metal plugs is characterized in that:
This first pattern dielectric layer was formed on this semiconductor-based end;
This first metal gasket unit is arranged in this first pattern dielectric layer, and wherein the peripheral shape of this first metal gasket unit is that polygon and each interior angle are greater than 90 °;
This second pattern dielectric layer is formed on this first pattern dielectric layer and this first metal gasket unit, and this second pattern dielectric layer that is positioned at above this first metal gasket unit has several interlayer holes;
Several metal plugs are arranged in this interlayer hole, and they are to electrically connect this first metal gasket unit;
The 3rd pattern dielectric layer is formed on this second pattern dielectric layer;
This second metal gasket unit is arranged in the 3rd pattern dielectric layer and is positioned on these metal plugs, and this metal plug and this first metal gasket unit are with electric connection; And
This protective layer, around periphery top, the second metal gasket unit, it protects this second metal gasket unit, and forms an opening on this second metal gasket cell surface.
15. the structure of the suprabasil metal gasket of semiconductor according to claim 14 is characterized in that, this first pattern dielectric layer is a low dielectric material layer.
16. the structure of the suprabasil metal gasket of semiconductor according to claim 14 is characterized in that, this first metal gasket unit is a bronze medal metal gasket.
17. the structure of the suprabasil metal gasket of semiconductor according to claim 14 is characterized in that, this second pattern dielectric layer is an oxide layer.
18. the structure of the suprabasil metal gasket of semiconductor according to claim 14 is characterized in that, these metal plugs are copper metal plugs.
19. the structure of the suprabasil metal gasket of semiconductor according to claim 14 is characterized in that, the 3rd pattern dielectric layer is an oxide layer.
20. the structure of the suprabasil metal gasket of semiconductor according to claim 14 is characterized in that, this second metal gasket unit is a bronze medal metal gasket.
21. the structure of the suprabasil metal gasket of semiconductor according to claim 14 is characterized in that, this polygon is a kind of of a pentagon, hexagon, octagon and circle.
22. the structure of the suprabasil metal gasket of semiconductor according to claim 14 is characterized in that, the peripheral shape of this second metal gasket unit is that polygon and each interior angle are greater than 90 °.
23. the structure of the suprabasil metal gasket of semiconductor according to claim 14 is characterized in that, this protective layer is a kind of of silicon nitride and silica.
24. the structure of the suprabasil metal gasket of semiconductor according to claim 22 is characterized in that, this polygon is a kind of of a pentagon, hexagon, octagon and circle.
25. the structure of the suprabasil metal gasket of semiconductor according to claim 22 is characterized in that, the identical and size of the peripheral shape of this opening of this protective layer is less than the peripheral shape of this second metal gasket unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021050155A CN1212663C (en) | 2002-02-10 | 2002-02-10 | Metal washer structure on semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021050155A CN1212663C (en) | 2002-02-10 | 2002-02-10 | Metal washer structure on semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1438702A true CN1438702A (en) | 2003-08-27 |
| CN1212663C CN1212663C (en) | 2005-07-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021050155A Expired - Lifetime CN1212663C (en) | 2002-02-10 | 2002-02-10 | Metal washer structure on semiconductor substrate |
Country Status (1)
| Country | Link |
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| CN (1) | CN1212663C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100405593C (en) * | 2005-04-18 | 2008-07-23 | 联发科技股份有限公司 | Bond pad structures and semiconductor devices using the same |
| CN100416809C (en) * | 2005-02-15 | 2008-09-03 | 台湾积体电路制造股份有限公司 | Bond pad structure for integrated circuit chip |
| CN103219254A (en) * | 2013-03-14 | 2013-07-24 | 上海华力微电子有限公司 | Method for forming metal pad |
| CN104425414A (en) * | 2013-09-09 | 2015-03-18 | 矽品精密工业股份有限公司 | Semiconductor device and method for fabricating the same |
| CN109148389A (en) * | 2018-07-11 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Device and the process cracked is prevented when temperature cycling test |
-
2002
- 2002-02-10 CN CNB021050155A patent/CN1212663C/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416809C (en) * | 2005-02-15 | 2008-09-03 | 台湾积体电路制造股份有限公司 | Bond pad structure for integrated circuit chip |
| CN100405593C (en) * | 2005-04-18 | 2008-07-23 | 联发科技股份有限公司 | Bond pad structures and semiconductor devices using the same |
| CN103219254A (en) * | 2013-03-14 | 2013-07-24 | 上海华力微电子有限公司 | Method for forming metal pad |
| CN103219254B (en) * | 2013-03-14 | 2015-09-30 | 上海华力微电子有限公司 | Form the method for metal gasket |
| CN104425414A (en) * | 2013-09-09 | 2015-03-18 | 矽品精密工业股份有限公司 | Semiconductor device and method for fabricating the same |
| CN109148389A (en) * | 2018-07-11 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Device and the process cracked is prevented when temperature cycling test |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1212663C (en) | 2005-07-27 |
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Granted publication date: 20050727 |
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