CN1295785C - Gasket area arrangement - Google Patents
Gasket area arrangement Download PDFInfo
- Publication number
- CN1295785C CN1295785C CNB021537399A CN02153739A CN1295785C CN 1295785 C CN1295785 C CN 1295785C CN B021537399 A CNB021537399 A CN B021537399A CN 02153739 A CN02153739 A CN 02153739A CN 1295785 C CN1295785 C CN 1295785C
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- metal
- layer
- pattern dielectric
- pad area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The present invention provides a structure of a jointing pad region, which can achieve the purpose of effectively preventing a jointing pad from peeling in a structure of an integrated circuit. The structure of a jointing pad region is suitable for a semiconductor substrate, and is used for throwing and manufacturing wire bonds on the surface of the jointing pad. The present invention is characterized in that the structure of a jointing pad region comprises a patterned dielectric layer which is formed on the surface of the semiconductor substrate, a top metal layer which is provided with a plurality of openings, and the jointing pad which is arranged in the patterned dielectric layer, wherein the top metal layer is arranged in the patterned dielectric layer, and the interior of the openings is filled with the dielectric layer; the jointing pad is overlapped with the top metal layer, and the surface of the jointing pad is exposed to the outside of the patterned dielectric layer.
Description
Technical field
The invention relates to a kind of semiconductor integrated circuit (semiconductor Integratedcircuits; ICs) structure, a kind of joint sheet (bonding pad) that can prevent is peeled off the junction pad area structure of (peeling).
Background technology
After the integrated circuit manufacturing is finished, the metal layer at top that is formed at the surface is through being defined as a plurality of joint sheets (bonding pad), and respectively be formed at after underlying metal pad (metal pad) become to electrically connect, be connected in metal wire between the corresponding lead foot of joint sheet and saddle in other words through wire bonder (bonder), joint sheet is as the interface between internal circuit and outer signal lead foot, and outer signal is nothing more than being exactly power supply signal, ground signalling or input/output signal or the like.
Below cooperate Fig. 1, Fig. 2 that known metal gasket structure is described.At first, please refer to Fig. 1, it shows the profile of known metal gasket structure.Wherein, label 108 is the semiconductor substrate, is formed with the several semiconductor element on it, is simplicity of illustration herein, only shows a smooth substrate.One first pattern dielectric layer 202 is formed in this substrate 108 with as metal intermetallic dielectric layer (lnter-metal dielectric; IMD), for example be low dielectric material layer, and one first metal gasket unit 201, external form is square or rectangle, is formed in the above-mentioned metal intermetallic dielectric layer 202, with the electric connection structure as connection semiconductor element intraconnections and outer lead.Afterwards, on the first pattern dielectric layer 202 and the first metal gasket unit 201, be formed with one second pattern dielectric layer 204, and the dielectric layer 204 that is positioned at 201 tops, the first metal gasket unit is formed with interlayer hole (via hole) 204a, copper metal plug (Plug) 204b is arranged, in order to electrically connect the first metal gasket unit 201 in the interlayer hole 204a.Then, be formed with one the 3rd pattern dielectric layer 206 and the second metal gasket unit 205 on the second pattern dielectric layer 204.These metal gasket unit 205 external forms are similarly square or rectangle, are to do to electrically connect also as the joint sheet (bonding pad) that is connected external circuit with the semiconductor element in the substrate 108 in order to see through the connector 204b and the first metal gasket unit 201.At last, above the second metal gasket unit, 205 peripheries, be formed with a passive state (passivation) protective layer 208, in follow-up encapsulation (Package) processing procedure, do not suffer damage with protection connection pad 205.Above-mentioned protective layer 208 has an opening 208a and exposes above-mentioned metal level 205 surfaces with the metal wire engaging portion as follow-up wire bonder.
Yet, please refer to Fig. 2, it shows according to the first pattern dielectric layer 202 of the 1st figure and the top view of the first metal gasket unit 201.As mentioned above, because the first pattern dielectric layer, 202 mechanical strengths are weak and tack (bondability) is not good, therefore at cmp (chemical mechanicalpolishing; CMP) under the effect of stress, in the corner of the first metal gasket unit 201 stress taking place and concentrate and dielectric layer 202 generation be full of cracks, has a strong impact on the electrical characteristics of element and the quality of product easily.Moreover, after the double action of mechanical stress that the process wire bonder applies and ultrasonic waves vibration, the phenomenon that first dielectric layer 202 can be full of cracks take place and peel off, as shown in Figure 2.More seriously, entire top metal level 205 and metal level 201 can be started by the metal wire of wire bonder and break away from (peeling) dielectric layer (not illustrating) and formation pitfall (crater), cause semiconductor device to lose efficacy.
United States Patent (USP) the 6th in Christian era bulletin in 23 days October calendar year 2001,306,749B1 number and 6 days November calendar year 2001 of the Christian era bulletin the special tooth the 6th of the U.S., 313, people such as Lin all discloses a kind of structure that prevents that junction pad area from peeling off in 541B1 number, main all be utilize increase joint sheet with on every side connect area to increase its adhesive force, yet, under the trend of thereupon dwindling along with the increase and the semiconductor element of semiconductor integrated level, these complicated structures face great difficulty in the making that size is dwindled.
Summary of the invention
In view of this, in order to address the above problem, main purpose of the present invention is to provide a kind of structure of junction pad area, not only can increase the release of external stress, also can guarantee the tackness of junction pad area, reaches the purpose that prevents the peeling off of joint sheet, pitfall.
The invention provides a kind of structure of junction pad area, be applicable in the semiconductor substrate, make pin (wire bond) in described gasket surface in order to routing, comprising:
One pattern dielectric layer is formed at described semiconductor-based basal surface;
One metal layer at top has a plurality of openings, and is arranged in the described pattern dielectric layer, makes to be full of described pattern dielectric layer in the described opening; And
One joint sheet, be arranged in the described pattern dielectric layer and with described top metal ply, its surface is exposed to outside the described pattern dielectric layer.
The structure of described junction pad area, wherein said opening be shaped as rectangle, triangle, irregularly shaped, arbitrary graphic pattern or literal arbitrarily.
The structure of described junction pad area, wherein said opening are arranged at four corners of described metal layer at top substantially.
The structure of described junction pad area wherein also comprises: a protective layer, be arranged at described joint sheet around the top the patterned dielectric laminar surface, only expose described metal gasket surface, as engaging portion.
The structure of described junction pad area wherein also comprises: a plurality of metal levels, be arranged at the metal layer at top below in the described pattern dielectric layer respectively, and wherein link to each other with a plurality of metal plugs between each metal level.
The structure of described junction pad area, wherein by top view, whole described opening is contained in described metal layer at top inside.
The structure of described junction pad area, wherein by top view, described opening is connected with described metal layer at top outside.
The structure of described junction pad area is full of described pattern dielectric layer in the wherein said opening, by top view, the described opening of part is connected with described metal layer at top outside, and the whole described metal layer at top inside that is contained in of the described opening of part.
According to the present invention, utilization is designed openings in metal layer at top, in order to discharge external stress, and open interior is full of pattern dielectric layer, can make whole junction pad area that the adhesive force (adhesion) of pattern dielectric layer is increased, strengthen the interlocking ability (interlock capability) of whole junction pad area structure, avoid carrying out routing when engaging, mechanical stress that wire bonder applies and ultrasonic waves vibration and cause that metal gasket is peeled off, the problem of pitfall takes place.
Description of drawings
Fig. 1 is the profile of known metal gasket structure;
Fig. 2 is the vertical view of known metal gasket structure;
Fig. 3 is the section of structure of the junction pad area of a preferred embodiment of the present invention;
Fig. 4 A-4F is the vertical view of the metal layer at top of a preferred embodiment of the present invention;
Fig. 5 A-5E is the vertical view of the metal layer at top of another preferred embodiment of the present invention;
Fig. 6 A-6C is the vertical view of the metal layer at top of another preferred embodiment of the present invention.
Symbol description
100, the semiconductor-based end of 108--;
111,202--first pattern dielectric layer;
112,204--first pattern dielectric layer;
113,206--the 3rd pattern dielectric layer;
114--the 4th pattern dielectric layer;
115--the 5th pattern dielectric layer;
120,208--protective layer;
The 131--the first metal layer;
132--second metal level;
133--the 3rd metal level;
134--the 4th metal level;
The 140--metal layer at top;
The 150--joint sheet:
The I--coupling opening;
The 201--first metal gasket unit;
The 204a--interlayer hole;
The 204b--metal plug;
The 205--second metal gasket unit;
The 208--protective layer;
The 208a--opening
Embodiment
Below utilize the top view of the metal layer at top of the section of structure of junction pad area of Fig. 3 and Fig. 4, Fig. 5 and Fig. 6, illustrate according to a preferred embodiment of the present invention.
At first, please the structure of junction pad area of the present invention be described earlier with reference to Fig. 3.This structure mainly comprises: be formed at surface, the semiconductor-based ends 100 a pattern dielectric layer 115, have a metal layer at top 140 of a plurality of openings and be arranged in the pattern dielectric layer 115 and a joint sheet 150 overlapping with metal layer at top 140.
Show semiconductor substrate 100 among the figure, surface, the semiconductor-based ends 100 may have any required semiconductor element, and for example: electric crystal, diode and any known semiconductor element for for the purpose of asking simplicity of illustration, do not illustrate among the figure herein.
And, a plurality of pattern dielectric layer, for example: one first pattern dielectric layer 111, one second pattern dielectric layer 112, one the 3rd pattern dielectric layer 113, one the 4th pattern dielectric layer 114 and one the 5th pattern dielectric layer 115 are stacked in regular turn at semiconductor-based the end 100.The material of each pattern dielectric layer 111-115 for example is silica (SiO
2), phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG) or other advanced low-k materials, as fluorine silex glass (FSG).
In addition, a plurality of metal levels, for example: the first metal layer 131, second metal level 132, the 3rd metal level 133 and the 4th metal level 134 are arranged at first to fourth pattern dielectric layer 131-134 inside respectively.Illustrate four layers of metal level 131-134 among the figure, yet in fact the number of plies of metal level can cooperate circuit design and adjust, and can decide on demand, is not changed limit at this.As for the number of plies of pattern dielectric layer then must the complexed metal layer number, each metal level is connect is arranged at each pattern dielectric layer inside.
In addition, metal layer at top 140 is to hold in the palm the metal level of top layer, is arranged at top layer (the 5th) pattern dielectric layer 115 inside.Feature of the present invention is that metal layer at top 140 has a plurality of openings, and open interior must be full of pattern dielectric layer 115.Because external stress concentrates on the corner easily, so those openings are arranged at four corners of metal layer at top 140 substantially, can effectively eliminate and discharge external stress, and open interior is full of pattern dielectric layer 115, can make whole junction pad area that the adhesive force of pattern dielectric layer is increased, thus, can prevent effectively that just junction pad area from causing peeling off because of being subjected to routing joint initiation stress.Opening by also observing metal layer at top 140 inside in the profile will describe the opening of metal layer at top 140 inside with top view in detail in the follow-up literary composition.
Each layer metal level 131 to 134 can comprise copper (Cu), aluminium (Al) or albronze (Cu/Al alloy) with the material of metal layer at top 140.And, between each metal level 131 to 134 and the metal layer at top 140 a plurality of metal plugs 10 are set all, with as electric connection.The material of metal plug 10 for example is a tungsten (W).
In addition, joint sheet (bonding pad) 150 is overlapped in the surface of metal layer at top, is arranged at pattern dielectric layer 115 inside equally, and its surface exposes to the outside, makes pin in order to follow-up by routing, in order to electrically connect with the outside.The material of joint sheet 150 for example is a metallic aluminium (Al).
At last, a protective layer 120, be arranged at joint sheet 150 around the top pattern dielectric layer 115 surfaces.And protective layer 120 has a coupling opening I, in order to expose joint sheet 150 surfaces, carries out routing to make things convenient for joint sheet 150.
Each layer metal level 131 to 134, metal layer at top 140 are generally rectangle with the shape of joint sheet 150, also can be made into other shapes according to demand, are not limited at this.
The invention is characterized in the opening 200 of metal layer at top 150, see also Fig. 4 A to Fig. 4 F, opening 200a can wholely be contained in metal layer at top 150 inside, in addition, see also Fig. 5 A to Fig. 5 E, opening 200b also can be connected with metal layer at top 150 outsides, or there be (shown in Fig. 6 A to Fig. 6 C) all simultaneously in opening 200a, the 200b of both kenels.The shape of opening 200a, 200b can comprise: arc, straight line, band shape, saw chi shape, diamond, rectangle, polygon (can be by limit, three limits to eight, or even more polygon, for example: rectangle, triangle, pentagon, hexagon, octangle ... etc.), irregularly shaped, arbitrary graphic pattern or literal (for example: C, E, H, I, J, K, L, M, N, O, U, V, W, X... etc.) arbitrarily, do not limited at this, and be arranged at four corners of metal layer at top 150 substantially.
According to the present invention, utilization is designed openings in metal layer at top, in order to discharge external stress, and open interior is full of pattern dielectric layer, can make whole junction pad area that the adhesive force (adhesion) of pattern dielectric layer is increased, strengthen the interlocking ability (interlock capability) of whole junction pad area structure, avoid carrying out routing when engaging, mechanical stress that wire bonder applies and ultrasonic waves vibration and cause that metal gasket is peeled off, the problem of pitfall takes place.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (7)
1, a kind of structure of junction pad area is applicable in the semiconductor substrate, makes pin in gasket surface in order to routing, it is characterized in that comprising:
One pattern dielectric layer is formed at described semiconductor-based basal surface;
One metal layer at top has a plurality of openings, and is arranged in the described pattern dielectric layer, makes to be full of described pattern dielectric layer in the described opening, and wherein said opening is arranged at one of four corners of described metal layer at top at least substantially; And
One joint sheet, be arranged in the described pattern dielectric layer and with described top metal ply, its surface is exposed to outside the described pattern dielectric layer.
2, the structure of junction pad area as claimed in claim 1, what it is characterized in that described opening is shaped as rectangle, triangle, irregularly shaped, arbitrary graphic pattern or literal arbitrarily.
3, the structure of junction pad area as claimed in claim 1 is characterized in that also comprising: a protective layer, be arranged at described joint sheet around the patterned dielectric laminar surface of top, only expose described metal gasket surface, with as engaging portion.
4, the structure of junction pad area as claimed in claim 1 is characterized in that also comprising: a plurality of metal levels, be arranged at the metal layer at top below in the described pattern dielectric layer respectively, and wherein link to each other with a plurality of metal plugs between each metal level.
5, the structure of junction pad area as claimed in claim 1 is characterized in that by top view, and whole described opening is contained in described metal layer at top inside.
6, the structure of junction pad area as claimed in claim 1 is characterized in that by top view, and described opening is connected with described metal layer at top outside.
7, the structure of junction pad area as claimed in claim 1, it is characterized in that being full of in the described opening described pattern dielectric layer, by top view, the described opening of part is connected with described metal layer at top outside, and the whole described metal layer at top inside that is contained in of the described opening of part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021537399A CN1295785C (en) | 2002-12-03 | 2002-12-03 | Gasket area arrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021537399A CN1295785C (en) | 2002-12-03 | 2002-12-03 | Gasket area arrangement |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1505140A CN1505140A (en) | 2004-06-16 |
| CN1295785C true CN1295785C (en) | 2007-01-17 |
Family
ID=34235275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021537399A Expired - Lifetime CN1295785C (en) | 2002-12-03 | 2002-12-03 | Gasket area arrangement |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1295785C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7679180B2 (en) * | 2006-11-07 | 2010-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bond pad design to minimize dielectric cracking |
| US8258629B2 (en) | 2008-04-02 | 2012-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Curing low-k dielectrics for improving mechanical strength |
| US9627337B2 (en) | 2011-03-31 | 2017-04-18 | Novatek Microelectronics Corp. | Integrated circuit device |
| CN104576580B (en) * | 2011-04-12 | 2017-10-03 | 联咏科技股份有限公司 | IC apparatus |
| CN103579166A (en) * | 2012-07-26 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Pad structure |
| CN103219254B (en) * | 2013-03-14 | 2015-09-30 | 上海华力微电子有限公司 | Form the method for metal gasket |
| CN104576582B (en) * | 2013-10-15 | 2017-09-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of bond pad structure |
| US10038025B2 (en) * | 2015-12-29 | 2018-07-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via support structure under pad areas for BSI bondability improvement |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6277672B1 (en) * | 1999-09-03 | 2001-08-21 | Thin Film Module, Inc. | BGA package for high density cavity-up wire bond device connections using a metal panel, thin film and build up multilayer technology |
| US6440833B1 (en) * | 2000-07-19 | 2002-08-27 | Taiwan Semiconductor Manufacturing Company | Method of protecting a copper pad structure during a fuse opening procedure |
-
2002
- 2002-12-03 CN CNB021537399A patent/CN1295785C/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6277672B1 (en) * | 1999-09-03 | 2001-08-21 | Thin Film Module, Inc. | BGA package for high density cavity-up wire bond device connections using a metal panel, thin film and build up multilayer technology |
| US6440833B1 (en) * | 2000-07-19 | 2002-08-27 | Taiwan Semiconductor Manufacturing Company | Method of protecting a copper pad structure during a fuse opening procedure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1505140A (en) | 2004-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100329407B1 (en) | Electrode structure of semiconductor element | |
| CN1097313C (en) | Lead frame and manufacturing method thereof | |
| KR100580970B1 (en) | Semiconducotor device | |
| CN1770437A (en) | Bond pad structure | |
| US7759797B2 (en) | Bonding pad structure to minimize IMD cracking | |
| CN1848417A (en) | Top via pattern for bond pad structure and making method thereof | |
| CN1095197C (en) | Semiconductor wafer, semiconductor device and manufacturing method of semiconductor device | |
| CN1722429A (en) | Semiconductor device | |
| CN1260591A (en) | Semiconductor package and mfg. method thereof | |
| CN1295785C (en) | Gasket area arrangement | |
| CN1319890A (en) | Semiconductor device and semiconductor assembly using same | |
| US20080003820A1 (en) | Bonding pad structure and method for making the same | |
| CN1992246A (en) | Composite projection | |
| CN1206729C (en) | Semiconductor device and its making process, circuit board and electronic instrument | |
| CN2696127Y (en) | Structure of joint pad | |
| CN1253939C (en) | Jointing washer structure on semiconductor substrate | |
| CN1835231A (en) | Semiconductor device and manufacturing method therefor | |
| CN1367533A (en) | Semiconductor device with reliable connecting chip | |
| CN1692481A (en) | Semiconductor device | |
| CN1226787C (en) | Metal pad and junction pad area structure | |
| CN1265452C (en) | Metal welding pad of integrated circuit and method for making the same | |
| CN1819188A (en) | Semiconductor device | |
| CN1630071A (en) | Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus | |
| CN1179411C (en) | Connecting pad with insulation intensifying structure and its making method | |
| CN1225790C (en) | Connecting pad structure and mfg. method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070117 |
|
| CX01 | Expiry of patent term |