CN1438574A - Instruction collection of 16-bit micro-processor - Google Patents
Instruction collection of 16-bit micro-processor Download PDFInfo
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Abstract
The instruction set uses RISC system architecture with each instruction being as single word length and single cycle. The instruction set containing 37 instructions is divided into 5 categories; the data transfers, the match and logic operations, the jump instructions, the immediate data operation and the processor control. The method for coding the instruction set combines three coding systems: the fixed length coding, the Hoffmann coding and the extended coding. The short codes are used for common instructions. The instructions belonging to categories: the data transfers, the jump instructions and the math and logic operations utilize four digits basic codes. The microprocessor contains 128 registers. The first 16 registers are general registers, and other registers can communicate with the general registers.
Description
One, affiliated technical field
The invention belongs to field of computer technology, relate to a kind of microprocessor instruction set, particularly a kind of microprocessor of 16 bit instruction set.
Two, background technology
When microprocessor is used for industrial control computer, generally do not need very complicated instruction, but the function of instruction set must be complete, efficient is carried out in instruction must be very high.And there is following defective in present microprocessor when being applied to Industry Control:
(1) common central processing unit (CPU) is in order to realize unitized purpose, and instruction set is huger, and instruction type is various, carries out an instruction and need get and refer to one to twice, even three times, has had a strong impact on the treatment effeciency of computing machine.
(2) repertoire of computer that has is too simple, command function too a little less than, can not realize due function.Sometimes in order to realize a set function, must use a large amount of program codes to finish, thereby influence processing speed, and take a large amount of storage spaces.
(3) one-chip computer of employing computer architecture, order set is simple in general, and the operation of each parts is serials, and instruction is carried out in a sequential manner, and the instruction throughput is low, and the whole system operation efficiency ratio is lower.
(4) because complex structure, so also relative complex of implementation structure, be unfavorable for the system integration.
In the modern industry control that requires constantly speed-raising, when particularly adopting SOC (system on a chip) (SOC) technology to carry out system integration design, the aforementioned calculation machine seems unable to do what one wishes, be badly in need of a kind of simply, the microprocessor towards Industry Control replaces efficiently, the LS-IPU16 microprocessor arises at the historic moment.
The coded system that the coding of computer system instruction at present uses has three kinds: fixed length coding, Huffman encoding and extended coding.They all respectively have shortcoming:
(1) the fixed length coded system is that the length of operational code is fixed, and concentrates and be placed in the field of instruction word.The length of instruction operation code has determined to finish in the order set instruction number of different operating.If the operation code length N position of certain machine, then it can have 2 at most
NThe bar instruction.The fixed length coded system is to simplifying hardware design, and it is highly beneficial to reduce instruction decode time, but this order format is unfavorable for the expansion of order set.
(2) Huffman encoding order format has reduced the average length of instruction operation code effectively, has shortened the storage space of program, but this order format has the operation code-point of waste.
(3) a sign indicating number form is a kind of variable format, i.e. the variable-length of operational code, and be dispersed in the different field of instruction.Its main thought is with certain or some code-point of class instruction expansion code-point as other instruction class.Extended coding order format helps the design of order format and the expansion of order set, but order format length irregularity.
Three, summary of the invention
Defective or deficiency according to above-mentioned prior art exists the objective of the invention is to, and a kind of microprocessor of 16 bit instruction set is provided.
Realize that technical scheme of the present invention is, the instruction set of LS-IPU16 microprocessor is characterized in, this instruction set adopts the RISC architecture, and every instruction is single-length, monocycle; Comprise data transmission, mathematical logic computing, shift control, count 5 classes totally 37 instructions such as operation and processor control immediately, constituted the instruction set of a complete risc processor.
Microprocessor instruction set of the present invention is compared with prior art, and its advantage is:
(1) instruction length of this microprocessor instruction set is fixed, and it is long to be single-word instruction, and promptly 16, every instruction only needs to program memory access once.
(2) owing to this processor adopting pipelining, except shifting the class instruction, all the other instructions are all finished in an instruction cycle.
(3) this microprocessor instruction set kind is few, comprises 37 instructions of five classes.But it can include all command functions that resemble 8031 processor instruction sets.
(4) instruction of microprocessor instruction set can comprise more than one function.For example: the instruction of computing class has also attached shift function except carrying out computing; The jump class instruction has also attached and whether has returned function except carrying out redirect.Such instruction cycle just can be finished two functions, adds flowing water mechanism, just is equal to the execution function of the four instructions of class 8031 order set for the such instruction that realizes function of the same race.
(5) this microprocessor instruction set has only peek and number storage order reference-to storage, and the operation of all the other instructions is all carried out between register.Thereby improved the execution efficient of processor.
(6) addressing mode is few.This instruction set has only used four kinds to seek how: count addressing, directly address, indirect addressing, relative addressing immediately.
Four, embodiment
When carrying out the design of microprocessor, at first to solve the design of the definite and order number of order set.The applicant adopts the present invention to finish the instruction set of LS-IPU16 microprocessor, and its instruction set is considered its versatility, high speed, high efficiency, easy implementation, has adopted the RISC architecture, and every instruction is single-length, monocycle.By selecting the higher simple instruction of usage frequency and some of great use but uncomplicated instruction, the instruction set of LS-IPU16 microprocessor, comprise data transmission, mathematical logic computing, shift control, count 5 classes totally 37 instructions such as operation and processor control immediately, constituted the instruction set of a complete risc processor.
During LS-IPU16 microprocessor instruction set coding these three kinds of coded systems of fixed length coding, Huffman encoding and extended coding are combined, avoid their shortcoming, draw advantage.Adopt Huffman thought, instruction commonly used is represented with short code, as counting load immediately; The instruction that is of little use is represented to instruct as miscellany with long code.Data are transmitted class, shift class instruction, arithmetical logic class type, and with four basic code codings, and all the other fields of instruction can be used for operand address or expand all instructions that this class is instructed.
The LS-IPU16 microprocessor comprises 128 registers, in order to effectively utilize instruction word length, stipulate that preceding 16 registers are general-purpose register (address is 0～15), can be used as the operand of arithmetic logical operation, also can be used as address register or carry out the data transmission with storer; The address is that 16～127 register then can only carry out data with 16 general-purpose registers and transmits.
The order format of LS-IPU16 microprocessor and encode as follows, wherein:
R: the register number that seven bits are represented
Rb: the register number that tetrad is represented as indirect addressing
Rd: the destination operand register number that tetrad is represented
Rs: source general-purpose register that tetrad is represented or special register A, count loads immediately
1. number → internal register immediately
Instruction mnemonic: LDM Rd, #imm10
Order format: 01, Rd, #imm10
Function: 10 number is immediately sent into internal register; B, data transmit the class instruction
1. internal register register
Instruction mnemonic: LD Rd, R and ST Rd, R
Order format: 00, Rd, 00, D, R (D is 1 expression ST, is 0 expression LD)
Function: LD delivers to internal register Rd with the content of register R;
ST delivers to register R with the content of internal register Rd;
2. internal register storer
Instruction mnemonic: LD Rd ， @Rb and ST Rd ， @Rb
Order format: 00, Rd, 01, D, 000, Rb
D is 1 expression ST, is 0 expression LD
Function: LD is sent to internal register Rd with the content of the storer of Rb indication;
ST is sent to the content of internal register Rd the memory cell of Rb indication;
3. stack manipulation: comprise pop down and pull instruction
Instruction mnemonic: PUSH Rd and POP Rd
Order format: 00, Rd, 11, D, 000,0001 (D is 1 expression PUSH, is 0 expression POP)
Function: PUSH is pressed into stack top with the content of internal register Rd;
POP is bound to internal register Rd with the stack top content; C, the instruction of arithmetic logical operation class
In order to reduce instruction type, shifting function is additional to after the arithmetic logical operation;
1. add " 1 " instruction
Instruction mnemonic: INC Rs (, shiftcode)
Function: specify register Rs content to add 1, by delivering to this register after the specific mode displacement;
2. subtract " 1 " instruction
Instruction mnemonic: DEC Rs (, shiftcode)
Function: specify register Rs content to subtract 1, by delivering to this register after the specific mode displacement;
3. addition or bring into the position addition
Instruction mnemonic: ADD Rs (, shiftcode)
Function: totalizer ACC content adds specifies register Rs content, by delivering to accumulator registers after the specific mode displacement;
Instruction mnemonic: ADDC Rs (, shiftcode)
Function: totalizer ACC content adds specifies register Rs content again behind the add carry, again by delivering to totalizer ACC after the specific mode displacement;
4. subtraction or bring into the position subtraction
Instruction mnemonic: SUB Rs (, shiftcode)
Function: totalizer ACC content subtracts specifies register Rs content, by delivering to totalizer ACC after the specific mode displacement;
Instruction mnemonic: SUBC Rs (, shiftcode)
Function: totalizer ACC content subtracts specifies register Rs content again behind the subtract carry, again by delivering to totalizer ACC after the specific mode displacement;
5. logical and accords with: AND Rs (, shiftcode)
Function: after totalizer ACC content logic and the appointment register Rs content, again by delivering to totalizer ACC after the specific mode displacement;
6. logical OR
Instruction mnemonic: OR Rs (, shiftcode)
Function: after totalizer ACC content logic or the appointment register Rs content, again by delivering to totalizer ACC after the specific mode displacement;
7. logic XOR
Instruction mnemonic: XOR Rs (, shiftcode)
Function: after totalizer ACC content logic XOR is specified register Rs content, again by delivering to totalizer ACC after the specific mode displacement;
8. Boolean complementation
Instruction mnemonic: NOT Rs (, shiftcode)
Function: after will specifying the every negate of register Rs content, again by delivering to accumulator registers after the specific mode displacement.
9. displacement
Instruction mnemonic: SHT Rs (, shiftcode)
Function: will specify register Rs content to press the specific mode displacement;
10. byte exchange
Instruction mnemonic: SWAP Rs
Function: with the high low byte exchange of internal register Rs.
Arithmetic logical operation order format: 11, Rs, 00, LAOP, ShiftMode
Format description: LAOP is arithmetic or the logical operation type code that tetrad is represented:
0000：INC 0010：DEC 1000：ADD 1001：ADDC
1010：SUB 1011：SUBC 1101：AND 1110：OR
1100:XOR 01 10:NOT 0100:SHT or SWAP
ShiftMode accounts for four, has stipulated the displacement mode when instruction is carried out:
0101: one of logical shift left, low level mends 0, and D15 send BF
0100: one of logical shift right, high-order benefit 0, D0 send BF
0011: one of ring shift left does not comprise BF
0010: one of ring shift right does not comprise BF
0111: one of ring shift left, comprise BF, D15 send BF
0110: one of ring shift right, comprise BF, D0 send BF
1000: high low byte exchange does not influence BF
1111 and other: the D that is not shifted, shift the class instruction
Relative address short branch, register shift, three kinds of instructions of the long transfer of first level address:
1. unconditional transfer
Instruction mnemonic: JMP[S] #imm13
Order format: 10, S, #imm13
S: the return address storaging mark is 1 preservation return address, and 0 does not preserve
Function: program jump is to the storage address of appointment.This address is 13 several immediately behaviour in the instruction
Count.
2. register shifts
Instruction mnemonic: JMP[S] Rs
Order format: 11, S000,10,0000, Rs (S is the same)
Function: program jump is to the storage address of content of registers indication.
3. conditional transfer
Instruction mnemonic:
JZ #imm8 or JZ label (if ZF is masked as true i.e. ' 1 ' transfer)
JNZ #imm8 or JNZ label (if ZF is masked as false i.e. ' 0 ' transfer)
JC #imm8 or JC label (if CF is masked as true i.e. ' 1 ' transfer)
JNC #imm8 or JNC label (if CF is masked as false i.e. ' 0 ' transfer)
JB #imm8 or JB label (if BF is masked as true i.e. ' 1 ' transfer)
JNB #imm8 or JNB label (if BF is masked as false i.e. ' 0 ' transfer)
JO #imm8 or JO label (if OF is masked as true i.e. ' 1 ' transfer)
JNO #imm8 or JNO label (if OF is masked as false i.e. ' 0 ' transfer)
Order format: 11, S000,10,0000, Rs (S is the same)
Function: when test condition was set up, program jump added the address of the storer of relative displacement to programmable counter;
Zero flag, carry flag, shift-out bit sign, overflow indicator are tested; E, miscellany
1. ON/OFF interrupt instruction
Instruction mnemonic: SETI and CLRI
Order format: 11,0000,11,0000,000S
S=1 represents that SETI opens interruption, is that 0 expression CLRI closes interruption
Command function: SETI is provided with interrupt enable flag for allowing; CLRI is provided with interrupt enable flag for forbidding;
2. remove the instruction of break in service sign
Instruction mnemonic: CLRIS
Order format: 11,0001,11,0000,0000
Function: remove and interrupt using service mark IS, this sign can only be by hardware set, and software is removed;
3. remove the instruction of storehouse overflow indicator
Instruction mnemonic: CLRSO
Order format: 11,0010,11,0000,0000
Function: remove storehouse sign SO, this sign can only be by hardware set, and software is removed;
4. stop instruction
Instruction mnemonic: HLT
Order format: 11,0011,11,0000,0001
Function: make the LS-IPU16 processor enter dormant state, freeze the work clock of LSIPU16 processor core;
5. soft interrupt instruction
Instruction mnemonic: INT #no
Order format: 11,1111,11,1111, #no
Function: change the #no interrupt service routine over to, and forbid subsequent interrupt by the break in service sign is set;
6. NOP instruction
Instruction mnemonic: NOP
Order format: 00,0000,00,0000,0000
Function: this instruction is a pseudo-operation instruction just, and this instructs unreal incumbent what operation, takies an instruction cycle.
7. link order
Instruction mnemonic: RET
Order format: 1101,0011,0000,0000
Function: eject from storehouse and return an address among the PC, that realizes interrupting returns.4. alternative:
(1) can increase the multiplication and division instruction.
(2) can increase or expand special instruction simply.
Claims (1)
1. the instruction set of a microprocessor of 16 bit is characterized in that, this instruction set adopts the RISC architecture, and every instruction is single-length, monocycle; System comprises data transmission, mathematical logic computing, shifts control, counts 5 classes totally 37 instructions such as operation and processor control immediately, has constituted the instruction set of a complete risc processor;
The order format of this microprocessor of 16 bit and encode as follows, wherein:
R: the register number that seven bits are represented
Rb: the register number that tetrad is represented as indirect addressing
Rd: the destination operand register number that tetrad is represented
Rs: source general-purpose register that tetrad is represented or special register A, count loads immediately
1. number → internal register immediately
Instruction mnemonic: LDM Rd, #imm10
Order format: 01, Rd, #imm10
Function: 10 number is immediately sent into internal register; B, data transmit the class instruction
1. internal register register
Instruction mnemonic: LD Rd, R and STRd, R
Order format: 00, Rd, 00, D, R (D is 1 expression ST, is 0 expression LD)
Function: LD delivers to internal register Rd with the content of register R;
ST delivers to register R with the content of internal register Rd;
2. internal register storer
Instruction mnemonic: LD Rd ， @Rb and ST Rd ， @Rb
Order format: 00, Rd, 01, D, 000, Rb
D is 1 expression ST, is 0 expression LD
Function: LD is sent to internal register Rd with the content of the storer of Rb indication;
ST is sent to the content of internal register Rd the memory cell of Rb indication;
3. stack manipulation: comprise pop down and pull instruction
Instruction mnemonic: PUSH Rd and POP Rd
Order format: 00, Rd, 11, D, 000,0001 (D is 1 expression PUSH, is 0 expression POP)
Function: PUSH is pressed into stack top with the content of internal register Rd;
POP is bound to internal register Rd with the stack top content; C, the instruction of arithmetic logical operation class
In order to reduce instruction type, shifting function is additional to after the arithmetic logical operation; 1. add " 1 " instruction
Instruction mnemonic: INC Rs (, shiftcode)
Function: specify register Rs content to add 1, by delivering to this register after the specific mode displacement; 2. subtract " 1 " instruction
Instruction mnemonic: DEC Rs (, shiftcode)
Function: specify register Rs content to subtract 1, by delivering to this register after the specific mode displacement; 3. addition or bring into the position addition
Instruction mnemonic: ADD Rs (, shiffcode)
Function: totalizer ACC content adds specifies register Rs content, by delivering to accumulator registers after the specific mode displacement;
Instruction mnemonic: ADDC Rs (, shiffcode)
Function: totalizer ACC content adds specifies register Rs content again behind the add carry, again by delivering to totalizer ACC after the specific mode displacement; 4. subtraction or bring into the position subtraction
Instruction mnemonic: SUB Rs (, shiffcode)
Function: totalizer ACC content subtracts specifies register Rs content, by delivering to totalizer ACC after the specific mode displacement;
Instruction mnemonic: SUBC Rs (, shiftcode)
Function: totalizer ACC content subtracts specifies register Rs content again behind the subtract carry, again by delivering to totalizer ACC after the specific mode displacement; 5. logical and accords with: AND Rs (, shiftcode)
Function: after totalizer ACC content logic and the appointment register Rs content, again by delivering to totalizer ACC after the specific mode displacement; 6. logical OR
Instruction mnemonic: OR Rs (, shiftcode)
Function: after totalizer ACC content logic or the appointment register Rs content, again by delivering to totalizer ACC after the specific mode displacement; 7. logic XOR
Instruction mnemonic: XOR Rs (, shiftcode)
Function: after totalizer ACC content logic XOR is specified register Rs content, again by delivering to totalizer ACC after the specific mode displacement; 8. Boolean complementation
Instruction mnemonic: NOT Rs (, shiftcode)
Function: after will specifying the every negate of register Rs content, again by delivering to accumulator registers after the specific mode displacement.9. displacement
Instruction mnemonic: SHT Rs (, shiftcode)
Function: will specify register Rs content to press the specific mode displacement; 10. byte exchange
Instruction mnemonic: SWAP Rs
Function: with the high low byte exchange of internal register Rs;
Arithmetic logical operation order format: 11, Rs, 00, LAOP, ShiftMode
Format description: LAOP is arithmetic or the logical operation type code that tetrad is represented:
0000：INC?0010：DEC 1000：ADD 1001：ADDC
1010：SUB?1011：SUBC?1101：AND 1110：OR
1100:XOR 0110:NOT 0100:SHT or SWAP
ShiftMode accounts for four, has stipulated the displacement mode when instruction is carried out:
0101: one of logical shift left, low level mends 0, and D15 send BF
0100: one of logical shift right, high-order benefit 0, D0 send BF
0011: one of ring shift left does not comprise BF
0010: one of ring shift right does not comprise BF
0111: one of ring shift left, comprise BF, D15 send BF
0110: one of ring shift right, comprise BF, D0 send BF
1000: high low byte exchange does not influence BF
1111 and other: the D that is not shifted, shift the class instruction
Relative address short branch, register shift, three kinds of instructions of the long transfer of first level address: 1. unconditional transfer
Instruction mnemonic: JMP[S] #imm13
Order format: 10, S, #imm13
S: the return address storaging mark is 1 preservation return address, and 0 does not preserve
Function: program jump is to the storage address of appointment.This address is 13 several immediately operands in the instruction.2. register shifts
Instruction mnemonic: JMP[S] Rs
Order format: 11, S000,10,0000, Rs (S is the same)
Function: program jump is to the storage address of content of registers indication.3. conditional transfer
Instruction mnemonic:
JZ #imm8 or JZ label (if ZF is masked as true i.e. ' 1 ' transfer)
JNZ #imm8 or JNZ label (if ZF is masked as false i.e. ' 0 ' transfer)
JC #imm8 or JC label (if CF is masked as true i.e. ' 1 ' transfer)
JNC #imm8 or JNC label (if CF is masked as false i.e. ' 0 ' transfer)
JB #imm8 or JB label (if BF is masked as true i.e. ' 1 ' transfer)
JNB #imm8 or JNB label (if BF is masked as false i.e. ' 0 ' transfer)
JO #imm8 or JO label (if OF is masked as true i.e. ' 1 ' transfer)
JNO #imm8 or JNO label (if OF is masked as false i.e. ' 0 ' transfer)
Order format: 11, S000,10,0000, Rs (S is the same)
Function: when test condition was set up, program jump added the address of the storer of relative displacement to programmable counter;
Zero flag, carry flag, shift-out bit sign, overflow indicator are tested; E, miscellany be the ON/OFF interrupt instruction 1.
Instruction mnemonic: SETI and CLRI
Order format: 11,0000,11,0000,000S
S=1 represents that SETI opens interruption, closes interruption for O represents CLRI
Command function: SETI is provided with interrupt enable flag for allowing; CLRI is provided with interrupt enable flag for forbidding; 2. remove the instruction of break in service sign
Instruction mnemonic: CLRIS
Order format: 11,0001,11,0000,0000
Function: remove and interrupt using service mark IS, this sign can only be by hardware set, and software is removed; 3. remove the instruction of storehouse overflow indicator
Instruction mnemonic: CLRSO
Order format: 11,0010,11,0000,0000
Function: remove storehouse sign SO, this sign can only be by hardware set, and software is removed; 4. stop instruction
Instruction mnemonic: HLT
Order format: 11,0011,11,0000,0001
Function: make the LS-IPU16 processor enter dormant state, freeze the work clock of LS IPU16 processor core; 5. soft interrupt instruction
Instruction mnemonic: INT #no
Order format: 11,1111,11,1111, #no
Function: change the #no interrupt service routine over to, and forbid subsequent interrupt by the break in service sign is set; 6. NOP instruction
Instruction mnemonic: NOP
Order format: 00,0000,00,0000,0000
Function: this instruction is a pseudo-operation instruction just, and this instructs unreal incumbent what operation, takies an instruction cycle; 7. link order
Instruction mnemonic: RET
Order format: 1101,0011,0000,0000
Function: eject from storehouse and return an address among the PC, that realizes interrupting returns.
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| CN 03114503 CN1438574A (en) | 2003-02-21 | 2003-02-21 | Instruction collection of 16-bit micro-processor |
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| CN 03114503 CN1438574A (en) | 2003-02-21 | 2003-02-21 | Instruction collection of 16-bit micro-processor |
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| CN102103486A (en) * | 2009-12-22 | 2011-06-22 | 英特尔公司 | Add instructions to add three source operands |
| CN102109976A (en) * | 2009-12-26 | 2011-06-29 | 英特尔公司 | Rotate instructions that complete execution without reading carry flag |
| CN101615173B (en) * | 2006-02-06 | 2011-11-30 | 威盛电子股份有限公司 | Stream processor for treating data in any of a plurality of different formats as well as method thereof and module |
| CN102411490A (en) * | 2011-08-09 | 2012-04-11 | 清华大学 | Instruction set optimization method for dynamically reconfigurable processors |
| CN101650645B (en) * | 2009-09-04 | 2013-01-09 | 浙江大学 | Device for expanding coprocessor command set |
| CN103970508A (en) * | 2014-06-04 | 2014-08-06 | 上海航天电子通讯设备研究所 | Simplified microprocessor IP core |
| WO2021093582A1 (en) * | 2019-11-11 | 2021-05-20 | 深圳市中兴微电子技术有限公司 | Risc-v vector extension instruction-based encoding processing method and device, and storage medium |
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| CN101615173B (en) * | 2006-02-06 | 2011-11-30 | 威盛电子股份有限公司 | Stream processor for treating data in any of a plurality of different formats as well as method thereof and module |
| CN101650645B (en) * | 2009-09-04 | 2013-01-09 | 浙江大学 | Device for expanding coprocessor command set |
| CN102103486B (en) * | 2009-12-22 | 2016-03-30 | 英特尔公司 | For the add instruction that three source operands are added |
| CN102103486A (en) * | 2009-12-22 | 2011-06-22 | 英特尔公司 | Add instructions to add three source operands |
| US9164762B2 (en) | 2009-12-26 | 2015-10-20 | Intel Corporation | Rotate instructions that complete execution without reading carry flag |
| US11106461B2 (en) | 2009-12-26 | 2021-08-31 | Intel Corporation | Rotate instructions that complete execution either without writing or reading flags |
| US11900108B2 (en) | 2009-12-26 | 2024-02-13 | Intel Corporation | Rotate instructions that complete execution either without writing or reading flags |
| CN102109976B (en) * | 2009-12-26 | 2015-04-22 | 英特尔公司 | Rotate instructions that complete execution without reading carry flag |
| US9940131B2 (en) | 2009-12-26 | 2018-04-10 | Intel Corporation | Rotate instructions that complete execution either without writing or reading flags |
| CN102109976A (en) * | 2009-12-26 | 2011-06-29 | 英特尔公司 | Rotate instructions that complete execution without reading carry flag |
| US9916160B2 (en) | 2009-12-26 | 2018-03-13 | Intel Corporation | Rotate instructions that complete execution either without writing or reading flags |
| US9940130B2 (en) | 2009-12-26 | 2018-04-10 | Intel Corporation | Rotate instructions that complete execution either without writing or reading flags |
| CN102411490A (en) * | 2011-08-09 | 2012-04-11 | 清华大学 | Instruction set optimization method for dynamically reconfigurable processors |
| CN102411490B (en) * | 2011-08-09 | 2014-04-16 | 清华大学 | Instruction set optimization method for dynamically reconfigurable processors |
| CN103970508A (en) * | 2014-06-04 | 2014-08-06 | 上海航天电子通讯设备研究所 | Simplified microprocessor IP core |
| WO2021093582A1 (en) * | 2019-11-11 | 2021-05-20 | 深圳市中兴微电子技术有限公司 | Risc-v vector extension instruction-based encoding processing method and device, and storage medium |
| CN113656071A (en) * | 2021-10-18 | 2021-11-16 | 深圳市智想科技有限公司 | RISC architecture based CPU instruction set system and CPU system |
| CN113656071B (en) * | 2021-10-18 | 2022-02-08 | 深圳市智想科技有限公司 | RISC architecture based CPU instruction set system and CPU system |
| WO2023065960A1 (en) * | 2021-10-18 | 2023-04-27 | 深圳市智想科技有限公司 | Cpu instruction set system and cpu system based on risc architecture |
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