CN113656071B - RISC architecture based CPU instruction set system and CPU system - Google Patents

RISC architecture based CPU instruction set system and CPU system Download PDF

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CN113656071B
CN113656071B CN202111208212.5A CN202111208212A CN113656071B CN 113656071 B CN113656071 B CN 113656071B CN 202111208212 A CN202111208212 A CN 202111208212A CN 113656071 B CN113656071 B CN 113656071B
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instruction
field
opcode
cpu
encoding format
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CN113656071A (en
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杨智华
周黄
赵文攀
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Shenzhen Zhixiang Technology Co ltd
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Shenzhen Zhixiang Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals

Abstract

The invention discloses a CPU instruction set system based on RISC architecture and a CPU system, relating to the technical field of computer system structures and processor microstructures. The CPU instruction set system is applied to a RISC architecture-based CPU system and comprises the following components: encoding a CPU instruction set; the CPU instruction set is coded into an instruction set coding format with the same length of 32 bits, supports 32 general function registers with the same length and comprises an operation code field with an indefinite length, a first register index field, a second register index field, a third register index field, an address offset field and an immediate digit field; the operation code field with different bit length is combined with the other fields, or the operation code field is combined into different instruction coding format types for executing at least one preset operation instruction. By the embodiment of the invention, the occurrence probability of the program scene needing to increase the instruction overhead due to insufficient address range of the jump instruction can be reduced, the programming difficulty can be effectively reduced, and the running performance of the processor can be improved.

Description

RISC architecture based CPU instruction set system and CPU system
Technical Field
The invention relates to the technical field of computer architecture and processor microstructure, in particular to a CPU instruction set system based on RISC architecture and a CPU system.
Background
In the current processor, two kinds of architectures are roughly classified according to the technical characteristics of the instruction set: complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC).
The instruction set system of the RISC architecture is relatively simple, only limited common and relatively simple instructions need to be realized, and other complex operations are completed by combining a plurality of instructions through a compiling technology. The instruction length of the instruction set of the RISC architecture is generally fixed and equal, and is usually 16 bits or 32 bits, for example, the basic instruction sets of the common RISC instruction sets PowerPC, MIPS, ARM and RISC-V are all 32 bits. The equal-length instructions are beneficial to the design of a hardware circuit, and can reduce the complexity of the circuit and improve the performance of the circuit. However, because of instruction encoding length limitations, the number of bits available in a single instruction to represent the address offset field is limited, thereby limiting the jump address range of jump-type instructions. Taking the RISC instruction set listed above as an example, the maximum instruction offset field using the program pointer PC as the base address is 26 bits, and 256 MB instruction space can be addressed; the maximum instruction offset field using the register as a base address is 16 bits, and can address 256 KB instruction space, so that the probability of occurrence of program scenes needing to increase instruction overhead due to insufficient address range of jump instructions is increased, the programming difficulty is increased, the program performance is reduced, and the running performance of a processor is reduced.
Disclosure of Invention
The embodiment of the invention aims to provide a CPU instruction set system based on a RISC architecture and a CPU system, which can reduce the occurrence probability of a program scene needing to increase instruction overhead due to insufficient address range of a jump instruction, thereby effectively reducing the programming difficulty, improving the program performance and improving the running performance of a CPU processor.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions: a CPU instruction set system based on RISC architecture, which is applied to the CPU system based on RISC architecture, the CPU instruction set system includes: encoding a CPU instruction set;
the CPU instruction set is encoded into an instruction set encoding format with the same length of 32 bits, 32-bit general function registers (G0-G31) are supported, and the instruction set comprises an operation code field Opcode with different lengths, a first register index field Ga, a second register index field Gb, a third register index field Gc, an address Offset field Offset and an immediate value field Imm; the instruction encoding method is characterized in that the instruction encoding method comprises operating code fields Opcode with different bit lengths and at least one of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset and the immediate field Imm, or comprises all operating code fields Opcode with different instruction encoding format types, and is used for executing at least one preset operating instruction as follows: the system comprises a jump instruction, a memory access instruction, a mathematical operation instruction, a logic operation instruction, a comparison instruction, a test instruction, a system call instruction, a shift instruction, a bit operation instruction, a condition test instruction, a system special operation instruction, a program return instruction and a miscellaneous instruction.
Optionally, the Opcode field Opcode is used to distinguish between instructions with different functions, and an independent binary code is provided for each instruction; the Opcode field Opcode is indefinite and unfixed in length, the length of the Opcode field Opcode depends on the remaining length of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset, and/or the immediate field Imm in the 32-bit long instruction set encoding format after the lengths of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset, and/or the immediate field Imm are added, and the Opcode field Opcode is 4 bits in shortest and 32 bits in longest.
Optionally, a starting position of the Opcode field Opcode in an instruction set encoding format with an equal length of 32 bits is located at a 0 th bit or a 31 th bit of the CPU instruction set encoding, and the specific starting position is: a number of bits in order from the 0 th bit of the CPU instruction set encoding or a number of bits in inverse order from the 31 th bit of the CPU instruction set encoding.
Optionally, the first register index field Ga is a fixed 5-bit length, and the first register index field Ga is used to specify that the CPU accesses one register of the 32 general-purpose function registers to obtain a first operand;
the second register index field Gb is a fixed 5-bit length, and the second register index field Gb is used to designate the CPU to access one register of the 32 general-purpose functional registers to obtain a second operand or to store an instruction operation result;
the third register index field Gc is of a fixed 5-bit length, and is used for designating a CPU to access one register of 32 general-purpose functional registers to obtain a third operand;
the address Offset field Offset is a fixed 16-bit or 18-bit or 28-bit length, the address Offset field Offset is used to provide an address Offset for a jump instruction or a memory access instruction to generate a target address;
the immediate field Imm is of a fixed 5-bit or 16-bit length and is used to directly provide operands for instruction operations.
Optionally, the CPU instruction set code at least includes 12 instruction coding format types, which are Type1 instruction coding format Type, Type2 instruction coding format Type, Type3 instruction coding format Type, Type4 instruction coding format Type, Type5 instruction coding format Type, Type6 instruction coding format Type, Type7 instruction coding format Type, Type8 instruction coding format Type, Type9 instruction coding format Type, Type10 instruction coding format Type, Type11 instruction coding format Type, Type12 instruction coding format Type, each instruction coding format Type is composed of operation code fields Opcode with different bit length and different field combinations im in the first register index field Ga, the second register index field Gb, the third index register field Gc, the address Offset field Offset and the immediate segment im, or all consist of combinations of Opcode fields Opcode to execute different preset operation instructions.
Optionally, the Type1 instruction encoding format Type includes an Opcode field Opcode with a length of 4 bits and an address Offset field Offset with a length of 28 bits;
the Type1 instruction encoding format Type is used for executing the following preset operation instructions: the jump instruction comprises an unconditional jump instruction with a program pointer PC as a base address and Offset as an Offset.
Optionally, the Type2 instruction encoding format Type includes an Opcode field Opcode with a length of 6 bits, a first register index field Ga, a second register index field Gb, and an address Offset field Offset with a length of 16 bits;
the Type2 instruction encoding format Type is used for executing at least one preset operation instruction as follows: the jump instruction comprises a memory access instruction with a register as a base address and Offset as an Offset and a conditional jump instruction with a program pointer PC as a base address and Offset as an Offset.
Optionally, the Type3 instruction encoding format Type includes an Opcode field Opcode with a length of 6 bits, a first register index field Ga, a second register index field Gb, and an immediate field Imm with a length of 16 bits;
the Type3 instruction encoding format Type is used for executing at least one preset operation instruction as follows: an arithmetic instruction using a register and an immediate as operands, and a comparison instruction using a register and an immediate as operands.
Optionally, the Type4 instruction encoding format Type includes an operation code field Opcode with a length of 9 bits, a first register index field Ga, and an address Offset field Offset with a length of 18 bits;
the Type4 instruction encoding format Type is used for executing the following preset operation instructions: the unconditional jump instruction comprises an unconditional jump instruction with a register as a base address and Offset as an Offset.
Optionally, the Type5 instruction encoding format Type includes an operation code field Opcode with a length of 11 bits, a first register index field Ga, and an immediate field Imm with a length of 16 bits;
the Type5 instruction encoding format Type is used for executing at least one preset operation instruction as follows: an arithmetic instruction with a register and an immediate as operands, and a conditional test instruction with a register and an immediate as operands.
Optionally, the Type6 instruction encoding format Type includes an operation code field Opcode with a length of 12 bits, a first register index field Ga, a second register index field Gb, and an immediate field Imm with a length of 10 bits;
the Type6 instruction encoding format Type is used for executing the following preset operation instructions: bit-operating instructions with registers and immediate as operands.
Optionally, the Type7 instruction encoding format Type comprises an Opcode field Opcode with a length of 16 bits and an immediate field Imm with a length of 16 bits;
the Type7 instruction encoding format Type is used for executing the following preset operation instructions: a system call instruction with an immediate as a single operand.
Optionally, the Type8 instruction encoding format Type includes an Opcode field Opcode with a length of 17 bits, a first register index field Ga, a second register index field Gb, and a third register index field Gc;
the Type8 instruction encoding format Type is used for executing at least one preset operation instruction as follows: an arithmetic instruction using 2 registers as operands, a memory access instruction using 1 register as a base address and 1 register as an offset, a conditional jump instruction using 2 registers as operands, a compare instruction using 2 registers as operands, a shift instruction using 2 registers as operands, and a conditional transfer instruction using 2 registers as operands.
Optionally, the Type9 instruction encoding format Type includes an Opcode field Opcode with a length of 17 bits, a first register index field Ga, a second register index field Gb, and an immediate field Imm with a length of 5 bits;
the Type9 instruction encoding format Type is used for executing the following preset operation instructions: shift instructions with registers and immediate as operands.
Optionally, the Type10 instruction encoding format Type includes an Opcode field Opcode with a length of 22 bits, a first register index field Ga and a second register index field Gb;
the Type10 instruction encoding format Type is used for executing at least one preset operation instruction as follows: the system comprises a bit operation instruction with 1 register as a single operand, a system special operation instruction with 1 register as a parameter, and a condition test instruction with 2 registers as operands.
Optionally, the Type11 instruction encoding format Type includes an Opcode field Opcode with a length of 27 bits and a first register index field Ga;
the Type11 instruction encoding format Type is used for executing the following preset operation instructions: system specific operation instruction using register as parameter.
Optionally, the Type12 instruction encoding format Type includes an Opcode field Opcode with a length of 32 bits;
the Type12 instruction encoding format Type is used for executing one of the following preset operation instructions: including program return instructions, miscellaneous instructions, and system-specific operating instructions.
In order to solve the above technical problems, embodiments of the present invention further provide the following technical solutions: a CPU system based on RISC architecture comprises a CPU based on RISC architecture and a CPU instruction set system based on RISC architecture of any embodiment of the invention, wherein the CPU is used for operating the CPU instruction set system based on RISC architecture.
Compared with the prior art, the CPU instruction set system based on the RISC architecture and the CPU system provided by the embodiment of the invention support 32-bit general function registers (G0-G31) by the fact that the CPU instruction set system based on the RISC architecture comprises a 32-bit CPU instruction set code with equal length, wherein the instruction set code format comprises an operation code field Opcode with indefinite length, a first register index field Ga, a second register index field Gb, a third register index field Gc, an address Offset field Offset and an immediate digital field Imm; the instruction encoding method is characterized in that the instruction encoding method comprises operating code fields Opcode with different bit lengths and at least one of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset and the immediate field Imm, or comprises all the operating code fields Opcode to form different instruction encoding format types, and the operating code fields Opcode are used for executing preset operating instructions. Therefore, a set of RISC instruction set with complete basic functions is provided, the offset address range of the jump instruction is enlarged on the basis of the RISC instruction set, the jump address range which is larger than that of other existing instruction sets is obtained under the condition of the same instruction coding with the word length of 32 bits, and the occurrence probability of program scenes needing to increase instruction overhead due to insufficient jump instruction address range can be reduced, so that the programming difficulty and the program performance can be effectively reduced, and the running performance of a CPU processor can be improved.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic diagram of the encoding format of a CPU instruction set system based on RISC architecture according to the present invention.
Fig. 2 is a schematic diagram of an encoding format of a Type1 instruction encoding format in a RISC-architecture-based CPU instruction set system according to the present invention.
Fig. 3 is a schematic diagram of an encoding format of a Type2 instruction encoding format in a RISC-architecture-based CPU instruction set system according to the present invention.
Fig. 4 is a schematic diagram of an encoding format of a Type3 instruction encoding format in a RISC-architecture-based CPU instruction set system according to the present invention.
FIG. 5 is a schematic diagram of the encoding format of Type4 instruction in the RISC-based CPU instruction set system according to the present invention.
Fig. 6 is a schematic diagram of an encoding format of a Type5 instruction encoding format in a RISC-architecture-based CPU instruction set system according to the present invention.
Fig. 7 is a schematic diagram of an encoding format of a Type6 instruction encoding format in a RISC-architecture-based CPU instruction set system according to the present invention.
Fig. 8 is a schematic diagram of an encoding format of a Type7 instruction encoding format in a RISC-architecture-based CPU instruction set system according to the present invention.
Fig. 9 is a schematic diagram of an encoding format of a Type8 instruction encoding format in a RISC-architecture-based CPU instruction set system according to the present invention.
Fig. 10 is a schematic diagram of an encoding format of a Type9 instruction encoding format in a RISC-based CPU instruction set system according to the present invention.
FIG. 11 is a schematic diagram of the encoding format of Type10 instruction in the RISC-based CPU instruction set system according to the present invention.
Fig. 12 is a schematic diagram of an encoding format of a Type11 instruction encoding format in a RISC-based CPU instruction set system according to the present invention.
Fig. 13 is a schematic diagram of an encoding format of a Type12 instruction encoding format in a RISC-architecture-based CPU instruction set system according to the present invention.
FIG. 14 is a schematic diagram of a RISC architecture based CPU system according to the present invention.
Detailed Description
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present. As used in this specification, the terms "upper," "lower," "inner," "outer," "bottom," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the invention and simplicity in description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Furthermore, the technical features mentioned in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.
In one embodiment, as shown in fig. 1, the present invention provides a RISC architecture-based CPU instruction set system, which is applied to a RISC architecture-based CPU system, where the CPU system includes a RISC architecture-based CPU, a first register Ga, a second register Gb, a third register Gc, a program pointer PC, and 32-bit general function registers (G0-G31); wherein: the CPU instruction set system includes:
the method comprises the following steps of CPU instruction set encoding, wherein the CPU instruction set encoding is in an instruction set encoding format with the same length of 32 bits, supports 32-bit general function registers (G0-G31), and comprises an operation code field Opcode with different lengths, a first register index field Ga, a second register index field Gb, a third register index field Gc, an address Offset field Offset and an immediate field Imm; the instruction encoding method is characterized in that the instruction encoding method comprises operating code fields Opcode with different bit lengths and at least one of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset and the immediate field Imm, or comprises all operating code fields Opcode with different instruction encoding format types, and is used for executing at least one preset operating instruction as follows: the system comprises a jump instruction, a memory access instruction, a mathematical operation instruction, a logic operation instruction, a comparison instruction, a test instruction, a system call instruction, a shift instruction, a bit operation instruction, a condition test instruction, a system special operation instruction, a program return instruction and a miscellaneous instruction.
In the embodiment, 32-bit general function registers (G0-G31) are supported by a CPU instruction set system based on a RISC (reduced instruction set computer) architecture, wherein the CPU instruction set system comprises a 32-bit equal-length CPU instruction set code, and the instruction set code format comprises an operation code field Opcode with an indefinite length, a first register index field Ga, a second register index field Gb, a third register index field Gc, an address Offset field Offset and an immediate field Imm; the operation code field Opcode with different bit lengths is combined with the other fields, or the operation code field Opcode forms different instruction encoding format types, which are used for executing the preset operation instruction. Therefore, a set of RISC instruction set with complete basic functions is provided, the offset address range of the jump instruction is enlarged on the basis of the RISC instruction set, the jump address range which is larger than that of other existing instruction sets is obtained under the condition of the same instruction coding with the word length of 32 bits, and the occurrence probability of program scenes needing to increase instruction overhead due to insufficient jump instruction address range can be reduced, so that the programming difficulty and the program performance can be effectively reduced, and the running performance of a CPU processor can be improved.
In one embodiment, the Opcode field Opcode is used to distinguish between instructions of different functions, and provides a separate binary encoding for each instruction, indicating instruction uniqueness, such that each instruction has a unique binary encoding specific to it.
The Opcode field Opcode is indefinite and unfixed in length, the length of the Opcode field Opcode depends on the remaining length of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset, and/or the immediate field Imm in the 32-bit long instruction set encoding format after the lengths of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset, and/or the immediate field Imm are added, and the Opcode field Opcode is 4 bits in shortest and 32 bits in longest.
The start position of the Opcode field Opcode in an instruction set encoding format with an equal length of 32 bits is located at the 0 th bit or the 31 th bit of the CPU instruction set encoding, and the specific start positions are: a number of bits in order from the 0 th bit of the CPU instruction set encoding or a number of bits in inverse order from the 31 th bit of the CPU instruction set encoding. Preferably, the Opcode field Opcode is located several digits from bit 0 of the CPU instruction set encoding.
The first register index field Ga is a fixed 5-bit length, and the first register index field Ga indicates an index value of a first register to be operated by the instruction, and is used for designating the CPU to access one register of the 32 general-purpose functional registers to obtain a first operand.
The second register index field Gb is a fixed 5-bit length, and the second register index field Gb indicates an index value of a second register to be operated by the instruction, and is used to designate the CPU to access one of the 32 general-purpose functional registers to obtain a second operand or to store an instruction operation result.
The third register index field Gc is of a fixed 5-bit length, and the third register index field Gc represents an index value of a third register to be operated by the instruction, and is used for designating the CPU to access one register of the 32 general-purpose functional registers to obtain a third operand.
The address Offset field Offset is a fixed length of 16 bits or 18 bits or 28 bits, and represents an address Offset of an addressing-class instruction (including a jump instruction and a memory access instruction) for providing an address Offset for the jump instruction or the memory access instruction to generate a target address.
The immediate field Imm is of fixed 5-bit or 16-bit length and represents a literal operand directly available from the instruction for providing the operand directly for instruction operations.
In this embodiment, the instruction set codes are 32-bit equal length, and are binary codes, and include an operation code field Opcode with an indefinite length of 4 bits and a longest length of 32 bits, a first register index field Ga with a length of 5 bits, a second register index field Gb with a length of 5 bits, a third register index field Gc with a length of 5 bits, an address Offset field Offset with a length of 16 bits or 18 bits or 28 bits, and an immediate field Imm with a length of 5 bits or 16 bits, where the operation code field Opcode with different bit lengths is combined with at least one of the first register index field Ga, the second register index field, the third register index field Gc, the address Offset field Offset, and the immediate field Imm, or all the operation code fields Opcode form different instruction coding format types for executing a preset operation instruction. Therefore, a set of RISC instruction set with complete basic functions is provided, the offset address range of the jump instruction is enlarged on the basis of the RISC instruction set, the jump address range which is larger than that of other existing instruction sets is obtained under the condition of the same instruction coding with the word length of 32 bits, and the occurrence probability of program scenes needing to increase instruction overhead due to insufficient jump instruction address range can be reduced, so that the programming difficulty and the program performance can be effectively reduced, and the running performance of a CPU processor can be improved.
In one embodiment, the CPU instruction set is encoded in an instruction set encoding format with an equal length of 32 bits, and includes different instruction encoding format types composed of operation code fields Opcode with different bit lengths in combination with the above other fields, or composed of operation code fields Opcode entirely, and is configured to execute at least one of the following preset operation instructions: the system comprises a jump instruction, a memory access instruction, a mathematical operation instruction, a logic operation instruction, a comparison instruction, a test instruction, a system call instruction, a shift instruction, a bit operation instruction, a condition test instruction, a system special operation instruction, a program return instruction and a miscellaneous instruction.
Wherein, as shown in FIG. 1, the CPU instruction set code at least comprises 12 instruction coding format types, which are Type1 instruction coding format Type, Type2 instruction coding format Type, Type3 instruction coding format Type, Type4 instruction coding format Type, Type5 instruction coding format Type, Type6 instruction coding format Type, Type7 instruction coding format Type, Type8 instruction coding format Type, Type9 instruction coding format Type, Type10 instruction coding format Type, Type11 instruction coding format Type, Type12 instruction coding format Type, each instruction coding format Type is composed of different combinations of Opcode fields Opcode with different bit lengths and different combinations of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset and the immediate digit field Imm, or all consist of combinations of Opcode fields Opcode to execute different preset operation instructions.
In one embodiment, as shown in FIG. 2, the Type1 instruction encoding format Type includes a combination of an Opcode field Opcode of 4 bits length and an address Offset field Offset of 28 bits length.
The Type1 instruction encoding format Type can be used for, but is not limited to, executing the following preset operation instructions: unconditional jump instruction with program pointer PC as base and Offset as Offset.
When the preset operation instruction is a jump instruction:
effective Offset address = { Offset, 2 'b 00}, where 2' b00 denotes that the instruction length is fixed to 4 bytes, since the jump is in units of 1 complete instruction, the actual effective Offset address needs to be calculated by shifting Offset to the left by 2 bits, and the effective Offset address range =230A byte.
Since the instructions are 32 bits, i.e. 4 bytes long, the actual addressing space is determined by shifting the address Offset field Offset of 28 bits long to the left by 2 bits, i.e. 30 bits, i.e. the effective instruction jump range of a single instruction is 1GB, which is 4 times that of the existing instruction set.
Table 1 shows that the instructions that can be encoded by the Type1 instruction encoding format Type are completely listed for this embodiment, where the instructions that can be encoded by the Type1 instruction encoding format Type include 2 instructions.
TABLE 1 types 1 Instructions that the instruction encoding format Type can encode
Figure 216354DEST_PATH_IMAGE001
In this embodiment, the Type1 instruction encoding format Type obtains a jump address range larger than other existing instruction sets under the same instruction encoding condition with a word length of 32 bits, and can reduce the occurrence probability of a program scenario requiring an increase in instruction overhead due to an insufficient jump instruction address range, thereby effectively reducing the programming difficulty and improving the program performance, and improving the running performance of the CPU processor.
In one embodiment, as shown in fig. 3, the Type2 instruction encoding format Type includes a 6-bit long Opcode field Opcode, a first register index field Ga, a second register index field Gb, and a 16-bit long address Offset field Offset.
The Type2 instruction encoding format Type can be used for, but is not limited to, executing at least one preset operation instruction as follows: the jump instruction comprises a memory access instruction with a register as a base address and Offset as an Offset and a conditional jump instruction with a program pointer PC as a base address and Offset as an Offset.
When the preset operation instruction is a jump instruction:
effective Offset address = { Offset, 2 'b 00}, where 2' b00 denotes that the instruction length is fixed to 4 bytes, since the jump is in units of 1 complete instruction, the actual effective Offset address needs to be calculated by shifting Offset to the left by 2 bits, and the effective Offset address range =218A byte.
When the preset operation instruction is a memory access instruction:
effective Offset Address = Offset, effectively OffsetAddress space =216A byte.
The first and second register index fields Ga and Gb may instruct the CPU to access any one of the 32 general-purpose function registers (G0-G31) according to its index value.
Table 2 shows that the instructions that can be encoded by the Type2 instruction encoding format Type are completely listed for this embodiment, where the instructions that can be encoded by the Type2 instruction encoding format Type include 13 instructions, i.e., a memory access instruction and a jump instruction.
TABLE 2 types 2 Instructions that the instruction encoding format Type can encode
Figure 27708DEST_PATH_IMAGE002
In one embodiment, as shown in fig. 4, the Type3 instruction encoding format Type includes a 6-bit length Opcode field Opcode, a first register index field Ga, a second register index field Gb, and a 16-bit length immediate field Imm.
The Type3 instruction encoding format Type can be used for, but is not limited to, executing at least one preset operation instruction as follows: an arithmetic instruction using a register and an immediate as operands, and a comparison instruction using a register and an immediate as operands.
When the preset operation instruction is a signed calculation instruction:
effective immediate number = {16{ Imm [15] }, Imm }, where Imm [15] is the most significant bit of Imm, i.e., the sign bit, so that a true effective immediate number can only be obtained after sign extension thereof.
Effective immediate size range: -32768- +32767
When the preset operation instruction is an unsigned calculation instruction:
effective immediate number = { 16' b0000_0000_0000_0000, Imm }
Effective immediate size range: 0 to 65535
The first and second register index fields Ga and Gb may instruct the CPU to access any one of the 32 general-purpose function registers (G0-G31) according to its index value.
Table 3 shows that the instructions that can be encoded by the Type3 instruction encoding format Type are completely listed for this embodiment, wherein the instructions that can be encoded by the Type3 instruction encoding format Type include 12 instructions, i.e., a mathematical operation instruction, a logical operation instruction, and a comparison instruction.
TABLE 3 types of Instructions that can be encoded by the Type of encoding format of the Type3 instruction
Figure 551835DEST_PATH_IMAGE003
In one embodiment, as shown in FIG. 5, the Type4 instruction encoding format Type comprises a 9-bit long Opcode field, Opcode, a first register index field, Ga, and an 18-bit long address Offset field, Offset.
The Type4 instruction encoding format Type can be used for, but is not limited to, executing the following preset operation instructions: the unconditional jump instruction comprises an unconditional jump instruction with a register as a base address and Offset as an Offset.
When the preset operation instruction is a jump instruction:
effective Offset address = { Offset, 2 'b 00}, where 2' b00 denotes that the instruction length is fixed to 4 bytes, since the jump is in units of 1 complete instruction, the actual effective Offset address needs to be calculated by shifting Offset to the left by 2 bits, and the effective Offset address range =220A byte.
When the preset operation instruction is a memory access instruction:
effective Offset address = Offset, effective Offset address space =218A byte.
The first register index field Ga may instruct the CPU to access any one of the 32 general function registers (G0-G31) according to its index value.
Since the instructions are 32 bits, i.e. 4 bytes long, the actual addressing space is determined by shifting the address Offset field Offset of 18 bits long to the left by 2 bits, i.e. 20 bits, i.e. the effective instruction jump range of a single instruction is 1MB, which is 4 times that of the existing instruction set.
Table 4 shows that the instructions that can be encoded by the Type4 instruction encoding format Type are completely listed for this embodiment, where the instructions that can be encoded by the Type4 instruction encoding format Type include 2 instructions.
TABLE 4 types 4 Instructions that the instruction encoding format Type can encode
Figure 820137DEST_PATH_IMAGE004
In this embodiment, the jump Type instruction defined by the Type4 instruction encoding format Type obtains a jump address range larger than other existing instruction sets under the same instruction encoding condition of 32-bit word length, and can reduce the occurrence probability of a program scenario requiring instruction overhead increase due to insufficient jump instruction address range, thereby effectively reducing the programming difficulty and improving the program performance, and improving the running performance of the CPU processor.
In one embodiment, as shown in FIG. 6, the Type5 instruction encoding format Type comprises an Opcode field Opcode of 11 bits length, a first register index field Ga and an immediate field Imm of 16 bits length.
The Type5 instruction encoding format Type can be used for, but is not limited to, executing at least one preset operation instruction as follows: an arithmetic instruction with a register and an immediate as operands, and a conditional test instruction with a register and an immediate as operands.
When the preset operation instruction is a signed calculation instruction:
effective immediate number = {16{ Imm [15] }, Imm }, where Imm [15] is the most significant bit of Imm, i.e., the sign bit, so that a true effective immediate number can only be obtained after sign extension thereof.
Effective immediate size range: -32768- +32767
When the preset operation instruction is an unsigned calculation instruction:
effective immediate number = { 16' b0000_0000_0000_0000, Imm }
Effective immediate size range: 0 to 65535
The first register index field Ga may instruct the CPU to access any one of the 32 general function registers (G0-G31) according to its index value.
Table 5 shows that the instructions that can be encoded by the Type5 instruction encoding format Type are completely listed for this embodiment, where the instructions that can be encoded by the Type5 instruction encoding format Type include conditional test instructions, which are 6 instructions in total.
TABLE 5 types 5 Instructions that the instruction encoding format Type can encode
Figure 516697DEST_PATH_IMAGE005
In one embodiment, as shown in fig. 7, the Type6 instruction encoding format Type includes a 12-bit long Opcode field Opcode, a first register index field Ga, a second register index field Gb, and a 10-bit long immediate field Imm.
The Type6 instruction encoding format Type can be used for, but is not limited to, executing the following preset operation instructions: bit-operating instructions with registers and immediate as operands.
When the preset operation instruction is a signed calculation instruction:
effective immediate number = {22{ Imm [9] }, Imm }, where Imm [9] is the most significant bit of Imm, i.e., the sign bit, so that a true effective immediate number can only be obtained after sign extension thereof.
Effective immediate size range: -512 to +511
When the preset operation instruction is an unsigned calculation instruction:
effective immediate number = { 22' b00_0000_0000_0000, Imm }
Effective immediate size range: 0 to 1023
The first and second register index fields Ga and Gb may instruct the CPU to access any one of the 32 general-purpose function registers (G0-G31) according to its index value.
Table 6 shows that the instructions that can be encoded by the Type6 instruction encoding format Type are completely listed for this embodiment, where the instructions that can be encoded by the Type6 instruction encoding format Type include 2 instructions.
TABLE 6 types 6 Instructions that the instruction encoding format Type can encode
Figure 128813DEST_PATH_IMAGE006
In one embodiment, as shown in FIG. 8, the Type7 instruction encoding format Type includes a Type consisting of an Opcode field Opcode of 16 bits length and an immediate field Imm of 16 bits length.
The Type7 instruction encoding format Type can be used for, but is not limited to, executing the following preset operation instructions: a system call instruction with an immediate as a single operand.
When the preset operation instruction is a signed calculation instruction:
effective immediate number = {16{ Imm [15] }, Imm }, where Imm [15] is the most significant bit of Imm, i.e., the sign bit, so that a true effective immediate number can only be obtained after sign extension thereof.
Effective immediate size range: -32768- +32767
When the preset operation instruction is an unsigned calculation instruction:
effective immediate number = { 16' b0000_0000_0000_0000, Imm }
Effective immediate size range: 0 to 65535
Table 7 shows that the instructions that can be encoded by the Type7 instruction encoding format Type are completely listed for this embodiment, where the instructions that can be encoded by the Type7 instruction encoding format Type include 1 instruction, a system call instruction.
TABLE 7 types 7 Instructions that the instruction encoding format Type can encode
Figure 227219DEST_PATH_IMAGE007
In one embodiment, as shown in fig. 9, the Type8 instruction encoding format Type includes an Opcode field Opcode of 17-bit length, a first register index field Ga, a second register index field Gb and a third register index field Gc.
The Type8 instruction encoding format Type can be used for, but is not limited to, executing at least one preset operation instruction as follows: the operation instruction with 2 registers as operands comprises a memory access instruction with 1 register as a base address and 1 register as an offset, a conditional jump instruction with 2 registers as operands, a comparison instruction with 2 registers as operands, a shift instruction with 2 registers as operands, and a conditional transfer instruction with 2 registers as operands.
The first, second and third register index fields Ga, Gb, Gc may instruct the CPU to access any one of the 32 general-purpose function registers (G0-G31) according to its index value.
Table 8 shows that the instructions that can be encoded by the Type8 instruction encoding format Type are completely listed for this embodiment, where the instructions that can be encoded by the Type8 instruction encoding format Type include 36 instructions, i.e., a mathematical operation instruction, a logical operation instruction, a memory access instruction, a conditional jump instruction, a compare instruction, a shift instruction, and a conditional transfer instruction.
TABLE 8 types 8 Instructions that the instruction encoding format Type can encode
Figure 932001DEST_PATH_IMAGE008
In one embodiment, as shown in fig. 10, the Type9 instruction encoding format Type includes an Opcode field Opcode of 17 bits in length, a first register index field Ga, a second register index field Gb and an immediate field Imm of 5 bits in length.
The Type9 instruction encoding format Type can be used for, but is not limited to, executing the following preset operation instructions: shift instructions with registers and immediate as operands.
When the preset operation instruction is a signed calculation instruction:
effective immediate number = {27{ Imm [4] }, Imm }, where Imm [4] is the most significant bit of Imm, i.e., the sign bit, so that a true effective immediate number can only be obtained after sign extension thereof.
Effective immediate size range: -16 to +15
When the preset operation instruction is an unsigned calculation instruction:
effective immediate number = { 27' b000_0000_0000_0000_0000_0000_0000, Imm }
Effective immediate size range: 0 to 31
The first and second register index fields Ga and Gb may instruct the CPU to access any one of the 32 general-purpose function registers (G0-G31) according to its index value.
Table 9 shows that the instructions that can be encoded by the Type9 instruction encoding format Type are completely listed for this embodiment, where the instructions that can be encoded by the Type9 instruction encoding format Type include 4 instructions.
TABLE 9 types 9 Instructions that the instruction encoding format Type can encode
Figure 850279DEST_PATH_IMAGE009
In one embodiment, as shown in fig. 11, the Type10 instruction encoding format Type includes an Opcode field Opcode of 22-bit length, a first register index field Ga, and a second register index field Gb.
The Type10 instruction encoding format Type can be used for, but is not limited to, executing at least one preset operation instruction as follows: the system comprises a bit operation instruction with 1 register as a single operand, a system special operation instruction with 1 register as a parameter, and a condition test instruction with 2 registers as operands.
The first and second register index fields Ga and Gb may instruct the CPU to access any one of the 32 general-purpose function registers (G0-G31) according to its index value.
Table 10 shows that the instructions that can be encoded by the Type10 instruction encoding format Type are completely listed for this embodiment, where the instructions that can be encoded by the Type10 instruction encoding format Type include 12 instructions, namely, a bit operation instruction and a conditional test instruction.
TABLE 10 Type10 Instructions that the encoding format Type can encode
Figure 16818DEST_PATH_IMAGE010
In one embodiment, as shown in FIG. 12, the Type11 instruction encoding format Type comprises of an Opcode field Opcode of 27 bits length and a first register index field Ga.
The Type11 instruction encoding format Type can be used for, but is not limited to, executing the following preset operation instructions: system specific operation instruction using register as parameter.
The first register index field Ga may instruct the CPU to access any one of the 32 general function registers (G0-G31) according to its index value.
Table 11 shows that the instructions that can be encoded by the Type11 instruction encoding format Type are completely listed for this embodiment, where the instructions that can be encoded by the Type11 instruction encoding format Type include 1 instruction, which is a special operation instruction of the system.
TABLE 11 Type11 Instructions that the encoding format Type can encode
Figure 690769DEST_PATH_IMAGE011
In one embodiment, as shown in FIG. 13, the Type12 instruction encoding format Type comprises an Opcode field Opcode of 32 bits in length.
The Type1 instruction encoding format Type can be used for, but is not limited to, executing at least one preset operation instruction as follows: the method comprises a program return instruction, a miscellaneous instruction and a system special operation instruction.
Table 12 shows that, for this embodiment, the instructions that can be encoded by the Type12 instruction encoding format Type are completely listed, where the instructions that can be encoded by the Type12 instruction encoding format Type include a return instruction ret, a miscellaneous instruction (e.g., no operation instruction NOP), and a system special operation instruction (e.g., SLEEP), which are 3 instructions in total.
TABLE 12 Type12 Instructions that the instruction encoding format Type can encode
Figure 18982DEST_PATH_IMAGE012
The invention provides a CPU instruction set system based on RISC framework, which provides a set of RISC instruction set with complete basic functions, contains necessary instructions required by the current general RISC processor, can complete the functions of mathematical operation, logic operation, bit operation, data transmission, program control and the like of the general RISC processor in an integer range, increases the offset address range of jump instructions on the basis of the RISC instruction set, obtains a jump address range larger than other existing instruction sets under the condition of the same 32-bit word length instruction coding, can reduce the occurrence probability of program scenes needing to increase instruction overhead due to insufficient jump instruction address range, thereby effectively reducing programming difficulty and improving program performance and improving the running performance of the CPU processor.
Based on the same concept, in an embodiment, as shown in fig. 14, the present invention provides a CPU system based on RISC architecture, where the CPU system includes a CPU based on RISC architecture and a CPU instruction set system based on RISC architecture as described in any of the above embodiments, and the CPU is configured to run the CPU instruction set system based on RISC architecture.
In this embodiment, the RISC architecture-based CPU instruction set system is identical to the RISC architecture-based CPU instruction set system described in any of the above embodiments, and specific structures and functions may refer to the RISC architecture-based CPU instruction set system described in any of the above embodiments, which is not described herein again.
In this embodiment, the RISC architecture based CPU system includes a RISC architecture CPU and a RISC architecture based CPU instruction set system, and the CPU is configured to run the RISC architecture based CPU instruction set system. The CPU instruction set system based on the RISC architecture comprises a 32-bit equal-length CPU instruction set code and supports 32-bit general function registers (G0-G31), wherein the instruction set code format comprises an operation code field Opcode with an indefinite length, a first register index field Ga, a second register index field Gb, a third register index field Gc, an address Offset field Offset and an immediate field Imm; the instruction encoding method is characterized in that the instruction encoding method comprises operating code fields Opcode with different bit lengths and at least one of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset and the immediate field Imm, or comprises all the operating code fields Opcode to form different instruction encoding format types, and the operating code fields Opcode are used for executing preset operating instructions. Therefore, a set of RISC instruction set with complete basic functions is provided, the offset address range of the jump instruction is enlarged on the basis of the RISC instruction set, the jump address range which is larger than that of other existing instruction sets is obtained under the condition of the same instruction coding with the word length of 32 bits, and the occurrence probability of program scenes needing to increase instruction overhead due to insufficient jump instruction address range can be reduced, so that the programming difficulty and the program performance can be effectively reduced, and the running performance of a CPU processor can be improved.
It should be noted that the above-mentioned embodiment of the CPU system and the embodiment of the CPU instruction set system based on the RISC architecture belong to the same concept, and the specific implementation process thereof is described in detail in the embodiment of the CPU instruction set system based on the RISC architecture, and the technical features in the embodiment of the CPU instruction set system based on the RISC architecture are applicable to the embodiment of the CPU system, and are not described herein again.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (15)

1. A CPU instruction set system based on RISC architecture is characterized in that the CPU instruction set system is applied to a CPU system based on RISC architecture, and the CPU instruction set system comprises: encoding a CPU instruction set;
the CPU instruction set is coded into an instruction set coding format with the same length of 32 bits, 32-bit general function registers are supported, and the instruction set coding format comprises an operation code field Opcode with an indefinite length, a first register index field Ga, a second register index field Gb, a third register index field Gc, an address Offset field Offset and an immediate digital field Imm; the instruction encoding method is characterized in that the instruction encoding method comprises operating code fields Opcode with different bit lengths and at least one of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset and the immediate field Imm, or comprises all operating code fields Opcode with different instruction encoding format types, and is used for executing at least one preset operating instruction as follows: a jump instruction, a memory access instruction, a mathematical operation instruction, a logic operation instruction, a comparison instruction, a test instruction, a system call instruction, a shift instruction, a bit operation instruction, a condition test instruction, a system special operation instruction, a program return instruction and a miscellaneous instruction;
the operation code field Opcode is used for distinguishing instructions with different functions and providing independent binary codes for each instruction; the Opcode field Opcode is indefinite and unfixed in length, the length of the Opcode field Opcode depends on the remaining length of the first register index field Ga, the second register index field Gb, the third register index field Gc, the address Offset field Offset and/or the immediate field Imm in an instruction set encoding format with 32 bits of equal length after being added, and the Opcode field Opcode is 4 bits in shortest and 32 bits in longest;
the start position of the Opcode field Opcode in an instruction set encoding format with an equal length of 32 bits is located at the 0 th bit or the 31 th bit of the CPU instruction set encoding, and the specific start positions are: a number of bits in order from the 0 th bit of the CPU instruction set encoding or a number of bits in inverse order from the 31 th bit of the CPU instruction set encoding.
2. The system of claim 1, wherein the first register index field Ga is a fixed 5-bit length, the first register index field Ga specifying that the CPU access one of the 32 general purpose functional registers to obtain a first operand;
the second register index field Gb is a fixed 5-bit length, and the second register index field Gb is used to designate the CPU to access one register of the 32 general-purpose functional registers to obtain a second operand or to store an instruction operation result;
the third register index field Gc is of a fixed 5-bit length, and is used for designating a CPU to access one register of 32 general-purpose functional registers to obtain a third operand;
the address Offset field Offset is a fixed 16-bit or 18-bit or 28-bit length, the address Offset field Offset is used to provide an address Offset for a jump instruction or a memory access instruction to generate a target address;
the immediate field Imm is of a fixed 5-bit or 16-bit length and is used to directly provide operands for instruction operations.
3. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type1 instruction encoding format Type, the Type1 instruction encoding format Type comprising of an Opcode field Opcode of 4 bits length and an address Offset field Offset of 28 bits length;
the Type1 instruction encoding format Type is used for executing the following preset operation instructions: the jump instruction comprises an unconditional jump instruction with a program pointer PC as a base address and Offset as an Offset.
4. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type2 instruction encoding format Type, the Type2 instruction encoding format Type comprising of a 6 bit length Opcode field Opcode, a first register index field Ga, a second register index field Gb, and a 16 bit length address Offset field Offset;
the Type2 instruction encoding format Type is used for executing at least one preset operation instruction as follows: the jump instruction comprises a memory access instruction with a register as a base address and Offset as an Offset and a conditional jump instruction with a program pointer PC as a base address and Offset as an Offset.
5. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type3 instruction encoding format Type, the Type3 instruction encoding format Type comprising a 6 bit length Opcode field Opcode, a first register index field Ga, a second register index field Gb, and a 16 bit length immediate field Imm;
the Type3 instruction encoding format Type is used for executing at least one preset operation instruction as follows: an arithmetic instruction using a register and an immediate as operands, and a comparison instruction using a register and an immediate as operands.
6. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type4 instruction encoding format Type, the Type4 instruction encoding format Type comprising a 9 bit length Opcode field Opcode, a first register index field Ga, and an 18 bit length address Offset field Offset;
the Type4 instruction encoding format Type is used for executing the following preset operation instructions: the unconditional jump instruction comprises an unconditional jump instruction with a register as a base address and Offset as an Offset.
7. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type5 instruction encoding format Type, the Type5 instruction encoding format Type comprising an 11 bit length Opcode field Opcode, a first register index field Ga, and a 16 bit length immediate field Imm;
the Type5 instruction encoding format Type is used for executing at least one preset operation instruction as follows: an arithmetic instruction with a register and an immediate as operands, and a conditional test instruction with a register and an immediate as operands.
8. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type6 instruction encoding format Type, the Type6 instruction encoding format Type comprising a 12 bit length Opcode field Opcode, a first register index field Ga, a second register index field Gb, and a 10 bit length immediate field Imm;
the Type6 instruction encoding format Type is used for executing the following preset operation instructions: bit-operating instructions with registers and immediate as operands.
9. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type7 instruction encoding format Type, the Type7 instruction encoding format Type comprising of a 16 bit length Opcode field Opcode and a 16 bit length immediate field Imm;
the Type7 instruction encoding format Type is used for executing the following preset operation instructions: a system call instruction with an immediate as a single operand.
10. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type8 instruction encoding format Type, the Type8 instruction encoding format Type comprising an Opcode field Opcode consisting of a 17 bit length, a first register index field Ga, a second register index field Gb, and a third register index field Gc;
the Type8 instruction encoding format Type is used for executing at least one preset operation instruction as follows: the operation instruction with 2 registers as operands comprises a memory access instruction with 1 register as a base address and 1 register as an offset, a conditional jump instruction with 2 registers as operands, a comparison instruction with 2 registers as operands, a shift instruction with 2 registers as operands, and a conditional transfer instruction with 2 registers as operands.
11. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type9 instruction encoding format Type, the Type9 instruction encoding format Type comprising an Opcode field Opcode of 17 bits length, a first register index field Ga, a second register index field Gb, and an immediate field Imm of 5 bits length;
the Type9 instruction encoding format Type is used for executing the following preset operation instructions: shift instructions with registers and immediate as operands.
12. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type10 instruction encoding format Type, the Type10 instruction encoding format Type comprising an Opcode field Opcode consisting of a 22 bit length, a first register index field Ga, and a second register index field Gb;
the Type10 instruction encoding format Type is used for executing at least one preset operation instruction as follows: the system comprises a bit operation instruction with 1 register as a single operand, a system special operation instruction with 1 register as a parameter, and a condition test instruction with 2 registers as operands.
13. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type11 instruction encoding format Type, the Type11 instruction encoding format Type comprising of an Opcode field Opcode of 27 bits length and a first register index field Ga;
the Type11 instruction encoding format Type is used for executing the following preset operation instructions: system specific operation instruction using register as parameter.
14. The system of claim 1, wherein the CPU instruction set encoding comprises at least a Type12 instruction encoding format Type, the Type12 instruction encoding format Type comprising an Opcode field Opcode of 32 bits length;
the Type12 instruction encoding format Type is used for executing one of the following preset operation instructions: including program return instructions, miscellaneous instructions, and system-specific operating instructions.
15. A RISC architecture based CPU system, comprising a RISC architecture CPU and a RISC architecture based CPU instruction set system according to any of claims 1 to 14, said CPU being adapted to run said RISC architecture based CPU instruction set system.
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