CN1434458A - Method and device for dynamically hiding memory defect - Google Patents
Method and device for dynamically hiding memory defect Download PDFInfo
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- CN1434458A CN1434458A CN 02102496 CN02102496A CN1434458A CN 1434458 A CN1434458 A CN 1434458A CN 02102496 CN02102496 CN 02102496 CN 02102496 A CN02102496 A CN 02102496A CN 1434458 A CN1434458 A CN 1434458A
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Abstract
The invention is a method and device can hide the bug of memory dynamically, the memory has at least one bug memory area; in one example, a memory area comparison table includes plural columns, each column is corresponding to a memory area, in the initial testing program of the memory, the column in comparison table corresponding to the bug memory area is signed, makes that it is considered it has been used, so the bug memory area can't be used; in another example, selects substituted memory area from a spare temporary register, each substituted memory area is corresponding to a bug memory area, the following access of bug memory area is redirected to correspondent substituted memory area.
Description
Technical field
The present invention relates to a kind of storer, especially a kind of method of dynamically concealing memory defect and device (method and apparatus for dynamically hiding memorydefect), the present invention is particularly useful for the having in-line memory wafer of (embedded memory).
Background technology
Defective in storer may cause the misoperation (malfunction) of system and not have the unexpected when machine (abrupt shutdown without advance warning) of early warning, this not only will expend the considerable time of user, also may cause the loss that is difficult to remedy.Yet, in the manufacture process of storer, the above storer generation defective of certain proportion is always arranged inevitably, normally, after finishing, storer is tested immediately, so that find defective storer and it is abandoned in the wafer manufacturing, but, the abandoning of storer causes loss, and especially the capacity of storer constantly is enhanced and process technique constantly progresses greatly, and wafer is only because the defective of only a few just is abandoned different from unfortunately.For the wafer with minority blemish still can be used, and needn't abandon, redundancy structure (redundancy scheme) is used to replace (replace) or repairs (repair) impaired memory bank.Typically, the method for repairing and mending of redundancy structure comprises the quadruplet program: test, analysis, repairing and test again, in the first cover program, nationality is by storer being bestowed the position that out of memory (failure) takes place with detecting a series of test signal aspect (test signal pattern), routine analyzer planning then and decision are used for the optimization of the redundant memory of correction of the defect storer, blown fuse (fuse) in Hotfix then, with the definition circuit connection and do not connect, again test more at last correctly operates to confirm the wafer after the repairing.
Though using redundancy structure to come patch memory can reduce wafer is abandoned, but these extra circuit and fuse occupy considerable chip area and make circuit and processing procedure complicates, not only increase cost, also make wafer become big, and this type of method for repairing and mending must expend long time on test procedure and routine analyzer, also increases considerable time and cost.More shape is serious in having the wafer of in-line memory for the problem that causes of blemish, this is more many than independent (stand-alone) memory chips complexity because of its circuit of wafer with in-line memory, in-line memory is owing to still there are many circuit around it, will test it and have higher degree of difficulty, the tester of use (tester) costliness and test procedure are more tediously long.Many schemes are suggested improves these shortcomings, for example, people such as Chan are at United States Patent (USP) the 5th, 841, a kind of method and circuit are proposed in No. 784, utilize one to switch circuit, make the storer that is embedded in the integrated circuit during memory test patterns, temporarily be coupled to line joint sheet (Interconnect pad), to reduce test duration and cost; People such as Irrinki are at United States Patent (USP) the 6th, 067, a kind of redundancy analysis methodology (redundancyanalysis methodology) with built-in self-test (built-in-sclf-test) and built-in self-repair (built-in-self-repair) circuit is provided in No. 262, make in-line memory to be tested, and allow detecting on-the-spot wrong (field error) relevant with operating conditions by the logic tester of standard; Wheater is at United States Patent (USP) the 6th, 073, discloses a kind of method and device of carrying out the redundant computation of two dimension in No. 258, with avoid testing and Hotfix in the collection of inefficacy data.
When the demand of bigger in-line memory was grown up, because the yield that processing procedure caused restriction also and then increases, though redundancy testing typically is used to do functional test, this method often was not enough or unpractical for bigger in-line memory.Therefore the design of in-line memory and the degree of difficulty of manufacturing are higher, and abandon the loss that wafer causes for blemish also bigger, more wish to reduce as far as possible wafer and are abandoned so have the wafer of in-line memory.McClure is at United States Patent (USP) the 5th, 471, propose a kind of method and structure in No. 431, utilize fuse circuit from an in-line memory, to define some, make abandoning of wafer minimize though obtain less in-line memory with function with function.
Yet, aforesaid prior art can only be got rid of the defective of finding at that time, this is static or fixing repairing, in case finish Hotfix, storer is changeless, and wafer starts now after using future or the defective that takes place can not be excluded, the wafer of this generation defective finally will be abandoned, more seriously, these defectives afterwards will cause wafer misoperation or the system in the use to work as machine, thereby cause bigger loss.Kablanian is at United States Patent (USP) the 5th, 764, a kind of built-in self-repair of suggestion system has on the wafer of in-line memory in No. 878, during the power initiation (power up) of each computer system, automatically carry out test as the aforementioned, repair and test again supervisor, this method can reach dynamically patch memory defective, but must introduce huge and complicated circuit on wafer, and all must experience aforesaid complicated tediously long program each time during the power initiation of computer system, and all must regroup the address translation table of storer each time, therefore also impracticable, in case and blemish is too many, surpass the quantity that redundant circuit can be repaired, system will work as machine.People such as Correale Jr. are at United States Patent (USP) the 6th, 192, a kind of blemish operating circuit (memory defect steering circuit) is provided in No. 486, it does not use fuse to repair, and detecting and avoid the storer of (bypass) defective when each computer system starts, recomputate the size of efficient memory again and transform storage address, though this method reduces the size of storer, but can dynamically get rid of blemish, but, recomputate the size of efficient memory at every turn and transform storage address still inconvenient, and the circuit of the transformation storage address that increases need take suitable area, again when shining upon (remapping) storage address again, because storage address is successional, the storer that can not get rid of defective individually must be brought into use from the next memory block of the memory block of defective, and the memory block before behind the memory block of defective all has been wasted.
Summary of the invention
The present invention promptly proposes a kind of method and device of dynamically concealing memory defect for the disappearance of improving aforementioned prior art, the present invention does not use fuse to come patch memory, but blemish covered (mask), thereby avoided tediously long and complicated analysis, repairing to reach the program of test again, the present invention may cause reducing the size of storer, but make defective wafer to be used, and needn't abandon.
One of purpose of the present invention is to utilize a kind of simple and direct method and device, to get rid of blemish.
One of purpose of the present invention is to reduce wafer and is abandoned because of blemish.
One of purpose of the present invention is dynamically to get rid of blemish, finds when wafer starts each time and hides wherein blemish.
One of purpose of the present invention is that the circuit of avoiding huge and redundant is got involved in the wafer.
One of purpose of the present invention is to avoid rerunning because of blemish the content of storage address.
One of purpose of the present invention is the functional circuit that has kept on the wafer with in-line memory.
One of purpose of the present invention is needn't patch memory.
In one embodiment, one storer is carried out initial testing (initial test), with the memory block (entry) of learning defective, one memory block takies the table of comparisons (entry occupiedmapping) and contains a plurality of fields (field), each field is to a memory block that should storer, mat one initial control device (initial control apparatus) is indicated (mark) one by one with the pairing field that takies the table of comparisons in the memory block of each defective, make it be considered to occupied, thereby this defective memory block is follow-up no longer is used, up to shutdown.
In another embodiment, an one standby working storage warehouse (backup registerspool) and a wrong memory block record/control device (error entry recorder/controller apparatus) are provided, behind the initial testing storer, mistake memory block record/control device misregistration memory block, and choose false from standby working storage warehouse for memory block (pseudoentry), each vacation is for corresponding wrong memory block, memory block, when follow-up access should the mistake memory block, will by guiding (redirect) again to this pairing vacation in mistake memory block for the memory block.
The present invention discloses a kind of method and device, with a kind of different viewpoint processing memory defective, particularly has the blemish in the wafer of in-line memory, this method is not used the fuse patch memory, the also not variation of processing memory size, but directly cover blemish, storer is seemed still as original complete appearance, for the user, and do not know the storer defectiveness.The position that the original test procedure of just having arranged was learnt blemish when this method was utilized system start-up, needn't introduce extra test procedure, also lack the program of repairing and testing again, therefore needn't spend the tediously long processing time, and use the simple storer that installs sign or recording defect, needn't increase complicated treatment circuit.Though the present invention may cause the size of storer to reduce, and makes wafer still can be used, and needn't abandon, and can dynamically get rid of blemish, makes the unlikely misoperation of system or works as machine.
Description of drawings
Fig. 1 is first embodiment device of the present invention;
Fig. 2 is an embodiment flow process utilizing the device operation of Fig. 1;
Fig. 3 is second embodiment device of the present invention;
Fig. 4 is an embodiment flow process utilizing the device operation of Fig. 3;
Fig. 5 is the embodiment flow process of a wrong storage control circuit.
Embodiment
Fig. 1 provides the first embodiment according to the invention schematic representation of apparatus, an in-line memory 100 contains N memory block, it is numbered 1 respectively, 2, ..., to N, as known, memory block takies the table of comparisons 200, and to be used to indicate in-line memory 100 be empty or occupied, one memory block takies quantity and in-line memory 100 big or small consistent of the field of the table of comparisons 200, the quantity of field is N in this embodiment, each field corresponding a memory block, for example first field 210 corresponding stored districts 110, second field 220 corresponding stored district 120, N field 230 corresponding last memory block 130, its corresponding memory block of the content representation of field is occupied or empty, as shown in FIG., the content of first field 210 is " 1 ", first memory block 100 of representing its correspondence is occupied, and the content of second field 220 and last field 230 is " 0 ", represents that its corresponding respectively memory block 120 and 130 all is empty.For do not produce possible obscure for the purpose of, other circuit with wafer of this in-line memory 100 do not show in the drawings.As computer system, when starting (start up), this system automatically tests in-line memory 100 in initialized program, in this program, can learn the position of the storer of inefficacy, present embodiment comprises an initial control device 300, its content only comprises a simple steering logic, realize with hardware or software, in build in the middle of the wafer with this in-line memory 100, or the use circumscribed, in initialized program, initial control device 300 will be indicated in the pairing field that takies the table of comparisons of blemish, as represented among the figure, first memory block 110 of in-line memory 100 was after tested for losing efficacy, therefore initial control device 300 writes " 1 " in its corresponding memory block takies first field 210 of the table of comparisons 200, represent the memory block 110 of its indication occupied, make that first memory block 110 of in-line memory 100 no longer is used in the follow-up running, that is, this memory block 110 when initialization with regard to crested., in initialize routine, write occupied sign as the suitable field that the memory block is taken the table of comparisons 200 aforementionedly, and blemish is hidden one by one by initial control device 300.This method is simple and quick, does not need to verify once more (verify), also needs complicated circuit exclusive disjunction.Though concealing memory defect will make effective size of in-line memory 100 reduce, but defective wafer is still worked unceasingly, and needn't be abandoned, and, the method is dynamically got rid of blemish, when starting each time, all obtain up-to-date blemish, avoid causing system's misoperation or working as machine because of defective afterwards.
Utilize the operating process of first embodiment device for example shown in Figure 2, in step S10, the power supply of system is unlocked or resets (reset), the wafer that has in-line memory 100 in this stage also is activated, as known, system will carry out test jobs to in-line memory 100 in initialize routine, this comprises three steps, in step S12, system writes a known data in the memory block, in step S14, reads data from this memory block then, then in step S16, the data that reads and the data that writes are compared, in step S18, if the two is identical for data that reads and the data that writes, represent that then tested memory block function is normal, in step S22,, then enter other program if all storeies are all finished test, otherwise get back to step S12, continue to test other storer; Otherwise, in step S18, if find the storer error, the two is different for data that promptly reads and the data that writes, and represents that then the memory block of this tested person is impaired, therefore enters among the step S20, this memory block is denoted as occupied, for example shown in Fig. 1, initial control device 300 writes " 1 " with first field 210 that the memory block takies the table of comparisons 200 to this process, is defective to represent its corresponding memory block 110.Abovementioned steps constantly repeats, and finishes up to all storeies are all tested.
As shown in fig. 1, the defective memory block 110 of in-line memory 100 is stored first field 210 that the district takies the table of comparisons 200 and is expressed as occupied, after this, memory block 110 promptly no longer is used, unless shutdown, therefore, this memory block 110 promptly is hidden in the process of system initialization.When system was activated each time, aforesaid process was promptly automatically carried out once, and therefore, this method is concealing memory defect dynamically, next time the memory block that is hidden after the system start-up and the memory block that this time is hidden may and incomplete same.In this embodiment, just so-so one though concealing memory defect can make that effective memory diminishes, there is the wafer of blemish to be abandoned, nor can causes system's misoperation because of blemish or work as machine.This method is concealing memory defect directly, thus effective size that needn't computing store, the address that also needn't transform storer.
Synoptic diagram according to second embodiment device of the present invention is presented among Fig. 3, as aforesaid first embodiment, this device comprises an in-line memory 100 and the memory block takies the table of comparisons 200, yet different with previous embodiment is, this device comprises a standby working storage warehouse 400 and one wrong memory block record/control device 500, standby working storage warehouse 400 is a plurality of vacations set for the memory block, and each vacation is big or small identical for the memory block of the size of memory block and an in-line memory 100.As aforesaid process, when system start-up, in-line memory 100 is automatically tested in initialized program, so position of learning the storer of inefficacy, the vacation of equal number is also selected for the memory block from a standby working storage warehouse 400 in address, wrong memory block in mistake memory block record/control device 500 record in-line memorys 100, each vacation is for corresponding wrong memory block, memory block, when follow-up access should the mistake memory block, to be directed to this pairing vacation in mistake memory block again for the memory block, for example shown in the figure, first memory block 110 of in-line memory 100 was after tested for losing efficacy, mistake memory block record/control device 500 is chosen this defective is represented in a vacation for memory block 410 memory block 110 from standby working storage warehouse 400, future, during the memory block 110 of each access defective, system is led this vacation again for memory block 410.Different with prior art, present embodiment does not use the fuse patch memory, therefore memory circuitry is not changed, the also program that needn't verify once more, but the memory block of defective has been hidden, the sensing of this defective memory block is redirected to false for the memory block, this method is still dynamically concealing memory defect, when power supply each time is unlocked or resets, this record and the process of arranging promptly are repeated once, and the vacation that standby next time working storage warehouse 400 is selected for the quantity of memory block and with the corresponding relation in the memory block of defective may be with this time different.In different embodiment, can use standby (backup) storer to replace aforesaid standby working storage warehouse 400.
Identical with first embodiment, mistake memory block record/control device 500 can use hardware or software to realize, and standby working storage warehouse 400 and wrong memory block record/control device 500 can in build in the middle of the wafer with this in-line memory 100, or use circumscribed.
Fig. 4 provides an operating process utilizing Fig. 3 device, in step S50, the power supply of system is unlocked or resets, the wafer that has in-line memory 100 in this stage also is activated, according to common program, system carries out test jobs to in-line memory 100 in initialize routine, in step S52, one group of test signal aspect is written in the in-line memory 100, then in step S54, read the data in the in-line memory 100, then in step S56, relatively read the signal aspect whether identical with the signal aspect that writes, in step S58, if the two is identical for data of reading and the data that writes, represent that then the function of tested in-line memory 100 is normal, therefore the program that enters other according to normal situation; Otherwise, represent that then this in-line memory 100 is impaired, therefore enter among the step S60, begin to carry out false configuration (configuration) for the memory block, at this moment, the memory block of mistake memory block record/control device 500 recording defects, choose vacation from standby working storage warehouse 400 and task the memory block of defective for memory block and branch, for example shown in Fig. 3, vacation is selected from standby working storage warehouse 400 for memory block 410, represent the impaired memory block 110 of in-line memory 100, after finishing configurator, following access to memory block 110 will be led to false for memory block 410, up to shutdown.This method concealing memory defect is also guided the access of memory block again, thus effective size that needn't computing store, address contents that also needn't operand store.
Fig. 5 provides the embodiment of a wrong storage control circuit, in this circuit, one configuration write signal WR connects N and lock, for simplicity, first and lock 511 and latter two and lock 512 and 513 only are shown among the figure, other relevant elements also together, the one wrong signal ERR_HAPPEN that takes place imports a counter 520, produce an output 0520 and offer N demoder 531, ..., 532 and 533, each demoder produces the lock that reaches that an output connects its correspondence, for example, the output 0531 of demoder _ 1 is delivered to and lock 511, and each and lock connect a localizer (pointer) 541, ..., 542 and 543, for example, reaching lock 511 is subjected to signal WR and 0531 to control and export 0511 and deliver to localizer _ 1, the latter's output is connected to a comparer 551, similarly, total N of comparer, each comparer connects a corresponding localizer respectively, and another input end of all comparers all connects general read-write memory block _ n-signal 600, the output of each comparer connects a computing logger 561, ..., 562 and 563, counting _ 1 that produces, ..., counting _ N-1, counting _ N delivers to and gathers computing logger 585, the output of all comparers also is connected to one or lock 570 simultaneously, to control a plurality of gates 591 to 592 and 593, counting 1-N cooperates a substrate address 580 to produce standby working storage or storage address 700.
Aforementioned two embodiment device are possible combined together, at this moment, in the middle of the memory block of defective, having some is directed to false for the memory block again in mode shown in Figure 3, other defective memory block is then hidden in mode shown in Figure 1, for example standby working storage warehouse 400 when exhausted, the direct crested in defective memory block that has more, and be not arranged to be directed to false for the memory block.
The above embodiment only is explanation technological thought of the present invention and characteristics, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when not limiting claim of the present invention with it, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim scope of the present invention.
Claims (10)
1. device of concealing memory defect dynamically, it is characterized in that: this storer contains plurality of memory, and this device comprises:
One memory block takies the table of comparisons, contains a plurality of fields, and each field is to one of them memory block that should plurality of memory; And
One initial control device takies in the field of defective memory block correspondence in the table of comparisons and writes a sign to be controlled at this memory block, and is occupied to represent this defective memory block.
2. the device of dynamically concealing memory defect as claimed in claim 1 is characterized in that: this field comprises the working storage of a bit.
3. method of concealing memory defect dynamically, it is characterized in that: this storer contains plurality of memory, and a memory block takies the table of comparisons and contains a plurality of fields, and each field is to one of them memory block that should plurality of memory, and this method comprises:
Test one of them memory block of this plurality of memory; And
When this tested memory block is impaired, in taking field corresponding in the table of comparisons, this memory block writes a sign, and occupied to represent this memory block.
4. the method for dynamically concealing memory defect as claimed in claim 3 is characterized in that: also be included in the preceding whole fields removings that this memory block taken the table of comparisons of test.
5. device of concealing memory defect dynamically, it is characterized in that: this storer contains plurality of memory, and this device comprises:
One standby working storage warehouse; And
One wrong memory block record/control device, with the address of recording defect memory block, and choose from this standby working storage warehouse a vacation for the memory block to should the defective memory block, will be directed to this vacation again for the access of this defective memory block for the memory block.
6. method of concealing memory defect dynamically, it is characterized in that: this storer contains plurality of memory, and this method comprises:
Test this plurality of memory;
The recording defect memory block; And
Choose falsely for the memory block from a standby working storage warehouse, each vacation is for a corresponding defective memory block, memory block, will be directed to the vacation of its correspondence again for the memory block for the access of defective memory block.
7. device of concealing memory defect dynamically is characterized in that: comprising:
One memory function means, for writing a sign, occupied to represent the defective memory block in this storer; And
One shielding function means write this sign to be controlled at this defective memory block after tested.
8. device of concealing memory defect dynamically is characterized in that: comprising:
One vacation is for the memory block, to the defective memory block in should storer; And
One guidance function means are pointed to this vacation for the memory block when being controlled at this defective memory block of access.
9. the device of dynamically concealing memory defect as claimed in claim 8 is characterized in that: this vacation is selected from a standby working storage warehouse for the memory block.
10. the device of dynamically concealing memory defect as claimed in claim 8 is characterized in that: this vacation is selected from a shelf storage for the memory block.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021024960A CN100382202C (en) | 2002-01-23 | 2002-01-23 | Method and device for dynamically hiding memory defect |
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| CNB021024960A CN100382202C (en) | 2002-01-23 | 2002-01-23 | Method and device for dynamically hiding memory defect |
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| CN 200610074997 Division CN1838329A (en) | 2002-01-23 | 2002-01-23 | Method and apparatus for dynamically concealing memory defect |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101086899B (en) * | 2006-06-09 | 2010-06-02 | 台湾积体电路制造股份有限公司 | Method and system for improving reliability of memory device |
| CN106710632A (en) * | 2015-11-17 | 2017-05-24 | 华邦电子股份有限公司 | Memory apparatus |
| WO2021179600A1 (en) * | 2020-03-11 | 2021-09-16 | 长鑫存储技术有限公司 | Memory testing method and related device |
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| CN1048624A (en) * | 1989-07-07 | 1991-01-16 | 约翰弗兰克制造公司 | The method and apparatus of ROM (read-only memory) fault diagnosis |
| JPH0428061A (en) * | 1990-05-24 | 1992-01-30 | Matsushita Electric Ind Co Ltd | Information recording medium and information recording and reproducing device |
| US5495445A (en) * | 1994-05-31 | 1996-02-27 | Townsend And Townsend And Crew | Redundancy scheme for memory circuits |
| KR0177740B1 (en) * | 1994-11-17 | 1999-04-15 | 김광호 | Redundancy circuit and its method for semiconductor memory device |
| US5841784A (en) * | 1996-04-02 | 1998-11-24 | Stmicroelectronics, Inc. | Testing and repair of embedded memory |
| CN1185618A (en) * | 1996-12-19 | 1998-06-24 | 联华电子股份有限公司 | Cauculating method of decoder compensating defect of storage |
| US6192486B1 (en) * | 1998-08-13 | 2001-02-20 | International Business Machines Corporation | Memory defect steering circuit |
| US6067262A (en) * | 1998-12-11 | 2000-05-23 | Lsi Logic Corporation | Redundancy analysis for embedded memories with built-in self test and built-in self repair |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101086899B (en) * | 2006-06-09 | 2010-06-02 | 台湾积体电路制造股份有限公司 | Method and system for improving reliability of memory device |
| CN106710632A (en) * | 2015-11-17 | 2017-05-24 | 华邦电子股份有限公司 | Memory apparatus |
| CN106710632B (en) * | 2015-11-17 | 2020-01-07 | 华邦电子股份有限公司 | Memory device |
| WO2021179600A1 (en) * | 2020-03-11 | 2021-09-16 | 长鑫存储技术有限公司 | Memory testing method and related device |
| US11854642B2 (en) | 2020-03-11 | 2023-12-26 | Changxin Memory Technologies, Inc. | Memory test methods and related devices |
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