CN1434385A - Microcomputer system reading data from secondary storage medium and writing data into primary storage medium - Google Patents
Microcomputer system reading data from secondary storage medium and writing data into primary storage medium Download PDFInfo
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- CN1434385A CN1434385A CN03102963A CN03102963A CN1434385A CN 1434385 A CN1434385 A CN 1434385A CN 03102963 A CN03102963 A CN 03102963A CN 03102963 A CN03102963 A CN 03102963A CN 1434385 A CN1434385 A CN 1434385A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/067—Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
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- Software Systems (AREA)
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- Microcomputers (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Read Only Memory (AREA)
Abstract
When a serial external interface 10 receives a port address from a host device 2, a CPU 21 reads the data of all device addresses corresponding to the port address from a secondary storage medium 22, and writes the data in a primary storage medium 14. When receiving the device address from the host device 2, the serial external interface 10 transmits the data corresponding to the device address stored in the primary storage medium 14 to the host device 2. Therefore, the data can be transmitted to the host device 2 in a short time after the least significant address is received.
Description
Technical field
The present invention relates to a kind of according to main equipment requirement and read microsystem with output data from storage medium, particularly a kind of can be to the microsystem of main equipment high speed output data and the method for data access thereof.
Background technology
Developing in recent years various according to main equipment requirement and read system with output data from storage medium, can enumerate employing employed MDIO (Medium Dependent Input/Output: the I/O that medium the is relevant) system of interface in LAN (LAN (Local Area Network)) as an example.
Fig. 1 is the figure that transmits in order to data between explanation main equipment and the MDIO interface.Main equipment is connected with a plurality of systems that have the MDIO interface (the following system that simply is called), gives different port addresss respectively to a plurality of systems.The storage medium that is comprised in the system is divided into a plurality of zones of about dozens of word in addition, gives different device addresses respectively to each zone.By the transmission of port address and device address, main equipment can selective system and system in the zone of the storage medium that comprised, and in desired regional access.
From system's sense data, then main equipment sends command code 101, port address 102 and the device address 103 that the expression data are read to system as main equipment.Each system reference port address 102 judges whether it is access to native system.If to the access of native system,,, and send to main equipment from regional sensed data 105 corresponding to the storage medium of its device address 103 then with reference to device address 103.Behind the main equipment transmitting apparatus address 103, must obtain data 105 through before the turnaround time 104.This turnaround time 104 is defined as two cycles usually.If what for example use is the clock of 2MHz, then system must turn back to main equipment with data 105 in 1 μ s.
In addition, as main equipment with the storage medium in the data writing system, then main equipment sends expression the data command code 101, port address 102, device address 103 and the data 105 that write successively, the zone corresponding with device address 103 that the system corresponding with port address 102 writes storage medium with data 105.
As mentioned above, behind the main equipment transmitting apparatus address 103, system must turn back to main equipment with data 105 in the turnaround time 104.Therefore intrasystem microcomputer owing to having little time from the storage medium sense data and sending to main equipment, therefore exists and must adopt special hardware to finish the problem of this work after receiving equipment address 103.
Summary of the invention
The purpose of this invention is to provide a kind of basis from the microsystem of the requirement energy high-speed transferring data of main equipment sense data and the method for data access thereof.
Another object of the present invention provides a kind of microsystem that can improve system's versatility.
Microsystem according to one aspect of the invention comprises: a storage medium; Capacity is greater than the secondary storage medium of a storage medium, and carry out the interface of data transmit-receive between the outside, and the moment that receives bit address at interface from the outside from the secondary storage medium read corresponding on bit address data and write the processor of a storage medium; Receive the moment of bit address down from the outside at interface, the data corresponding to following bit address that store in the storage medium are sent to the outside.
Because the data of the following bit address that interface stores bit address under the outside receives constantly will be corresponding to a storage medium send to the outside, therefore receive descend bit address most after, can in the of short duration time, send data to the outside.
Microsystem according to another aspect of the present invention comprises: a storage medium, and carry out the interface of data transmit-receive and processor between the outside; Interface the moment processor that receives bit address from the outside read from the secondary storage medium that is arranged on the microsystem outside corresponding on bit address data and write storage medium one time, the data of the following bit address that interface stores the moment that receives following bit address from the outside will be corresponding to a storage medium send to the outside.
Because interface sends to the outside in the data that receive the following bit address that following bit address stores constantly will be corresponding to a storage medium from the outside, therefore receive descend bit address most after, can in the of short duration time, send data to the outside.In addition, because the secondary storage medium is arranged on the outside of microsystem, so can determine the capacity of secondary storage medium and access speed etc. according to system, this makes the versatility that improves microsystem become possibility.
Description of drawings
Fig. 1 is the figure that transmits in order to data between explanation main equipment and the MDIO interface.
Fig. 2 is the block diagram of the schematic configuration of microsystem in the expression embodiments of the invention 1.
Fig. 3 is the block diagram of the schematic configuration of the series peripheral interface 10 in the expression microsystem 1.
Fig. 4 is the process flow diagram in order to microsystem handling procedure in the explanation embodiment of the invention 1.
Fig. 5 is the block diagram of the schematic configuration of microsystem in the expression embodiments of the invention 2.
Fig. 6 is the block diagram of the schematic configuration of microsystem in the expression embodiments of the invention 3.
Fig. 7 is the block diagram of the schematic configuration of microsystem in the expression embodiments of the invention 4.
Embodiment
Fig. 2 is the block diagram of the schematic configuration of microsystem in the expression embodiments of the invention 1.This microsystem 1 comprises: and carry out the series peripheral interface 10 of serial transceive data between the series peripheral interface 20 in the main equipment 2, control the CPU (central processing unit) 21 of whole microsystem 1, and jumbo secondary storage medium 22.And series peripheral interface 10 comprises can temporarily store a storage medium 14 data, high access speed of reading from secondary storage medium 22.Dotted line among Fig. 2 is represented each information flow shown in Figure 1 in addition, will be described in detail afterwards.
Static RAM) storage medium 14 is by low capacity register that can zero access, SRAM (StaticRandom Access Memory: formation such as.
Dynamic RAM), volatile memory such as SRAM and mask ROM (Read OnlyMemory: ROM (read-only memory)), nonvolatile memory such as flash memory constitutes secondary storage medium 22 is by DRAM (Dynamic Random Access Memory:.When using rewritable nonvolatile memory such as flash memory, owing to when accidents such as generation instantaneous power-off, also can preserve data, simultaneously when disconnecting, power supply also can preserve data, therefore can rewrite suitable data and be updated to latest data, thereby when recovering, can restart with up-to-date state.
And in the occasion of using volatile memory such as DRAM, SRAM, compare with nonvolatile memory, because the energy zero access, so can carry out at a high speed transmitting from the data of 22 to storage mediums 14 of secondary storage medium, this is effective for the high interface of clock frequency.
Fig. 3 is the block diagram of the schematic configuration of the series peripheral interface 10 in the expression microsystem 1.Series peripheral interface 10 comprises: will be transformed to parallel data from the serial data that the series peripheral interfaces in the main equipment 2 20 receive and the data conversion that will read from a storage medium 14 is serial data and I/O (I/O) interface 11 that sends to the series peripheral interface 20 in the main equipment 2, to the port address demoder 12 of decoding from the port address of I/O interface 11 receptions, to the device address demoder 13 of decoding from the device address of I/O interface 11 receptions, and a storage medium 14.
In a single day I/O interface 11 receives the command code 101 of autonomous device 2, outputs to CPU 21 just with command code 101 decodings, and with decoded result.In a single day I/O interface 11 receives the port address 102 of autonomous device 2 in addition, just by internal bus 16 port address 102 is outputed to port address demoder 12.Port address demoder 12 is with port address 102 decodings, and decoded result outputs to CPU 21 by internal bus 17.In addition, in a single day I/O interface 11 receives the device address 103 of autonomous device 2, just by internal bus 16 device address 103 is outputed to device address demoder 13.Device address demoder 13 is decoded device address 103, and decoded result is outputed to storage medium 14 one time by internal bus 17.
Fig. 4 is the process flow diagram in order to microsystem handling procedure in the explanation embodiment of the invention 1.Handling procedure during port address demoder 12 sense datas of this flowcharting main equipment 2 in microsystem 1.In a single day I/O interface 11 receives the command code 101 of expression from main equipment 2 sense datas, just receives port address 102 thereafter, and it is outputed to port address demoder 12 (S1).
As Fig. 2 1. shown in, port address 102 decodings that port address demoder 12 will receive from I/O interface 11, and this decoded result outputed to CPU 21.Whether the decoded result that 21 couples of CPU receive from port address demoder 12 is consistent with secondary storage medium 22 and judges (S2).(S2 No) is consistent, and then returns step S1, waits for designated port address 102 once more if decoded result is not with secondary storage medium 22.
(the S2 if decoded result is consistent with secondary storage medium 22, Yes), then as Fig. 2 2. shown in, CPU 21 reads data corresponding to all devices address of port address 102 from secondary storage medium 22, writes a storage medium 14 (S3) by internal bus 17.If I/O interface 11 then receives device address 103, then device address 103 is outputed to device address demoder 13 (S4).Device address demoder 13 is device address 103 decoding, and this decoded result is outputed to storage medium 14 one time, as Fig. 2 3. shown in, make data output to a storage medium 14 (S5) corresponding to device address 103.The data conversion that I/O interface 11 will receive from a storage medium 14 is a serial data, sends to main equipment 2 by universal serial bus 15.
In addition, in the above description, port address demoder 12 is port address 102 decoding, and CPU 21 reads data corresponding to all devices address of port address 102 according to this decoded result from secondary storage medium 22, and these data are write storage medium 14 one time; But also can be like this, when port address demoder 12 is with port address 102 decodings, device address demoder 13 is with the upper address decoder of device address 103, CPU 21 is according to the decoded result of the last bit address of port address 102 and device address 103, read all data corresponding from secondary storage medium 22, and these data are write storage medium 14 one time with the last bit address of port address 102 and device address 103.In this occasion, device address demoder 13 outputs to storage medium 14 one time with the decoded result of the following bit address of device address 103, and makes the data output that storage medium 14 will be corresponding with the following bit address of device address 103.
In addition, though in the present embodiment the situation of two-level address structure with port address 102 and device address 103 is illustrated, can realize microsystem too for situation with address structure more than three grades.By increasing the hierarchy of address, can reduce the capacity of a storage medium 14, thereby can reduce power consumption and circuit scale like this.
As mentioned above, according to the microsystem in the present embodiment, since determined secondary storage medium 22 on moment of bit address (port address 102), read the data of corresponding with it all devices address and write storage medium 14 one time from secondary storage medium 22, and in moment of the following bit address of having determined secondary storage medium 22 (device address 103), read corresponding with it data and send to main equipment from a storage medium 14, therefore can receive descend bit address most after in about one-period, the data of correspondence are sent to main equipment 2.Even, also can be in the turnaround time data designated be turned back to main equipment 2 so adopt CPU 21 to carry out software processes.
And, can constitute by a slice chip owing to comprise the microsystem of CPU, therefore can realize interface at an easy rate.In addition since microsystem in comprise CPU, so control CPU other peripheral loop also can in be contained in the same chip, thereby can design extendibility and the good system of flexibility.By changing the performed program of CPU, just can realize adapting to the interface of all size in addition.
Fig. 5 is the block diagram of the schematic configuration of microsystem in the expression embodiments of the invention 2.This microsystem 30 comprises: and carry out the parallel external interface 23 of data transmit-receive in the main equipment 40 between the parallel external interfaces 41 with parallel mode, control the CPU 21 of whole microsystem 30, and jumbo secondary storage medium 22.And parallel external interface 23 comprises can temporarily store the data of reading from secondary storage medium 22, and has a storage medium 14 of zero access speed.
In a single day parallel external interface 23 receives the command code 101 of expression from main equipment 40 sense datas, just receives port address 102 thereafter and decodes.So, as Fig. 5 1. shown in, this decoded results is output to CPU 21.If the decoded result that receives from parallel external interface 23 is consistent with secondary storage medium 22, then as Fig. 5 2. shown in, CPU 21 reads data corresponding to all devices address of port address 102 from secondary storage medium 22, and writes storage medium 14 one time.
Continue receiving equipment addresses 103 as parallel external interface 23, output to storage medium 14 one time then with device address 103 decodings, and with this decoded result, as Fig. 5 3. shown in, allow a storage medium 14 will be corresponding to the data output of device address 103.The data that parallel external interface 23 will receive from a storage medium 14 send to main equipment 40 with the form of parallel data.
As mentioned above,, transmit, therefore in embodiment 1, the illustrated effect, can also reduce data and transmit the required time owing to can between microsystem 30 and main equipment 40, carry out data concurrently according to microsystem in the present embodiment.
Fig. 6 is the block diagram of the schematic configuration of microsystem in the expression embodiments of the invention 3.This microsystem 50 comprises: and carry out the series peripheral interface 10 of serial transceive data between the series peripheral interface 20 in the main equipment 2, and the CPU 21 that controls whole microsystem 50.And series peripheral interface 10 comprises can temporarily store a storage medium 14 data, that have zero access speed of reading from the secondary storage medium 28 that is arranged on microsystem 50 outsides.
Microsystem 50 is compared with microsystem among the embodiment 1 shown in Figure 2 in the present embodiment, and difference only is that secondary storage medium 28 is arranged on the outside of microsystem 50.So no longer elaborate with regard to the 26S Proteasome Structure and Function that repeats.
The secondary storage medium 28 that is arranged on microsystem 50 outsides can adopt volatile memory such as DRAM, SRAM, and nonvolatile memory such as mask ROM, flash memory.In the occasion of using rewritable nonvolatile memories such as flash memory, owing to when accidents such as generation instantaneous power-off, also can preserve data, can be up-to-date data therefore by rewriteeing suitable Data Update, when recovering, restart with up-to-date state.
And in the occasion of using volatile memory such as DRAM, SRAM, compare with nonvolatile memory, because the energy zero access so can carry out at a high speed transmitting from the data of 28 to storage mediums 14 of secondary storage medium, is effective for the high interface of clock frequency.
In a single day series peripheral interface 10 receives the command code 101 of expression from main equipment 2 sense datas, just receives port address 102 thereafter, and decodes.And as Fig. 6 1. shown in, this decoded result is exported to CPU 21.If the decoded result that receives from series peripheral interface 10 is consistent with secondary storage medium 28, then as Fig. 6 2. shown in, CPU 21 reads data corresponding to all devices address of port address 102 from being arranged on outside secondary storage medium 28, and writes storage medium 14 one time.
Then receive device address 103 as series peripheral interface 10, then with device address 103 decoding, this decoded result is output to storage medium 14 one time, and as Fig. 6 3. shown in, make a storage medium 14 will be corresponding to the data output of device address 103.The data conversion that series peripheral interface 10 will receive from a storage medium 14 is to send to main equipment 2 after the serial data.
As mentioned above, according to microsystem in the present embodiment, because secondary storage medium 28 is arranged on the outside of microsystem 50, in embodiment 1 the illustrated effect, also has such effect, promptly storage medium can be connected, thereby the versatility of microsystem can be improved with any capacity and access speed.
Fig. 7 is the block diagram of the schematic configuration of microsystem in the expression embodiments of the invention 4.This microsystem 60 comprises: and carry out the parallel external interface 23 of data transmit-receive and the CPU21 that controls whole microsystem 60 between the parallel external interface 41 in the main equipment 40 concurrently.And parallel external interface 23 comprises can temporarily store a storage medium 14 data, that have high access speed of reading from the secondary storage medium 28 that is arranged on microsystem 60 outsides.
Microsystem 60 is compared with microsystem 50 among the embodiment 3 shown in Figure 6 in the present embodiment, and difference only is parallel the carrying out that data transmit between microsystem 60 and the main equipment 40.Therefore, no longer elaborate with regard to the 26S Proteasome Structure and Function that repeats.
In a single day parallel external interface 23 receives the command code 101 of expression from main equipment 40 sense datas, just receives port address 102 thereafter.As Fig. 7 1. shown in, this decoded results is output to CPU 21.If the decoded result that receives from parallel external interface 23 is consistent with secondary storage medium 28, then as Fig. 7 2. shown in, CPU 21 reads data corresponding to all devices address of port address 102 from being arranged on outside secondary storage medium 28, and writes storage medium 14 one time.
Then receive device address 103 as parallel external interface 23, then with device address 103 decodings, this decoded result is exported to storage medium 14 one time, and as Fig. 7 3. shown in, allow a storage medium 14 will be corresponding to the data output of device address 103.The data that parallel external interface 23 will receive from a storage medium 14 send to main equipment 40 with the form of parallel data.
As mentioned above,, in embodiment 3, the illustrated effect, carry out, can also reduce data and transmit the required time because the data between microsystem 60 and the main equipment 40 transmit to walk abreast according to microsystem in the present embodiment.
Claims (12)
1. microsystem, comprising:
A storage medium,
Capacity is greater than the secondary storage medium of a storage medium,
And carry out the interface of data transmit-receive between the outside, and
Receive moment of bit address from the outside at described interface, read corresponding to described from described secondary storage medium and go up the data of bit address and it is write the processor of a described storage medium;
Described interface is receiving from the outside the down moment of bit address, and the data corresponding with the described bit address down that stores in the described storage medium are sent to the outside.
2. microsystem as claimed in claim 1 is characterized in that: carry out data transmit-receive between described interface and the outside serially.
3. microsystem as claimed in claim 1 is characterized in that: carry out data transmit-receive between described interface and the outside concurrently.
4. microsystem as claimed in claim 1 is characterized in that: described interface comprises decodes and decoded result is exported to the port address demoder of described processor the port address that receives from the outside, and
Device address decoding that will receive and the device address demoder of decoded result being exported to a described storage medium from the outside.
5. microsystem as claimed in claim 1 is characterized in that: a described storage medium is made of the low capacity register of energy zero access,
Described secondary storage medium is made of the jumbo nonvolatile memory that access speed is lower than a described storage medium.
6. microsystem as claimed in claim 1 is characterized in that: a described storage medium is made of the low capacity register of energy zero access,
Described secondary storage medium is made of the jumbo volatile memory that access speed is lower than a described storage medium.
7. microsystem, comprising:
A storage medium,
And carry out the interface of data transmit-receive between the outside, and
Processor;
Described interface is in the moment that receives bit address from the outside, and described processor is read corresponding to described from the secondary storage medium that is arranged on described microsystem outside and gone up the data of bit address and it is write a described storage medium,
In the moment of described interface bit address under receiving, the data corresponding with the described bit address down that stores in the described storage medium are sent to the outside from the outside.
8. microsystem as claimed in claim 7 is characterized in that: carry out data transmit-receive between described interface and the outside serially.
9. microsystem as claimed in claim 7 is characterized in that: carry out data transmit-receive between described interface and the outside concurrently.
10. microsystem as claimed in claim 7 is characterized in that: described interface comprises port address decoding that will receive from the outside and decoded result exported to the port address demoder of described processor, and
Device address decoding that will receive and the device address demoder of decoded result being exported to a described storage medium from the outside.
11. microsystem as claimed in claim 7 is characterized in that: a described storage medium is made of the low capacity register of energy zero access,
Described secondary storage medium is made of the jumbo nonvolatile memory that access speed is lower than a described storage medium.
12. microsystem as claimed in claim 7 is characterized in that: a described storage medium is made of the low capacity register of energy zero access,
Described secondary storage medium is made of the jumbo volatile memory that access speed is lower than a described storage medium.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12977/2002 | 2002-01-22 | ||
| JP2002012977A JP2003216343A (en) | 2002-01-22 | 2002-01-22 | Microcomputer system and its data access method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1434385A true CN1434385A (en) | 2003-08-06 |
Family
ID=19191773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN03102963A Pending CN1434385A (en) | 2002-01-22 | 2003-01-22 | Microcomputer system reading data from secondary storage medium and writing data into primary storage medium |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6813647B2 (en) |
| JP (1) | JP2003216343A (en) |
| KR (1) | KR20030063226A (en) |
| CN (1) | CN1434385A (en) |
| DE (1) | DE10301933A1 (en) |
| TW (1) | TW589540B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003308288A (en) * | 2002-04-18 | 2003-10-31 | Mitsubishi Electric Corp | Microcomputer system |
| CN100440880C (en) * | 2003-09-16 | 2008-12-03 | 华为技术有限公司 | Physical address conversion device and conversion method |
| US7304950B2 (en) * | 2003-12-15 | 2007-12-04 | Finisar Corporation | Two-wire interface having dynamically adjustable data fields depending on operation code |
| KR100675850B1 (en) * | 2005-10-12 | 2007-02-02 | 삼성전자주식회사 | System for axi compatible network on chip |
| US7376780B2 (en) * | 2005-10-31 | 2008-05-20 | Lsi Corporation | Protocol converter to access AHB slave devices using the MDIO protocol |
| US9201790B2 (en) * | 2007-10-09 | 2015-12-01 | Seagate Technology Llc | System and method of matching data rates |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5754540A (en) * | 1995-07-18 | 1998-05-19 | Macronix International Co., Ltd. | Expandable integrated circuit multiport repeater controller with multiple media independent interfaces and mixed media connections |
| US5920698A (en) * | 1997-01-06 | 1999-07-06 | Digital Equipment Corporation | Automatic detection of a similar device at the other end of a wire in a computer network |
| US6052751A (en) * | 1997-02-14 | 2000-04-18 | Advanced Micro Devices, I Nc. | Method and apparatus for changing the number of access slots into a memory |
| EP1150213B1 (en) * | 2000-04-28 | 2012-01-25 | TELEFONAKTIEBOLAGET LM ERICSSON (publ) | Data processing system and method |
| US6701406B1 (en) * | 2000-11-17 | 2004-03-02 | Advanced Micro Devices, Inc. | PCI and MII compatible home phoneline networking alliance (HPNA) interface device |
-
2002
- 2002-01-22 JP JP2002012977A patent/JP2003216343A/en not_active Withdrawn
- 2002-11-07 TW TW091132751A patent/TW589540B/en not_active IP Right Cessation
- 2002-12-24 US US10/327,048 patent/US6813647B2/en not_active Expired - Fee Related
-
2003
- 2003-01-20 DE DE10301933A patent/DE10301933A1/en not_active Withdrawn
- 2003-01-21 KR KR10-2003-0003966A patent/KR20030063226A/en not_active Application Discontinuation
- 2003-01-22 CN CN03102963A patent/CN1434385A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| TW200302416A (en) | 2003-08-01 |
| JP2003216343A (en) | 2003-07-31 |
| TW589540B (en) | 2004-06-01 |
| US20030140187A1 (en) | 2003-07-24 |
| DE10301933A1 (en) | 2003-07-31 |
| KR20030063226A (en) | 2003-07-28 |
| US6813647B2 (en) | 2004-11-02 |
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