CN1433227A - Digital PLL regulating crystal oscillator frequency and its regulation method - Google Patents
Digital PLL regulating crystal oscillator frequency and its regulation method Download PDFInfo
- Publication number
- CN1433227A CN1433227A CN 02110538 CN02110538A CN1433227A CN 1433227 A CN1433227 A CN 1433227A CN 02110538 CN02110538 CN 02110538 CN 02110538 A CN02110538 A CN 02110538A CN 1433227 A CN1433227 A CN 1433227A
- Authority
- CN
- China
- Prior art keywords
- phase
- error data
- phase error
- fifo2
- crystal oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A digital phase-locked ring to regulate frequency of crystal oscillator includes LIU, PD, DIV, DLF and OCXO, of which DLF consists of two first-in and first-out shift counters of FIFO, and FIFO2, accumulator ACC, mutiplying-dividing circuit and D/A converter. The method of realization for it is as follows: 1) phase error data sampling, 2) phase error data to be formed to be one-dimensional digital set {delta phi}m and to input them into FIFO, and FIFO2 as well as to get rid of a phase error data being sampled at the most early time, 3) accumulating phase error data delta phi and then to carry on averaging to calculate out the corresponding voltage controlled voltage value and 4) to regulate OCXO output frequency through D/A.
Description
Technical field
It is stable that the present invention relates to electro coupled oscillator, especially relate to a kind of lock to the ring.
Background technology
Along with the extensive use of various communication systems on public telecommunication network, cause network size increasing, network environment also becomes increasingly complex, especially for various edge networks such as wired access network and wireless access networks, network environment is more complicated, such as the transmission network of being relied on SDH (Synchronous Digital Hierarchy is arranged, synchronous digital hierarchy), PDH (Pseudo-synchronous Digital Hierarchy, plesiochronous digital system), digital microwave even SDH/PDH hybrid network.On the other hand, at present transmission network is based on SDH basically, although SDH has its exclusive broadband, self-healing ability is strong and advantage such as strong network management ability, it is applied in the edge network is a subject matter synchronously.Generally speaking, because the pointer adjustment can be dealt with the frequency difference between the network element,, two kinds of deterioration mode of operation (asynchronous) and non-deterioration mode of operations (synchronously) are arranged promptly so the SDH net might not need to be operated under the method for synchronization.But in order to dock and carry the needs of multiple business with PDH, SDH still needs to be operated in synchronous environment (being non-deterioration mode), otherwise a large amount of pointer adjustment can make 2M branch service and the serious deterioration of timing quality; In addition, in order to distribute and to transmit regularly, SDH also needs to be operated under the method for synchronization.Even SDH is operated in the synchronous environment, because the noise process of jitter accumulation and equipment self, the pointer adjustment still can take place, and especially after NE quantity surpassed certain limit value, pointer adjustment meeting was risen rapidly.For example, at N website away from the Source Site, its shake/floating is J=(N)
1/2J
0, J wherein
0Be the shake of Source Site/float.Therefore, when ITU (International Telecommunication Union, International Telecommunications Union) regulation SDH is used for timing allocation and transmission, can only use the signal of STM-N grade, and can not use the 2M tributary signal of SDH.If under special circumstances, the 2M tributary signal that needs to adopt SDH then must carry out " more regularly " to this tributary signal in the SDH side and handle as timing reference.
In actual applications, the BTS (BaseTransceiver Station, base transceiver station) of GSM (Global System of Mobile Communication) network belongs to needs to adopt the special circumstances of the 2M tributary signal of SDH as timing reference.In this case, there are two SDH/PDH borders in whole network.Usually, regularly be to distribute to BTS from MSC (Mobile Switching Center, mobile switching centre), be no problem synchronously therefore at BSC (Base StationControl, base station controller) side SDH and BSC.And in the BTS side, BTS just need use the 2M clock that recovers from the 2M branch road as synchronous refernce clocks, makes the BTS of whole network keep to guarantee the sub-district performance of handoffs, promptly switching not call drop synchronously.But, the 2M branch road great majority of present existing transmission network are not handled through " more regularly ", so, if BTS adopts regularly the 2M tributary signal of quality deterioration as timing reference, just require the BTS equipment clock to have very strong shake/float tolerance and smoothing capability, otherwise not only can make BTS net synchronization capability deterioration, and the performance on the wireless mouth of meeting deterioration, finally tend to cause GSM network performance deterioration, as phenomenons such as call drop is serious occur.
The Telecommunication Network Element equipment clock is used in comparatively abominable network environment for adapting to, and traditional method is to select integration time constant suitable and long loop filter with tolerance and level and smooth big shake/float.But, the selection of the integration time constant of loop filter also should be according to designed clock grade, be selected OCXO (Oven Control CrystalOscillator, the thermostatic control crystal oscillator) parameter is decided, for example, low-grade clock just should not selected oversize integration time constant, because DPLL is (Digital Phase Locked Loop, digital phase-locked loop) twice adjusting play, be to be in a kind of " the near maintenance " state in the time of integration, and the maintenance precision and time correlation of clock, promptly with temperature stability, voltage stability, load stability is relevant with ageing properties, so low-grade clock, the maintenance precision that its correspondence is lower, if select long integration time constant, certainly will make the each adjusting range of clock bigger, cause artificial " floating ".Usually, the integration time constant of the loop filter of network element device clock is 100ms～100s, and special-purpose synchronizer is more than the 100s as SSU (Synchronization Supply Unit, synchronization supply unit), even reaches 10000s.Shake/the Energy distribution that floats of considering the 2M branch road of SDH transmission network generally concentrates on 0.01Hz～10Hz low frequency region, the shake that obvious integration time constant at the common 100ms～100s that adopts of network element device clock grade is an effectively filtering 2M branch road/float.
In sum, have the problem of this two aspect in the prior art, on the one hand: abominable 2M branch road regularly quality requirement BTS equipment clock should have long loop filter integration time constant, on the other hand: cause bigger instantaneous frequency rate of change for avoiding each adjustment of clock, require the network element device clock to have the short loop filter integration time constant that adapts with its OCXO grade again, obviously this two aspect is a contradiction.So network element device clock tolerance at present and level and smooth big shake/float are limited in one's ability, can not adapt to the regularly comparatively abominable network environment of quality.
Summary of the invention
The purpose of this invention is to provide a kind of overlength loop filter integration time constant that both can realize, again the DPLL that OCXO can dynamically be adjusted, i.e. sliding window DPLL.It can be tolerated on the one hand and level and smooth big shake/float, improve the online survival ability of network element device clock; OCXO that on the other hand needn't high stable is to adapt to overlength loop filter integration time constant.
In order to solve the problems of the technologies described above, sliding window digital phase-locked loop of the present invention, it comprises LIU (Line InterfaceUnit, line interface unit), PD (Phase Detector, phase discriminator), DIV frequency divider, DLF (Digital Loop Filter, digital loop filters) and OCXO (Oven Control Crystal Oscillator, the thermostatic control crystal oscillator), described DLF includes FIFO1 (first in first out shift counter) and FIFO2, accumulator ACC, multiplication and division circuit and D/A converter.
The implementation method of described DLF may further comprise the steps: (1) obtains the phase error data ΔΦ by the PD phase discriminator, finishes the phase error data sampling; (2) the above-mentioned phase error data that obtains is joined the one-dimension array of forming by the phase error data sampling { ΔΦ }
mIn, be input among FIFO1 and the FIFO2, and remove phase error data of sampling at first in the array; And if FIFO2 less than the time, phase data is only imported and is not exported; Or when if FIFO2 is full, the phase data in the FIFO2 is poured FIFO1 earlier into, returns step (1) then; (3) described ACC reads the phase error data ΔΦ immediately from described FIFO1, and adds up, and by a multiplication and division circuit phase data is averaged then, and calculates corresponding voltage-controlled magnitude of voltage according to loop gain; (4) regulate the output frequency of OCXO by D/A.
The each output time of described PD be 250 milliseconds to the several seconds, described array { ΔΦ }
mLength and the ratio of the each output time of PD be 1000: 1, the degree of depth of described FIFO is corresponding with the length of described array.
Compared with prior art, the invention has the beneficial effects as follows: its can be tolerated on the one hand and level and smooth big shake/float, improve the online survival ability of network element device clock; OCXO that on the other hand needn't high stable is to adapt to overlength loop filter integration time constant.
Description of drawings
Fig. 1 is a sliding window DPLL workflow block diagram of the present invention;
Fig. 2 is a sliding window DPLL electrical schematic diagram of the present invention;
Fig. 3 is a sliding window DPLL structure key diagram of the present invention;
Fig. 4 is a sliding window DPLL implementation method flow chart of the present invention;
Fig. 5 is the timing diagram of the specific embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is done and to describe in further detail:
The basic thought of sliding window DPLL of the present invention design be big time of integration window with less step value to front slide, promptly only refresh the sub-fraction data in the integration time interval, this part data is with updated most of data sum-average arithmetic.Hardware implementation method and software implementation method are sliding window DPLL hardware circuit implementation and software algorithm flow process.The annexation of each functional block of sliding window DPLL and signal flow to.
Fig. 1 shows a kind of sliding window digital phase-locked loop that is used for communication network of the present invention, and it comprises LIU line interface unit, PD phase discriminator, DIV frequency divider, DLF digital loop filters and thermostatic control crystal oscillator OCXO; Wherein LIU is reference clock (REF) input interface, mainly finishes reference clock and recovers and frequency division; The reference clock that PD mainly obtains by frequency divider DIV frequency division OCXO and local clock carry out than mutually, thereby obtain the phase demodulation value; DLF carries out integration with the shake of filtering reference clock/float to identified result, thereby obtains OCXO control voltage.
Fig. 2 shows DLF of the present invention and includes first in first out shift counter FIFO1 and FIFO2, accumulator ACC, multiplication and division circuit and D/A converter; PD exports the phase error data ΔΦ of one 4 second after average per 4 seconds, the phase error data that phase discriminator PD obtains FIFO less than, when promptly catching soon, be input to FIFO1 and FIFO2 simultaneously.Accumulator ACC reads the phase error data ΔΦ immediately from FIFO1, and adds up.By a multiplication and division circuit phase data is averaged at last, and calculate voltage-controlled voltage V_CTL digital value according to loop gain KgG.For FIFO2, less than the time phase data only import and do not export.When FIFO2 was full, the phase data in the FIFO2 was poured FIFO1 earlier into, read in a new phase error data by PD output then, read all data in the FIFO1 immediately and was input to ACC and FIFO2 simultaneously.ACC obtains the V_CTL digital value at last by the multiplication and division circuit after phase data is added up.Data in the FIFO2 are refunded FIFO1 again, and repeat aforesaid operations, so move in circles.The each cycling of FIFO1 and FIFO2 all refreshes a phase error data, and obtains a new V_CTL digital value by all data in the FIFO1.
The implementation method that described DLF has been shown among Fig. 3 and Fig. 4 is as follows: (1) obtains the phase error data ΔΦ by the PD phase discriminator, finishes the phase error data sampling; (2) the above-mentioned phase error data that obtains is joined the one-dimension array of forming by the phase error data sampling { ΔΦ }
mIn, be input among FIFO1 and the FIFO2, and remove phase error data of sampling at first in the array; If FIFO2 less than the time, phase data is only imported and is not exported; Or when if FIFO2 is full, the phase data in the FIFO2 is poured FIFO1 earlier into, returns step 1 then; The described ACC of third step reads the phase error data ΔΦ immediately from described FIFO1, and adds up, and by a multiplication and division circuit phase data is averaged then, and calculates corresponding voltage-controlled magnitude of voltage according to loop gain KgG by formula V_CTL=KgG* ΔΦ; The 4th step is regulated the output frequency of OCXO by D/A.
Relation between above-mentioned PD, array length and the FIFO degree of depth is: the each output time of PD is generally 250 milliseconds to the several seconds, general loop integral time constant and the each output time of PD according to the DPLL that will design of array length determined, for example, if the each output time of PD is 1S, requiring the DPLL integration time constant is 1000S, and then array length is 1000.And FIFO is the storage array, so the degree of depth of FIFO is relevant with array length.
Embodiment at sliding window DPLL of the present invention is described as follows below:
We know, shake in the 2M of SDH transmission network branch road/Energy distribution floats, generally be to concentrate in 0.01Hz～10Hz low frequency region, so the loop filter integration time constant must be far longer than 100s, otherwise the 0.01Hz low frequency that just is difficult to smoothly to fall the 2M branch road float.To the selection of window slip step value, to guarantee that OCXO dynamically adjusts within a short period of time on the one hand, to enough attenuations be arranged to guarantee the stable of output frequency to shaking/float the reference clock instantaneous frequency deviation that causes on the other hand.Loop filter integration time constant when supposing T for tracking, the stepping that window slides is τ, then the attenuation of instantaneous frequency deviation is T/ τ.If τ=1s, T=5000s, and the 2M branch road of SDH is generally 3～5ppm owing to shake/float the instantaneous frequency deviation that causes, then will decay to≤0.001ppm through sliding window DPLL, this can not cause the fluctuation of output frequency basically.In addition, benchmark (reference clock) is lost to and recovers and benchmark switches and all can cause reference clock phase jump (being instantaneous frequency deviation), and sliding window DPLL is effective this phase jump of filtering also.
Fig. 1 shows the workflow diagram of the DPLL of Telecommunication Network Element equipment clock.Reference clock send PD and local clock to carry out than mutually after LIU reception, recovery, frequency division or level conversion.For following when hardware is realized FIFO cross dark and software when realizing array excessive, PD will carry out once average to phase error data.Therefore specify PD to export average phase error data per 4 seconds.Adopt method that the time of integration, window slided that identified result is carried out integration with the shake of filtering reference clock/float and obtain OCXO control voltage.
Loop filter integration time constant when T is tracking, the window time of integration when promptly following the tracks of have been shown among Fig. 3.For catching state soon, the every τ of PD this moment obtains a phase error data in the time interval, and average together with the phase error data of front when the time of integration, window was less than T, and then the time of integration, window increased τ.The window time of integration of obviously catching soon be movable, increase progressively, can adapt to the regularly different network environment of quality deterioration degree of 2M branch road like this.Such as, catching integration time constant soon and can not obtain 10 as 240s
-8During the average frequency of precision, as long as the size of T suitably, the broadening of window generally all can obtain 10 before the window time of integration reaches T along with the time of integration
-8The average frequency of precision.After entering tracking, the time of integration, window T size was constant, and to front slide, and every slip once obtains a new phase error with the stepping of τ, lost in the window phase error of collection the earliest simultaneously.The each slip all to phase error data in time window T integrates, and obtain a voltage-controlled magnitude of voltage of new OCXO.Because it is very big that the window T time of integration when following the tracks of can obtain, sliding part advances value and then can establish very for a short time, and this explanation sliding window track algorithm is dynamic, can obtain its long-term average frequency by the effectively level and smooth big instantaneous frequency deviation of reference clock again.
As shown in Figure 4, the time of integration, window slid through an one-dimension array { ΔΦ }
mRealize.Array length is m (getting m=4096), if still designing per 4 seconds kind PD exports a phase error data ΔΦ, then the time of integration, window T was 4m second.Whenever ΔΦ of PD output, just deposit one-dimension array { ΔΦ } in
mWhen catching soon array less than the time, ΔΦ value of every increase in the array, just summation, average, and calculate V_CTL output.After entering tracking, because array is full, whenever an input new value (ΔΦ) in array
M+1Just, then equal first number (ΔΦ) in the array with pointed zero
1Refresh and be (ΔΦ)
M+1Again through after 4 seconds, second number (ΔΦ)
2Refresh and be (ΔΦ)
M+24m is after second for process, m number (ΔΦ)
mRefresh and be (ΔΦ)
2mPromptly through the window T cycle time of integration, the several refresh alls in the array once.Array { ΔΦ }
mWhenever refresh a number, just summation of whole array, average, and calculate V_CTL output by the V_CTL=KgG* ΔΦ.Adopt the double-FIFO structure by drawing whole DLF among Fig. 2.FIFO determines its degree of depth according to designing requirement.Dark more when the FIFO degree of depth, the average effect of DLF is good more.Suppose that PD exports the phase error data ΔΦ of one 4 second after average per 4 seconds, the phase error data that phase discriminator PD obtains FIFO less than, when promptly catching soon, be input to FIF01 and FIFO2 simultaneously.Accumulator ACC reads the phase error data ΔΦ immediately from FIFO1, and adds up.By a multiplication and division circuit phase data is averaged at last, and calculate voltage-controlled voltage V_CTL digital value according to loop gain G.The V_CTL digital value becomes the voltage of simulation and regulates its output frequency by the voltage-controlled end of OCXO through a D/A converter spare, thereby realizes phase place and frequency lock.For FIFO2, less than the time, phase data is only imported and is not exported.When FIFO2 was full, the phase data in the FIFO2 was poured FIFO1 earlier into, read in a new phase error data by PD output then, read all data in the FIFO1 immediately, and was input to ACC and FIFO2 simultaneously.ACC obtains the V_CTL digital value at last by the multiplication and division circuit after phase data is added up.Data in the FIFO2 are refunded FIFO1 again, and repeat aforesaid operations, so move in circles.The each cycling of FIFO1 and FIFO2 all refreshes a phase error data, and obtains a new V_CTL digital value by all data in the FIFO1.Above-mentionedly supposed that PD exports a phase error data per 4 seconds, then the time of integration, window slip stepping was 4 seconds.Suppose that the FIFO degree of depth is 4K * 8bit, then the time of integration, window T was 16384 seconds.The read-write operation of FIFO1 and FIFO2 is by full index signal FIFO1 FULL and the strict control of FIFO2 FULL of read-write 4S_WR and 4S_RD and two FIFO in 4 seconds, and its sequential relationship as shown in Figure 5.
Claims (5)
1. digital phase-locked loop of regulating crystal oscillator frequency, comprise LIU line interface unit, PD phase discriminator, DIV frequency divider, DLF digital loop filters and OCXO thermostatic control crystal oscillator, it is characterized in that: described DLF includes two first in first out shift counter FIFO1 and FIFO2, accumulator ACC, multiplication and division circuit and D/A converter.
2. method of utilizing the described digital phase-locked loop of claim 1 to regulate crystal oscillator frequency, it is characterized in that: the implementation method of described DLF may further comprise the steps:
(1) obtains the phase error data ΔΦ by the PD phase discriminator, finish the phase error data sampling;
(2) the above-mentioned phase error data that obtains is joined the one-dimension array of forming by the phase error data sampling { ΔΦ }
mIn, be input among FIFO1 and the FIFO2, and remove phase error data of sampling at first in the array; And
If FIFO2 less than the time, phase data is only imported and is not exported; Or
If when FIFO2 was full, the phase data in the FIFO2 was poured FIFO1 earlier into, returns step (1) then;
(3) described ACC reads the phase error data ΔΦ immediately from described FIFO1, and adds up, and by a multiplication and division circuit phase data is averaged then, and calculates corresponding voltage-controlled magnitude of voltage according to loop gain;
(4) regulate the output frequency of OCXO by D/A.
3. the method for adjusting crystal oscillator frequency according to claim 2 is characterized in that: the each output time of described PD be 250 milliseconds to the several seconds.
4. the method for adjusting crystal oscillator frequency according to claim 2 is characterized in that: the degree of depth of described FIFO is corresponding with the length of described array.
5. according to the method for claim 2 or 3 described adjusting crystal oscillator frequencies, it is characterized in that: described array { ΔΦ }
mLength and the ratio of the each output time of PD be 1000: 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021105383A CN100440986C (en) | 2002-01-09 | 2002-01-09 | Digital PLL regulating crystal oscillator frequency and its regulation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021105383A CN100440986C (en) | 2002-01-09 | 2002-01-09 | Digital PLL regulating crystal oscillator frequency and its regulation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1433227A true CN1433227A (en) | 2003-07-30 |
| CN100440986C CN100440986C (en) | 2008-12-03 |
Family
ID=27628171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021105383A Expired - Fee Related CN100440986C (en) | 2002-01-09 | 2002-01-09 | Digital PLL regulating crystal oscillator frequency and its regulation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100440986C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112737905A (en) * | 2020-12-22 | 2021-04-30 | 青岛鼎信通讯消防安全有限公司 | Method and system for transmitting and receiving parallel two-bus communication |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5148450A (en) * | 1990-05-15 | 1992-09-15 | Apple Computer, Inc. | Digital phase-locked loop |
| DE69225320T2 (en) * | 1992-09-25 | 1998-11-19 | Ibm | Adapter for connection to a "clear channel" transmission network |
-
2002
- 2002-01-09 CN CNB021105383A patent/CN100440986C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112737905A (en) * | 2020-12-22 | 2021-04-30 | 青岛鼎信通讯消防安全有限公司 | Method and system for transmitting and receiving parallel two-bus communication |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100440986C (en) | 2008-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5757652A (en) | Electrical signal jitter and wander measurement system and method | |
| EP0828343B1 (en) | Signal generator for generating a jitter/wander output | |
| AU745230B2 (en) | Apparatus for reducing jitter in a digital desynchronizer | |
| CN105960759B (en) | Two phase-locked loop and corresponding method and purposes with frequency stability | |
| EP0473338B1 (en) | Bit synchronization with elastic memory | |
| EP0849907B1 (en) | Phase measurement apparatus and method | |
| AU700007B2 (en) | Cell-based clock recovery device | |
| US6415006B2 (en) | Reducing waiting time jitter | |
| EP0626117B1 (en) | Desynchronizer and method for suppressing pointer jitter in a desynchronizer | |
| WO2010033255A1 (en) | Network timing synchronization systems | |
| CN100450230C (en) | Clock recovery method and apparatus in RF far-end module | |
| CN101536364A (en) | Method and apparatus for automatic frequency correction in a multimode device | |
| CN100440986C (en) | Digital PLL regulating crystal oscillator frequency and its regulation method | |
| CA2983578C (en) | Data phase tracking device, data phase tracking method and communication device | |
| CN101009545B (en) | A phase lock loop adjusting method and device for adjusting phase lock loop | |
| US5268655A (en) | Device and method for automatically adjusting a phase-locked loop | |
| CN101174940A (en) | Nonlinear parameter regulating phase-locked loop method and device | |
| EP0776094B1 (en) | Phase-locked loop circuit for reproducing clock signals synchronized with transmitter in receiver | |
| CN101931481A (en) | IEEE 1588 clock output device and method | |
| US6819727B1 (en) | Method and device for the numeric control of the buffer and of a phase-locked loop for asynchronous networks | |
| CN115037294A (en) | Phase-locked loop, signal processing equipment and signal processing method | |
| US7154979B2 (en) | Timing recovery with variable bandwidth phase locked loop and non-linear control paths | |
| FI85318B (en) | COMPENSATION AV FELET I EN KLOCKAS GAONG. | |
| CN112910590A (en) | Clock synchronization system and method | |
| CN102130765A (en) | Method for adjusting phase-locked loop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHENZHENG CITY ZTE CO., LTD. Free format text: FORMER OWNER: SHENZHENG CITY ZTE CO., LTD. SHANGHAI SECOND INSTITUTE Effective date: 20030725 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20030725 Applicant after: Zhongxing Communication Co., Ltd., Shenzhen City Applicant before: Shanghai Inst. of No.2, Zhongxing Communication Co., Ltd., Shenzhen City |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081203 Termination date: 20180109 |