CN101009545B - A method for adjusting a phase-locked loop and a device for adjusting a phase-locked loop - Google Patents

Abstract

The invention belongs to the digital communication technical field and provides a method for adjusting the phase-locked loop and the device of phase-locked loop. For concreteness: the real-time measurement for quality is done, and calculates the phase difference between the reference time and the local time, if the phase difference is bigger than the second presetting phase difference, the judge is degraded, and the detection goes on until the phase difference is smaller or equal with the second presetting phase difference, and select the fast repairing parameter, if the said phase difference is bigger than the first presetting phase difference, and chooses one fast repairing parameter whose damp coefficient is smaller than the presetting, and if the said phase difference is smaller or equal with the first presetting phase difference, and switch one fast repairing parameter whose damp coefficient is bigger than the presetting. Using the invention, it can reduce the time of entering lock, eliminate the shake of input phase effectively, and when the reference clock is degraded, the local time do not trace to ensure the quality of reference clock.

Description

A method for adjusting a phase-locked loop and a device for adjusting a phase-locked loop

technical field

The invention relates to the technical field of digital communication, in particular to a method for adjusting a digital phase-locked loop and a device for adjusting the phase-locked loop. the

Background technique

With the wide application of various communication systems on public telecommunication networks, the scale of the network is getting larger and the network environment is becoming more and more complex, especially for various edge networks such as wired access networks and wireless access networks, the network environment It is more complicated, for example, the transmission network relied on includes SDH (Synchronous Digital Hierarchy, synchronous digital system), PDH (Pseudo-synchronous Digital Hierarchy, quasi-synchronous digital system), digital microwave and even SDH/PDH hybrid network. At present, the transmission network is basically based on SDH. Although SDH has its unique broadband, strong self-healing ability, and powerful network management capabilities, SDH still needs to work in a synchronous environment in order to interface with PDH and carry multiple services. Otherwise, a large number of pointer adjustments will seriously deteriorate the 2M branch service and timing quality; on the other hand, in order to allocate and transmit timing, SDH also needs to work in a synchronous mode. Even if SDH works in a synchronous environment, due to the jitter accumulation and the noise process of the equipment itself, the pointer adjustment will still occur, especially when the number of network elements exceeds a certain phase difference, the pointer adjustment will increase rapidly, so a clock phase-locked loop is required to make the system The clock goes up one step synchronously. the

The global clock system of the communication system requires that the local clock can track the external clock with good quality smoothly and stably. It must adopt a loosely coupled clock phase-locked loop instead of an integrated clock phase-locked loop of the local clock system, that is, a tightly coupled clock-locked loop. phase ring. A high-performance clock synchronization system is indispensable in the field of communication transmission, and determines the performance of the entire communication transmission business to a large extent. The clock synchronization system is based on the synchronization principle of the phase-locked loop, tracking the reference clock, and comparing the output frequency with the input frequency to obtain a phase difference value, and then through the low-pass filtering method to control the high-performance voltage-controlled oscillator. Finally, the output frequency and the input frequency are strictly kept the same. The quality of the clock phase-locked loop will directly affect the rapidity of clock capture, the accuracy and stability of clock tracking. the

In the prior art, the quick capture parameters used are: ζ=0.707, ω _n =0.007rad/s, when the difference between the local clock and the reference clock is 2.5PPM, the lock-in time will be 13 minutes, the response speed is slow, and the lock-in time is long . Due to the large phase difference between the local clock and the reference clock, the local clock will overshoot when it reaches the frequency of the reference clock due to inertia. Moreover, when switching the clock reference source, if the quality of the reference source is not checked first, the local clock will still track when the quality of the reference source is poor.

Contents of the invention

The technical problem to be solved by the embodiments of the present invention is to provide a method for adjusting a digital phase-locked loop and a device for adjusting the phase-locked loop, which can realize smooth and stable tracking of an external reference clock by a local clock. the

In order to solve the problems of the technologies described above, the purpose of the present invention is achieved through the following technical solutions:

An embodiment of the present invention provides a method for adjusting a phase-locked loop, including:

Preset the parameters of the phase-locked loop, input the reference clock, set the phase-locked state flag as the fast capture flag, and initialize the control parameters and control variables;

Detect the phase of the reference clock and the local clock, calculate the phase difference between the reference clock and the local clock, if the phase difference is greater than the second preset phase difference, then alarm, continue to detect the quality of the reference clock until the phase difference Less than or equal to the second preset phase difference; if the phase difference is greater than the first preset phase difference, then select a group of fast capture parameters with a damping coefficient smaller than the preset damping coefficient, if the phase difference is less than or is equal to the first preset phase difference, switch to a set of fast capture parameters with a damping coefficient larger than the preset damping coefficient. the

The embodiment of the present invention also provides a device for adjusting the phase locked loop, including: a quick capture parameter selection unit, a phase detector and a quality detection unit;

A phase detector, used to detect the phase of the reference clock and the local clock, calculate the phase difference between the reference clock and the local clock, and send the phase difference to the quick capture parameter selection unit;

The quick capture parameter selection unit compares whether the received phase difference is greater than the first preset phase difference, if so, selects a group of quick capture parameters with a damping coefficient smaller than the preset damping coefficient, otherwise, selects a group of fast capturing parameters with a damping coefficient smaller than the preset damping coefficient A set of fast-catching parameters with a large damping coefficient; and

The quality detection unit is used to detect whether the phase difference between the reference clock received from the phase detector and the local clock is greater than the second preset phase difference, if so, alarm, and continue to detect until the reference clock and the local clock When the phase difference between the local clocks is less than or equal to the second preset phase difference, the phase difference between the reference clock and the local clocks is sent to the quick capture parameter selection unit. the

It can be seen from the above technical solutions that the present invention calculates the phase difference between the reference clock and the local clock by detecting the phases of the reference clock and the local clock, and selects the quick capture parameter. If the phase difference is greater than the first preset phase poor, then select a group of quick capture parameters whose damping coefficient is smaller than the preset damping coefficient to achieve fast response and shorten the time for locking; if the phase difference is less than the first preset phase difference , then switch to a set of fast-capture parameters whose damping coefficient is larger than the preset damping coefficient, reduce overshoot, achieve fast convergence, and effectively eliminate the jitter of the input phase. the

Description of drawings

Fig. 1 is the flowchart of the embodiment of the present invention;

Figure 2 is a general lock-in schematic diagram of a second-order phase-locked loop;

Fig. 3 is the schematic diagram that adopts the phase-locked loop that self-adaptive parameter adjustment of the embodiment of the present invention locks in

Fig. 4 is a block diagram of a device provided by an embodiment of the present invention. the

Detailed ways

Embodiments of the present invention provide a method for adjusting a phase-locked loop and a device for adjusting a phase-locked loop. In order to make the purpose, technical solutions and advantages of the present invention clearer, the following examples are given with reference to the accompanying drawings to further describe the present invention. Detailed description. the

Referring to Fig. 1, it is a flowchart of an embodiment of the present invention, specifically as follows:

101: preset the parameters of the phase-locked loop circuit model;

102: Preset the power-on test preheating flag and the power-on preheating flag, if the preset power-on preheating flag is 55AAH, detect whether the power-on test preheating flag is the power-on preheating flag, If so, enter step 103, otherwise, power on and preheat until the power-on test preheating flag is the power-on preheating flag;

103: Input the reference clock, set the phase lock state as the fast capture flag, and initialize the control parameters and control variables;

104: Calculate the phase difference between the reference clock and the local clock, if the phase difference between the reference clock and the local clock is greater than a second preset phase difference, for example, the second preset phase difference is 0.4 PPM, it is determined that the reference clock is degraded, and step 106 is performed, and if the phase difference between the reference clock and the local clock is less than or equal to the second preset phase difference, then step 105 is performed;

105: Within the range of the second preset phase difference, for the phase difference between the reference clock and the local clock and the first preset phase difference, for example, the first preset phase difference is 0.1 PPM, for comparison, if the phase difference is greater than the first preset phase difference, then select a group of quick capture parameters with a damping coefficient smaller than the preset damping coefficient, and the preset damping coefficient is used to determine the size of the damping coefficient A reference can be preset according to the specific situation. If the phase difference is less than or equal to the first preset phase difference, switch to a set of fast capture parameters with a damping coefficient larger than the preset damping coefficient, and enter Lock discrimination, if satisfy preset lock-in discrimination condition, for example, described lock-in discrimination condition is: the phase difference between local clock and reference clock in 5 minutes is less than 0.1PPM, then set phase-lock state mark as tracking mark, Parameters are converted from quick capture parameters to tracking parameters, enter step 107, if the lock-in condition is not satisfied, then repeat step 104;

106: Alarm, continue to detect whether the phase difference between the reference clock and the local clock is greater than the second preset phase difference, if so, repeat step 106, otherwise, go to step 105;

107: The local clock tracks the reference clock, and if the phase difference between the local clock and the reference clock is greater than the preset out-of-lock discrimination phase difference, for example, the out-of-lock discrimination phase difference can be 0.3PPM, and it is judged as out-of-lock, if The phase difference between the local clock and the reference clock is less than or equal to the preset out-of-lock discrimination phase difference, then the local clock continues to track the reference clock, and detects in real time whether the phase difference between the reference clock and the local clock is greater than the preset phase difference. If it is the second preset phase difference, if it is determined that the reference clock is degraded, step 108 is executed; otherwise, if it is detected that the phase difference between the reference clock and the local clock is less than or equal to the second preset phase difference , that is, the reference clock is qualified, then return to step 104;

108: Set the phase-locked state to hold, and detect the quality of the reference clock in real time. If the phase difference is less than or equal to the second preset phase difference, the reference clock is restored and enters the fast capture state, and returns to step 107. If the phase difference is greater than the second preset phase difference, continue to execute step 108 . the

Wherein, the parameters of the preset phase-locked loop in step 101 include: determining the voltage control sensitivity according to the selected crystal oscillator, determining the damping coefficient and the free oscillation frequency according to the characteristics of the reference source, and determining the two phase-locked loops according to the system accuracy requirements. The nominal frequency of the clock and the count clock frequency. the

Wherein, in the step 105, in the process of selecting the quick capture parameters, if the deviation of the reference clock and the local clock is too large, it can be divided into multiple sections and multiple groups of parameters, such as three sections, i.e. three groups of parameters. For example, from a difference of 6PPM to a difference of 2PPM, from a difference of 2PPM to a difference of 0.3PPM, from 0.3PPM to locking. the

Wherein, in the step 103, the process of initializing control parameters and control variables includes: reading from the EEPROM, pre-stored parameters, if there is no storage in the EEPROM or the parameters read do not meet the requirements, the control parameters and control variables are then Take the values in the initialization function as parameters and variables. the

Below in conjunction with the closed-loop transfer function of the phase-locked loop, the embodiments of the present invention are further described:

$\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; v</span>}}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; a</span>}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; v</span>}}}{{\mathrm{<span\; class="notranslate">\; the\; <figure-callout\; id="2"\; label="s"\; filenames="S07100194520070116E000021.png"\; state="\{\{state\}\}">s</figure-callout></span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; v</span>}}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; a</span>}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; v</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

a is the integral coefficient. set up

$\mathrm{<span\; class="notranslate">\; \&zeta;</span>}<span\; class="notranslate">\; =</span>\sqrt{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; v</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; a</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; a</span>}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; v</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Among them, ζ is the damping coefficient, ω _n is the free oscillation frequency.

Another way to express the closed-loop transfer function of the phase-locked loop (4):

$\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; \&theta;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; \&theta;</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&zeta;</span>}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; the\; <figure-callout\; id="2"\; label="s"\; filenames="S07100194520070116E000021.png"\; state="\{\{state\}\}">s</figure-callout></span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&zeta;</span>}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

The derived error function is:

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; e</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; \&theta;</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; \&theta;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; \&theta;</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; the\; <figure-callout\; id="2"\; label="s"\; filenames="S07100194520070116E000021.png"\; state="\{\{state\}\}">s</figure-callout></span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; the\; <figure-callout\; id="2"\; label="s"\; filenames="S07100194520070116E000021.png"\; state="\{\{state\}\}">s</figure-callout></span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&zeta;</span>}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

It can be seen that H(s) has low-pass characteristics, as long as ζ and ω _n are properly selected, the input phase jitter can be well filtered out.

When the input reference clock signal f _i is an ideal clock signal, the input reference clock signal f _i can be regarded as a step function:

ω _i (t) = α U (t) (6)

Then the change of the input phase with time is:

${\mathrm{<span\; class="notranslate">\; \&theta;</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; \&Integral;</span>}_{\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; i</span>}}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&tau;</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; d\&tau;</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&alpha;t</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

When the frequency of the input signal is a step function, the stable phase error can be obtained by the final value theorem:

E _s = lim s E(s) = lim sθ _i (s) _He (s) = 0 (8)

Equation (8) shows that when the second-order phase-locked loop jumps to the reference clock and is stable at a certain frequency, the final result of phase-locking is that the phase is consistent, and of course the frequency is also consistent. According to the same analysis, if the reference frequency changes linearly with time, the result is that after phase-locking by the second-order phase-locked loop, there is a stable phase difference between the input and output, and the input and output frequencies are the same. the

The following example explains in detail:

The selected parameters are damping coefficient ζ=0.707, free oscillation frequency ω _n =0.007rad/s, reference reference clock f _i is 8000 Hz, local clock f ₀ is 8000.02 Hz, and the difference between the reference clock and the local clock is 2.5PPM.

Referring to Fig. 2, it is the general lock-in process of the second-order phase-locked loop. It can be seen from the figure that f ₀ oscillates back and forth, gradually approaching _fi under the action of damping, and finally locks, but the lock-in time is too long, reaching 13 minutes.

In order to change the problem of too long lock-in time, the present invention adopts a digital phase-locked loop technology with self-adaptive parameter adjustment. In the initial stage, the parameter damping coefficient ζ=0.707, the free oscillation frequency ω _n =0.007rad/s, when the local clock and the reference When the phase difference between clocks is less than 0.3PPM, switch to another set of smoother parameter damping coefficient ζ=3.54, free oscillation frequency ω _n =0.002rad/s. As a result, the local clock quickly tracks the reference clock, and it only takes 3 minutes to enter the lock, and the lock entry condition is 0.1PPM.

Referring to Fig. 3, for the lock-in process of the phase-locked loop that adopts the parameter adjustment of the present invention, as can be seen from the figure, when the phase difference between the local clock and the reference clock is less than 0.3PPM, selecting a larger damping coefficient can reduce the Adjustment, to achieve fast convergence, the local clock tracking reference clock produces a small inertia, will not produce a large overshoot and reverberation, and can effectively eliminate the jitter of the input phase. Therefore, when the difference between them is small, switching to another set of appropriate parameters can effectively shorten the lock-in time. After entering the lock, select the locked parameters, damping coefficient ζ = 3.8, free oscillation frequency ω _n = 0.0005rad/s, which can effectively eliminate the jitter of the input phase.

Wherein, the transfer function and various parameter conversion algorithms can be implemented by a microprocessor. K _m is the conversion coefficient from the phase difference count output value of the digital phase detector to the phase difference; K _θ is the phase detection sensitivity, that is, the control voltage that should be output per unit phase difference; K _n is the digital conversion coefficient of the voltage-controlled oscillator VCO control voltage, That is, the VCO voltage is converted into the digital voltage value of the DAC; K _f is the voltage control sensitivity of the VCO, that is, the VCO frequency change caused by the unit control voltage. The relationship between K _f , K _θ and the loop gain K _v is as follows:

K _v =K _f ·K _θ (9)

For the selected voltage-controlled oscillator VCO, K _f is known, K _v is determined by the selected ζ, ω _n through formulas (2) and (3), then K _θ can be determined by formula (9). When the clock counting frequency of the digital phase detector is determined, K _m is also determined. The digital phase detector can convert the phase difference of the two signals into the width of the digital pulse, and use this pulse to control the counting of the counter. The size of the phase difference reflects the width of the pulse, which is actually measured by the period of the counter clock. Measure the width of the pulse. If the reference clock frequency of the two signals involved in phase locking is f _i , and the local clock frequency is f ₀ , then K _m is:

K _m =2πf _i /f ₀ (10)

If the phase difference of the phase detector obtained by the phase detector counter is m, then the phase difference θ _e is:

θ _e =K _m m (11)

Among them, K _m is the phase difference represented by the phase difference of the unit phase detector, and K _n is the basic quantization voltage of how many DACs are required to represent the unit voltage.

According to the algorithm of the second-order phase-locked loop, the VCO control voltage of the voltage-controlled oscillator is calculated by the following formula:

V _ctrl ＝K _m K _n K _θ ·(θ _e +a·sθ _e ) (12)

Wherein, said V _ctrl is the voltage-controlled oscillator VCO control voltage, θ _e is the phase difference after linearization processing with the phase difference of the phase detector as the unit, sθ _e is the integral of θ _e to time, and a is the integral coefficient .

It can be seen that if the PLL is already in the locked state and θ _e is zero at this time, the control voltage is determined by sθ _e and the control parameters a and K _m , K _n and K _θ parameters of the PLL.

So far, all control parameters of the phase-locked loop have been obtained. the

Wherein, the local clock is provided by an oven-controlled crystal oscillator, and the frequency and stability of the oven-controlled crystal oscillator are closely related to temperature, so the frequency stability of the local clock is closely related to the temperature of the oven-controlled crystal oscillator. When the constant temperature bath crystal oscillator is powered on, because it has not yet reached thermal equilibrium, there will be a large difference between its initial output frequency and the nominal frequency. If the quick capture process is entered at the beginning, the θ _e and sθ _e will deviate far from the locked value, resulting in a long fast capture process. For this reason, there is a 7-minute power-on preheating process before entering the fast capture process, waiting for the crystal oscillator in the constant temperature bath to basically stabilize. If it is reset normally, it can skip the power-on preheating process and directly enter the quick capture process. For example, set the power-on test flag byte of a byte. If it is detected that the flag byte is not 55AAH, it indicates that it is a new power-on, and then enters the power-on preheating stage. After the preheating is over, the test flag byte is set to 55AAH, indicating that it has been preheated. If a normal reset causes the processor to re-enter the initialization sequence, the warm-up sequence can be skipped since a valid power-up test flag byte has already been set.

The reference clock can be extracted from the SDH transmission network. Since the loop of the transmission network is very complex, it cannot be guaranteed that the reference clock extracted from the SDH transmission network at all times is of good quality and meets the tracking requirements. When the reference clock extracted from the SDH transmission network deviates from the reference frequency, the local reference clock cannot be tracked, otherwise the local reference clock will be seriously pulled. It is necessary to establish a basis for judging the degradation of the benchmark, and this technology provides a method for judging the degradation of the clock. It is realized by measuring the change of the phase difference of the two clock signals, as follows:

${\mathrm{<span\; class="notranslate">\; \&theta;</span>}}_{\mathrm{<span\; class="notranslate">\; e</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}{<span\; class="notranslate">\; \&Integral;</span>}_{{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}^{{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; dt</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 13</span>}<span\; class="notranslate">\; )</span>$

f _i is the frequency of the external reference clock, f ₀ is the output frequency of the local clock, and θ _{e is} the phase difference between them in the t ₁ ~ t ₂ period. Equation (13) shows that if the two clock frequencies are the same, f _i is equal to f ₀ , then θ _e is zero, and the phase difference between them will remain constant. If the frequencies are not equal, the phase difference increases with time, and the greater the frequency difference, the faster the phase difference changes with time. Therefore, the frequency difference between the two clocks can be inferred by detecting the change of the phase difference, so as to determine whether the quality of the clock is degraded.

Referring to Fig. 4, a kind of device for adjusting phase-locked loop that the embodiment of the present invention provides, comprises:

Phase detector 401, quality detection unit 402, parameter selection unit 403;

The phase detector 401 is used to detect the phase of the reference clock and the local clock, calculate the phase difference between the reference clock and the local clock, and send the phase difference to the quality detection unit 402;

The quality detection unit 402 is used to detect the quality of the reference clock, and when it is detected that the phase difference received from the phase detector 401 is greater than the second preset phase difference, an alarm is given, and the quality of the reference clock continues to be detected until the phase difference is greater than the second preset phase difference. The difference is less than or equal to the second preset phase difference, and the second preset phase difference is sent to the quick capture parameter selection unit 403;

Fast catch parameter selection unit 403, compare whether the phase difference between the received reference clock and the local clock is greater than the first preset phase difference, if so, select a group of fast catch parameters with damping coefficient less than the preset damping coefficient , otherwise, select a set of fast capture parameters whose damping coefficient is larger than the preset damping coefficient. the

Wherein, the device further includes: a filter 404, a voltage-controlled oscillator 405;

A filter 404, configured to filter the received phase difference, and convert the phase difference into a voltage-controlled voltage for the voltage-controlled oscillator 405;

The voltage-controlled oscillator 405 is configured to convert the received voltage-controlled voltage into a local clock output. the

Wherein, the first preset phase difference is smaller than the second preset phase difference. the

Wherein, the reference clock can be extracted from the SDH transmission network, because the loop of the transmission network is very complicated, it cannot be guaranteed that the reference clock extracted from the SDH transmission network at all times is of good quality and meets the tracking requirements. The detection unit 402 performs real-time quality detection on the reference clock extracted from the SDH transmission network. When it is detected that the reference clock deviates from the reference frequency, the local reference clock cannot be tracked, otherwise the local reference clock will be seriously skewed. the

Wherein, after the local clock enters the tracking state, the reference clock still detects the quality of the reference clock in real time, and if the degradation of the reference source is detected, that is, the phase difference between the reference clock and the local clock is greater than the second preset Set the phase difference, set the phase lock status to hold, and continue to detect the quality of the reference source in real time. If the quality of the reference source is automatically restored, the local clock will continue to track. the

As can be seen from the above embodiments, the present invention detects the quality of the reference clock in real time. When the reference clock degrades, the local clock will not track it, and by detecting the phases of the reference clock and the local clock, the reference clock and the local clock are calculated. The phase difference between them, select the quick capture parameter, if the phase difference is greater than the first preset phase difference, then select a quick capture parameter with a damping coefficient smaller than the preset damping coefficient in a group of quick capture parameters to achieve fast Response, shorten the time of entering the lock; if the phase difference is less than the first preset phase difference, then switch to a set of fast capture parameters whose damping coefficient is larger than the preset damping coefficient, and reduce the overshoot Adjustment to achieve fast convergence, effectively eliminate the jitter of the input phase, and quickly, reliably and accurately synchronize with the frequency reference of the upper node, thus providing a stable, accurate and reliable frequency reference for the lower node. the

A method for adjusting the phase-locked loop provided by the present invention and a device for adjusting the phase-locked loop have been introduced in detail above. In this paper, specific examples have been used to illustrate the principle and implementation of the present invention. The above embodiments The description is only used to help understand the method of the present invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application. In summary , the contents of this specification should not be construed as limiting the present invention.

Claims (8)

1. A method for adjusting a phase-locked loop, characterized in that, comprising: Preset the parameters of the phase-locked loop, input the reference clock, set the phase-locked state flag as the fast capture flag, and initialize the control parameters and control variables; Detect the phase of the reference clock and the local clock, calculate the phase difference between the reference clock and the local clock, if the phase difference is greater than the second preset phase difference, then alarm, continue to detect the quality of the reference clock until the The phase difference is less than or equal to the second preset phase difference; if the phase difference is greater than the first preset phase difference, then select a group of quick capture parameters whose damping coefficient is smaller than the preset damping coefficient, if the phase difference If it is less than or equal to the first preset phase difference, switch to a set of fast capture parameters with a damping coefficient larger than the preset damping coefficient. 2. The method according to claim 1, wherein the first preset phase difference is smaller than the second preset phase difference. 3. The method according to claim 1, characterized in that, after said selection of quick capture parameters, comprising: performing lock-in discrimination, if the preset lock-in condition is met, then setting the phase-lock status flag as a tracking flag, parameter Convert the fast capture parameter to the tracking parameter, and if it is detected that the phase difference between the reference clock and the local clock is greater than the second preset phase difference, continue to detect until the phase difference between the reference clock and the local clock The difference is less than or equal to the second preset phase difference. 4. The method according to claim 3, characterized in that, after the phase-locked state flag is set as a tracking flag, it also includes: The local clock tracks the reference clock, and judges whether the phase difference between the local clock and the reference clock is greater than the preset out-of-lock discrimination phase difference. variable, otherwise, the local clock continues to track the reference clock; If it is detected that the phase difference between the reference clock and the local clock is greater than the second preset phase difference, an alarm will be issued, and the phase lock state will be set to hold, and continue to detect whether the phase difference is less than or equal to the second preset If so, set the phase-locked state to fast capture; otherwise, continue to detect whether the phase difference between the reference clock and the local clock is less than or equal to the second preset phase difference. 5. The method according to claim 1, wherein, before the input reference clock, comprising: Presetting the power-on test preheating flag and the power-on preheating flag, detecting whether the power-on test preheating flag is the power-on preheating flag, if so, setting the phase-locked state flag as a fast catch flag, otherwise , power on and preheat until the power-on test preheat flag is the power-on preheat flag. 6. A device for adjusting a phase-locked loop, characterized in that it comprises: a quick capture parameter selection unit, a phase detector and a quality detection unit; A phase detector, used to detect the phase of the reference clock and the local clock, calculate the phase difference between the reference clock and the local clock, and send the phase difference to the quick capture parameter selection unit; The quick capture parameter selection unit compares whether the received phase difference is greater than the first preset phase difference, if so, selects a group of quick capture parameters with a damping coefficient smaller than the preset damping coefficient, otherwise, selects a group of fast capturing parameters with a damping coefficient smaller than the preset damping coefficient A set of fast-catching parameters with a large damping coefficient; and The quality detection unit is used to detect whether the phase difference between the reference clock received from the phase detector and the local clock is greater than the second preset phase difference, if so, alarm, and continue to detect until the reference clock and the local clock When the phase difference between the local clocks is less than or equal to the second preset phase difference, the phase difference between the reference clock and the local clocks is sent to the quick capture parameter selection unit. 7. The device according to claim 6, wherein the first preset phase difference is smaller than the second preset phase difference. 8. The device according to claim 6, wherein the device further comprises: a filter for filtering the phase difference between the received reference clock and the local clock, and converting the phase difference into a voltage-controlled voltage for the voltage-controlled oscillator; A voltage-controlled oscillator, configured to convert the received voltage-controlled voltage into a local clock output. the

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