CN1427564A - Synchronous signal detecting circuit device and detecting method of said device detecting synchronous signal - Google Patents
Synchronous signal detecting circuit device and detecting method of said device detecting synchronous signal Download PDFInfo
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- CN1427564A CN1427564A CN01144557A CN01144557A CN1427564A CN 1427564 A CN1427564 A CN 1427564A CN 01144557 A CN01144557 A CN 01144557A CN 01144557 A CN01144557 A CN 01144557A CN 1427564 A CN1427564 A CN 1427564A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2668—Details of algorithms
- H04L27/2673—Details of algorithms characterised by synchronisation parameters
- H04L27/2675—Pilot or known symbols
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Abstract
A device for detecting synchronizing signals is composed of correlation arithmetic unit and a correlation peak detector for comparing the output of correlation arithmetic unit with threshold voltage to detect the synchronizing signal by judging the time interval between adjacent peaks. Its detecting method includes such steps as defining the signals of said correlation arithmetic unit and correlation peak detector, arithmetic processing to relative values, and detecting synchronizing signal.
Description
Technical field
The present invention relates to the detection method that synchronization signal detection circuit device in a kind of OFDM (Orthogonal Frequency Division Multiplexing) communication system and this device detect synchronizing signal.
Background technology
The detection of synchronizing signal is an important component part of wireless communication system.Carrying out auto-correlation computation to received signal is a kind of traditional synchronization detecting method.The subject matter of utilizing auto-correlation computation to detect synchronizing signal is that circuit scale and power consumption are big.Yet, do not have technical substantial breakthrough not have relevant document to disclose at present as yet at this problem yet.
Summary of the invention
Problem to be solved by this invention provides a kind of device, this device can utilize the characteristics that the characteristic signal in the synchronizing signal repeats and utilize the computing cross-correlation device to detect characteristic signal in the received signal, realizes the detection of synchronizing signal with the running of its computing cross-correlation device and correlation peak detector.Take this, the main technical schemes that the present invention will deal with problems is: a kind of synchronization signal detection circuit device is provided, at least comprise a computing cross-correlation device, one correlation peak detector, wherein, described computing cross-correlation device is a computing cross-correlation device of being made computing cross-correlation by input signal and condition code signal, described correlation peak detector is that the cross-correlated signal and the predefined family of power and influence's voltage that receive described computing cross-correlation device output compare the back judgement of passing through the time interval of adjacent peak value, detect the correlation peak arithmetic unit of synchronous head, and described its signal output part of computing cross-correlation device is connected with the signal input part of described correlation peak arithmetic unit.And the present invention also provides a kind of detection method of utilizing this device to detect synchronizing signal, can obtain the precise quantification value of short, long condition code at least with several formulas in the method, thereby determines synchronous head signal.At, detect the device of synchronizing signal and the method that such device detects synchronizing signal than auto-correlation computation, substantive distinguishing features that the present invention had and outstanding feature are conspicuous: utilize device simple in structure to realize the detection of synchronizing signal, utilize the specifically defined and algorithm through this device input, output signal is drawn the precision value that is of universal significance.
Description of drawings
Fig. 1 is the structural representation of the synchronization signal detection circuit device that the present invention relates to;
Fig. 2 is the embodiment of synchronization signal detection circuit device that the present invention relates to.
Fig. 3 is a synchronized signal detector correlation peak output schematic diagram;
Fig. 4 is the Digital Analog Hybrid Circuits structural representation of short condition code real part computing cross-correlation;
Fig. 5 is the digital circuit structure schematic diagram figure of short condition code real part computing cross-correlation;
Chart 1 is the short condition code Short Symbol value before quantizing;
Chart 2 is the short condition code Short Symbol quantized values after quantizing;
Chart 3 is the long condition code Long Symbol values before quantizing;
Chart 4 is the long condition code Long Symbol quantized values after quantizing;
Embodiment
By Fig. 1 and other accompanying drawing, all charts, the present invention relates to a kind of synchronization signal detection circuit device, this device comprises a computing cross-correlation device at least, one correlation peak detector, wherein, described computing cross-correlation device is a computing cross-correlation device of being made computing cross-correlation by input sample signal and condition code signal, described correlation peak detector is to receive the correlation peak arithmetic unit that detects synchronous head after the cross-correlated signal of described computing cross-correlation device output and predefined family of power and influence's voltage compare, and described its signal output part of computing cross-correlation device is connected with the signal input part of described correlation peak arithmetic unit.And, described computing cross-correlation device comprises that at least one stack features sign indicating number real part and condition code imaginary part do the computing cross-correlation circuit of computing cross-correlation with input real part or input imaginary part respectively separately, the output of described computing cross-correlation circuit links to each other with at least one group of add circuit respectively, its input of described add circuit links to each other with the quadratic sum computing circuit, and described quadratic sum computing circuit links to each other with the input of peak value detector.And described computing cross-correlation device can be that a kind of digital-to-analogue is as shown in Figure 4 mixed the computing cross-correlation device, and is made of at least one group of sampling value preserving circuit, one group of reverse operational amplifier.And, described computing cross-correlation device can be a kind of digital computing cross-correlation device as shown in Figure 5, and by at least one group 16 Parallel Digital switch SW Bank1, one group of sixteen bit shift register SR that is used to control 16 Parallel Digital switches, one group of plural bit register group RegBank that controls and be connected by Parallel Digital switch SW Bank1 with input signal, one group is used to realize that value is 0,1,-1 condition code and input signal mutually 16 grades of shift registers of multiplication to (Cx0, Cx1, x is 0 to 15 integer value), one group be connected with adder by shift register to (Cx0, Cx1) Kong Zhi switch SW Bank2, one group of adder ADDB of being connected with control switch SWBank2 constitutes, and the initial condition that is used to control the sixteen bit shift register SR of 16 Parallel Digital switch SW Bank1 can be made as 1000000000000000; Be used to realize value be 0,1 ,-1 condition code with input signal mutually multiplication 16 grade of 2 bit shift register to (Cx0, initial condition Cx1) can be made as (0,0) (1,0) (0,0) (0,0) (0,0) (1,0) (0,0) (0,0) (1,0) (0,0) (0,1) (0,1) (0,1) (0,0) (1,0) (0,0), and the right shift motion of shift register SR and shift register is controlled by the clock signal that has a same frequency with input signal.Simultaneously, it detects the detection method of synchronizing signal to utilize described device, this method comprises the formula treatment step of the condition code in computing cross-correlation device, the correlation peak detector, condition code and input sample signal, input analog signal and sampling holder being exported analog signal and correlation peak, synchronous head, wherein, the formula of synchronous head signal is:
In the formula, S (t) is synchronizing signal and is made up of M characteristic signal that a is a constant of expression fading channel coefficient, and C (t) is the condition code signal, can be real number or complex signal, and N is the number of condition code signal element; The condition code signal is made up of N code element and formula is:
In the formula, c
i(t) representing length is the code element of T; The code element of characteristic signal and the formula of sampled signal are:
In the formula, s (m) is the complex sampling value of the signal that receives,
Be the conjugate of code element, Re{ }, Im{ } expression real and imaginary part; And described condition code signal is divided into short condition code signal and long condition code signal, and its quantification treatment formula of the real of described short condition code signal and imaginary part is respectively::
Its quantification treatment formula of the real of described long condition code signal and imaginary part is respectively:
And the computing cross-correlation formula of the real part of described short condition code signal and input sample signal is:
In addition, described synchronous head signal is that interval and formula between a kind of that can be consecutively detected peak value and the adjacent peak value gap length of calculating is corresponding to by the detected synchronous head signal of correlation peak detector.
Fig. 1 is represented is structural relation between computing cross-correlation device and the correlation peak detector, obviously, how to detect the front end output signal that synchronizing signal depends on the correlation peak detector, and its operation principle also can be shown it by Fig. 4 or Fig. 5.If the synchronizing signal s in the wireless signal that receives (t) is made up of M characteristic signal, can calculate the value of synchronizing signal and characteristic signal by formula (1), formula (2) so.And, code element c in formula 2
iCan get real number value or complex values.Work as c
iDuring for non-integer,, can carry out quantification treatment according to actual needs in order to simplify the complexity of circuit.Certainly, after the sampling, carry out computing cross-correlation shown in formula (3) with the code element of characteristic signal to received signal, can obtain the output signal with correlation peak as shown in Figure 3, the time interval of its correlation peak is N * T.For the cross-correlated signal of computing cross-correlation device output, the correlation peak detector detects the related output signal with high voltage by the family of power and influence's voltage that sets in advance.Because including adjacent peak value blanking time in the relevant output of synchronizing signal is N the correlation peak of NT, therefore by the blanking time of the adjacent peak value in the judgement related output signal and the number of peak value, just can judge whether the signal that receives contains synchronous head signal.
Is that the short characteristic signal (Short Symbol) of 0.8 microsecond (16 sampled values) and long characteristic signal (Long Symbo1) that 2 length is 1.6 microseconds (32 sampled values) are formed based on the synchronizing signal of the wideband wireless local area network of IEEE802.11a or HiperLAN2 standard supposition by 10 length.With reference to chart 1, when now applying the present invention to wideband wireless local area network (Broadband Wireless LAN) communication system based on IEEE802.11a or HiperLAN2 standard, for the realization complexity of simplifying circuit keeps necessary operational precision simultaneously, can carry out quantification treatment to the real part and the imaginary part of the fractional fixed point code element in the chart 1 by formula (4), (5).Result after the quantification is shown in chart 2.In like manner, formula (6) (7) is at chart 3, promptly the real part and the imaginary part of the fractional fixed point code element of each long characteristic signal is carried out the quantification treatment formula, and its quantized value is shown in chart 4.In addition, at the plural computing cross-correlation shown in the formula (3), form by four real number computing cross-correlation circuit with analog structure.Therefore, the real part that can lack characteristic signal when the method for designing of its computing cross-correlation circuit of explanation is an example announcement relation each other with the computing cross-correlation of the real part of input signal.Formula (8) can be realized with Fig. 4 or circuit shown in Figure 5.Shown in Figure 4 is computing cross-correlation Digital Analog Hybrid Circuits structure, and the SH1 to SH14 among the figure represents 14 sampling hold circuits, and NAMP1 and NAMP2 represent two reverse operational amplifiers, and capacitor volume is in the ratio value among the figure.When importing analog signal under the control of Action clock signal, behind sampling hold circuit, displacement step by step, the output analog signal of sampling hold circuit directly is added in many input addition and subtraction circuits and goes, and the output analog signal that obtains is represented by formula (9).
And, described computing cross-correlation device can be a kind of digital computing cross-correlation device as shown in Figure 5, and by at least one group 16 Parallel Digital switch SW Bank1, one group of sixteen bit shift register SR that is used to control 16 Parallel Digital switches, one group of plural bit register group RegBank that controls and be connected by Parallel Digital switch SW Bank1 with input signal, one group is used to realize that value is 0,1,-1 condition code and input signal mutually 16 grades of shift registers of multiplication to (Cx0, Cx1, x is 0 to 15 integer value), one group be connected with adder by shift register to (Cx0, Cx1) Kong Zhi switch SW Bank2, one group of adder ADDB of being connected with control switch SWBank2 constitutes, and the initial condition that is used to control the sixteen bit shift register SR of 16 Parallel Digital switch SW Bank1 can be made as 1000000000000000; Be used to realize value be 0,1 ,-1 condition code with input signal mutually 16 grade of 2 bit shift register of multiplication (Cx0, initial condition Cx1) can be made as (0,0) (1,0) (0,0) (0,0) (0,0) (1,0) (0,0) (0,0) (1,0) (0,0) (0,1) (0,1) (0,1) (0,0) (1,0) (0,0).And the right shift motion of shift register SR and shift register is by having the clock signal control of same frequency with input signal.
Above process has only been introduced the circuit implementation method of the computing cross-correlation of short condition code and input signal, for the computing cross-correlation of long condition code, only need to change the short condition code in the foregoing circuit into long condition code and corresponding circuit unit number once adjusted to utilize similar circuit configuration to realize with input signal.
The Short Symbol value of chart 1 IEEE802.11a standard code
| Re | ?0.002 | -0.079 | -0.013 | 0.000 | -0.013 | -0.079 | ?0.002 | 0.046 | -0.132 | -0.013 | ?0.143 | ?0.092 | ?0.143 | -0.013 | -0.132 | ?0.046 |
| Im | -0.132 | -0.013 | ?0.143 | ?0.092 | ?0.143 | -0.013 | -0.132 | ?0.046 | ?0.002 | -0.079 | -0.013 | ?0.000 | -0.013 | -0.079 | ?0.002 | ?0.046 |
The quantized value of the Short Symbol value of chart 2 IEEE802.11a standard codes
| ??# | ???0 | ??1 | ??2 | ??3 | ??4 | ??5 | ??6 | ??7 | ??8 | ??9 | ??10 | ??11 | ??12 | ??13 | ??14 | ??15 |
| ??Re | ???0 | ?-1 | ??0 | ??0 | ??0 | ?-1 | ??0 | ??0 | ?-1 | ??0 | ??1 | ??1 | ??1 | ??0 | ?-1 | ??0 |
| ?Im | ??-1 | ??0 | ??1 | ??1 | ??1 | ??0 | ?-1 | ??0 | ??0 | ?-1 | ??0 | ??0 | ??0 | ?-1 | ??0 | ??0 |
The Long Symbol value of chart 3 IEEE802.11a standard codes
| ????# | ????Re | ????Im | ??# | ??Re | ????Im |
| ????0 | ??0.012 | ??-0.098 | ?16 | ?0.119 | ???0.004 |
| ????1 | ??0.092 | ??-0.106 | ?17 | -0.022 | ??-0.161 |
| ????2 | ?-0.092 | ??-0.115 | ?18 | ?0.059 | ???0.015 |
| ????3 | ?-0.003 | ??-0.054 | ?19 | ?0.024 | ???0.059 |
| ????4 | ??0.075 | ???0.074 | ?20 | -0.137 | ???0.047 |
| ????5 | ?-0.127 | ???0.021 | ?21 | ?0.001 | ???0.115 |
| ????6 | ?-0.122 | ???0.017 | ?22 | ?0.053 | ??-0.004 |
| ????7 | ?-0.035 | ???0.151 | ?23 | ?0.098 | ???0.026 |
| ????8 | ?-0.056 | ???0.022 | ?24 | -0.038 | ???0.106 |
| ????9 | ?-0.060 | ??-0.081 | ?25 | -0.115 | ???0.055 |
| ????10 | ??0.070 | ??-0.014 | ?26 | ?0.060 | ???0.088 |
| ????11 | ??0.082 | ??-0.092 | ?27 | ?0.021 | ??-0.028 |
| ????12 | ?-0.131 | ??-0.065 | ?28 | ?0.097 | ??-0.083 |
| ????13 | ?-0.057 | ??-0.039 | ?29 | ?0.040 | ???0.111 |
| ????14 | ??0.037 | ??-0.098 | ?30 | -0.005 | ???0.120 |
| ????15 | ??0.062 | ???0.062 | ?31 | ?0.156 | ???0.000 |
The quantized value of the Long Symbol value of chart 4 IEEE802.11a standard codes
| ????# | ????Re | ???Im | ??# | ??Re | ?Im |
| ????0 | ????0 | ??-1 | ??16 | ??1 | ??0 |
| ????1 | ????1 | ??-1 | ??17 | ??0 | ?-1 |
| ????2 | ???-1 | ??-1 | ??18 | ??0 | ??0 |
| ????3 | ????0 | ???0 | ??19 | ??0 | ??0 |
| ????4 | ????0 | ???0 | ??20 | ?-1 | ??0 |
| ????5 | ???-1 | ???0 | ??21 | ??0 | ??1 |
| ????6 | ???-1 | ???0 | ??22 | ??0 | ??0 |
| ????7 | ????0 | ???1 | ??23 | ??1 | ??0 |
| ????8 | ????0 | ???0 | ??24 | ??0 | ??1 |
| ????9 | ????0 | ??-1 | ??25 | ?-1 | ??0 |
| ????10 | ????0 | ???0 | ??26 | ??0 | ??1 |
| ????11 | ????1 | ???0 | ??27 | ??0 | ??0 |
| ????12 | ???-1 | ???0 | ??28 | ??1 | ?-1 |
| ????13 | ????0 | ???0 | ??29 | ??0 | ??1 |
| ????14 | ????0 | ??-1 | ??30 | ??0 | ??1 |
| ????15 | ????0 | ???0 | ??31 | ??1 | ??0 |
Claims (7)
1. synchronization signal detection circuit device, at least comprise a computing cross-correlation device, a correlation peak detector, it is characterized in that, described computing cross-correlation device is a computing cross-correlation device of being made computing cross-correlation by input sample signal and condition code signal, described correlation peak detector is to receive the correlation peak arithmetic unit that detects synchronous head after the cross-correlated signal of described computing cross-correlation device output and predefined family of power and influence's voltage compare, and described its signal output part of computing cross-correlation device is connected with the signal input part of described correlation peak arithmetic unit.
2. synchronization signal detection circuit device according to claim 1, it is characterized in that, described computing cross-correlation device comprises that at least one stack features sign indicating number real part and condition code imaginary part do the computing cross-correlation circuit of computing cross-correlation with input real part or input imaginary part respectively separately, the output of described computing cross-correlation circuit links to each other with at least one group of add circuit respectively, its input of described add circuit links to each other with the quadratic sum computing circuit, and described quadratic sum computing circuit links to each other with the input of peak value detector.
3. synchronization signal detection circuit device according to claim 1 and 2 is characterized in that, described computing cross-correlation device is that a kind of digital-to-analogue is mixed the computing cross-correlation device, and is made of at least one group of sampling value preserving circuit, one group of reverse operational amplifier.
4. synchronization signal detection circuit device according to claim 1 and 2, it is characterized in that, described computing cross-correlation device be a kind of only be 0 to value,-1,1 condition code, and the analog signal of input is carried out the digital computing cross-correlation device of computing cross-correlation after A/D conversion, and by at least one group 16 Parallel Digital switch SW Bank1, one group of sixteen bit shift register SR that is used to control 16 Parallel Digital switches, one group of plural bit register group RegBank that controls and be connected by Parallel Digital switch SW Bank1 with input signal, one group is used to realize that value is 0,1,-1 condition code and input signal mutually 16 grade of 2 bit shift register of multiplication to (Cx0, Cx1, x is 0 to 15 integer value), one group be connected with adder by the switch SW Bank2 of shift register to control, one group of adder ADDB formation that is connected with control switch SWBank2.And the initial condition that is used to control the sixteen bit shift register SR of 16 Parallel Digital switch SW Bank1 can be made as 1000000000000000; 16 grade of two bit shift register to (Cx0, initial condition Cx1) can be made as (0,0) (1,0) (0,0) (0,0) (0,0) (1,0) (0,0) (0,0) (1,0) (0,0) (0,1) (0,1) (0,1) (0,0) (1,0) (0,0), and the right shift motion of shift register SR and shift register is made of the circuit that has the clock signal control of same frequency with input signal.
A device as claimed in claim 1 its detect the detection method of synchronizing signal, it is characterized in that, described method comprises the formula treatment step of the condition code in computing cross-correlation device, the correlation peak detector, condition code and input sample signal, input analog signal and sampling holder being exported analog signal and correlation peak, synchronous head, wherein, the formula of synchronous head signal is:
In the formula, S (t) is synchronizing signal and is made up of M characteristic signal that a is a constant of expression fading channel coefficient, and C (t) is the condition code signal, can be real number or complex signal, and N is the number of condition code signal element; The condition code signal is made up of N code element and formula is:
In the formula, c
i(t) representing length is the code element of T; The code element of characteristic signal and the formula of sampled signal are:
In the formula, s (m) is the complex sampling value of the signal that receives,
Be the conjugate of code element, Re{ }, Im{ } expression real and imaginary part; And described condition code signal is divided into short condition code signal and long condition code signal, and its quantification treatment formula of the real of described short condition code signal and imaginary part is respectively::
Its quantification treatment formula of the real of described long condition code signal and imaginary part is respectively:
6. detection method according to claim 5 is characterized in that, the computing cross-correlation formula of the real part of described short condition code signal and input sample signal is:
7. detection method according to claim 5, it is characterized in that described synchronous head signal is that the gap length of calculating of interval and the formula between a kind of that can be consecutively detected peak value and adjacent peak value is corresponding to by the detected synchronous head signal of correlation peak detector.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011445572A CN100461656C (en) | 2001-12-20 | 2001-12-20 | Synchronous signal detecting circuit device and detecting method of said device detecting synchronous signal |
| AU2002354167A AU2002354167A1 (en) | 2001-12-20 | 2002-12-20 | A synchronous signal detect circuit device of ofdm communication system and a detection method to detect synchronous signal of the device |
| PCT/CN2002/000905 WO2003055125A1 (en) | 2001-12-20 | 2002-12-20 | A synchronous signal detect circuit device of ofdm communication system and a detection method to detect synchronous signal of the device |
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| CNB011445572A CN100461656C (en) | 2001-12-20 | 2001-12-20 | Synchronous signal detecting circuit device and detecting method of said device detecting synchronous signal |
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| CN100461656C CN100461656C (en) | 2009-02-11 |
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| AU (1) | AU2002354167A1 (en) |
| WO (1) | WO2003055125A1 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100361423C (en) * | 2004-05-12 | 2008-01-09 | 北京信威通信技术股份有限公司 | Method for synchronizing down going service code channel in CDMA system of using intelligent antenna |
| CN101039293B (en) * | 2006-03-15 | 2010-06-23 | 华为技术有限公司 | Apparatus, method and receiver for initial timing synchronization in communication system |
| CN101304402B (en) * | 2008-06-30 | 2011-08-31 | 北京海尔集成电路设计有限公司 | Locking method and system for correlation peak value process |
| CN101345576B (en) * | 2008-08-29 | 2012-02-29 | 芯通科技（成都）有限公司 | Method and system for reducing switch vibration of TD-SCDMA repeater |
| CN101304403B (en) * | 2008-06-30 | 2012-04-11 | 北京海尔集成电路设计有限公司 | Method and system for frame synchronization |
| CN103226169A (en) * | 2012-06-12 | 2013-07-31 | 嘉兴联星微电子有限公司 | Square wave detector for wireless wake-up circuit |
| CN103414676A (en) * | 2013-07-25 | 2013-11-27 | 桂林电子科技大学 | Self-adaptation and self-synchronizing TCM-MPPM coded modulation and demodulation communication method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571136B (en) * | 2012-01-29 | 2014-01-22 | 北京航空航天大学 | Correlated peak detection method of double channel pn code acquisition system |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6226336B1 (en) * | 1998-02-20 | 2001-05-01 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and apparatus for detecting a frequency synchronization signal |
| JP3606761B2 (en) * | 1998-11-26 | 2005-01-05 | 松下電器産業株式会社 | OFDM receiver |
| KR100335443B1 (en) * | 1999-06-15 | 2002-05-04 | 윤종용 | Symbol timing and frequency synchronizing device for OFDM signals and method thereof |
| JP2001103033A (en) * | 1999-09-30 | 2001-04-13 | Hitachi Denshi Ltd | Data transmission device |
| US6711221B1 (en) * | 2000-02-16 | 2004-03-23 | Thomson Licensing S.A. | Sampling offset correction in an orthogonal frequency division multiplexing system |
-
2001
- 2001-12-20 CN CNB011445572A patent/CN100461656C/en not_active Expired - Fee Related
-
2002
- 2002-12-20 WO PCT/CN2002/000905 patent/WO2003055125A1/en not_active Application Discontinuation
- 2002-12-20 AU AU2002354167A patent/AU2002354167A1/en not_active Abandoned
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100361423C (en) * | 2004-05-12 | 2008-01-09 | 北京信威通信技术股份有限公司 | Method for synchronizing down going service code channel in CDMA system of using intelligent antenna |
| CN101039293B (en) * | 2006-03-15 | 2010-06-23 | 华为技术有限公司 | Apparatus, method and receiver for initial timing synchronization in communication system |
| CN101304402B (en) * | 2008-06-30 | 2011-08-31 | 北京海尔集成电路设计有限公司 | Locking method and system for correlation peak value process |
| CN101304403B (en) * | 2008-06-30 | 2012-04-11 | 北京海尔集成电路设计有限公司 | Method and system for frame synchronization |
| CN101345576B (en) * | 2008-08-29 | 2012-02-29 | 芯通科技（成都）有限公司 | Method and system for reducing switch vibration of TD-SCDMA repeater |
| CN103226169A (en) * | 2012-06-12 | 2013-07-31 | 嘉兴联星微电子有限公司 | Square wave detector for wireless wake-up circuit |
| CN103226169B (en) * | 2012-06-12 | 2015-07-08 | 殷明 | Square wave detector for wireless wake-up circuit |
| CN103414676A (en) * | 2013-07-25 | 2013-11-27 | 桂林电子科技大学 | Self-adaptation and self-synchronizing TCM-MPPM coded modulation and demodulation communication method and system |
| CN103414676B (en) * | 2013-07-25 | 2016-08-24 | 桂林电子科技大学 | A kind of self adaptation self synchronous TCM-MPPM coded modulation demodulation communication means |
Also Published As
| Publication number | Publication date |
|---|---|
| AU2002354167A1 (en) | 2003-07-09 |
| CN100461656C (en) | 2009-02-11 |
| WO2003055125A1 (en) | 2003-07-03 |
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