CN1425157A - Dual-mode processor - Google Patents

Dual-mode processor Download PDF

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Publication number
CN1425157A
CN1425157A CN00818611A CN00818611A CN1425157A CN 1425157 A CN1425157 A CN 1425157A CN 00818611 A CN00818611 A CN 00818611A CN 00818611 A CN00818611 A CN 00818611A CN 1425157 A CN1425157 A CN 1425157A
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China
Prior art keywords
processor
memory
circuit
data
pattern
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CN00818611A
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Chinese (zh)
Inventor
B·坎戴罗
E·J·史普朗克
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Arris Technology Inc
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General Instrument Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2105—Dual mode as a secondary aspect

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Storage Device Security (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

A multiple-mode processing circuit, such as a dual-mode processor (5), operates in at least first and second modes according to a switch (10). When a mode is active, data transfer between the processor and a respective memory occurs. Thus, instructions from the memory can be executed at the processor, and the results can be stored in the respective memory. For example, first and second memories (14, 54) may be provided for the first and second modes (10, 50), respectively. The memories are separate, and no data transfer can occur between the memories directly or via the processor. The first mode (10) may be a secure mode for secure processing operations, such as providing conditional access for television programming services at a set-top subscriber terminal. The second mode (50) may be a non-secure mode, such as for providing any other application at the terminal, e.g., program guide, shop at home service, etc. In one embodiment, a data bus is provided for time-multiplexed transfer of data between the processor and the respective memories. In another embodiment, switching of individual internal registers and external elements such as address and data latches, is provided.

Description

Dual-mode processor
Background of invention
The present invention relates to have the circuit of the such multimode processors of dual-mode processor for example.This processor is particularly suitable for providing secure access control for subscriber's TV network in digital terminal.
In existing market, exist the cost that pressure economically goes to increase function and reduces consumer's electronic product.Situation is like this especially---also to claim integrated receiver-code translator (IRD) or subscriber's terminal---for set-top box (set-top) terminal, and this terminal receives and the decoding TV signal, shows for TV.This signal can be transmitted by satellite through cable installation, or transmits by terrestrial broadcast system.
A driving force of integrated cost is the number that constitutes the assembly of product.A method that reduces assembly is that function merges, and the function of soon being finished by two or more integrated circuit (IC) usually is put among the IC to be finished.This is applicable to the chip with flush bonding processor.For example, can obtain having the two chip of internal memory and CPU (central processing unit) (CPU) now.
In addition, increasing functional other method is more effectively to utilize circuit unit.The clock speed that microprocessor is carried out constantly promotes, and makes that the assembly with similar number can be finished more multiprocessing in the identical time.Therefore can make product have more performances and the consumer is had response more rapidly.The clock speed that increases also makes single-processor be handled multiple application program.
By being incorporated in the application program of moving in a plurality of processors, it can be moved in single-processor, promptly make the functional increase of single circuit and component count reduces.Yet merging application program is not trival matters, particularly for the application program of flush bonding processor, because when merging application program, operating system, code structure, interrupt timing and process interaction interdependence etc. usually all will change.Usually must all redesign the embedded code that pooling function is arranged.
In personal computer, have multiple application program as the complex operations system of windows system, their generally operations simultaneously and not disturbing mutually.But personal computer environment has many standards at software and hardware aspect.The programmer wishes to utilize the operating system service routine and goes to write application program with common hardware.Yet built-in application program both can't be benefited in standard operation system usually and also can't have been benefited from the typical hardware platform.Even but in the PC operating system environment of exploitation maturation, application program also can break down, thereby cause total system to be shut down or ＂ hang-up (hang) ＂, thereby must restart total system or total system is resetted.Also may make and write bad program or rewritten Another Application program in the internal memory as the rogue program of ＂ virus ＂.These Viruses can harm the storage administration subregion that operating system can be used usually.
Operating system has been developed protection mechanism, and to prevent the program with the user application mode operation, unlikely (privileged) system information of will speciallyying permit is rewritten.The frequent use one of these systems is called the logical circuit of memory management unit (MMU), and with the master routine that prevents to carry out in internal memory, the malicious application that is run on user model is rewritten.In this kind system, at the same time between the application program of Zhi Hanging and unprotect.In addition, global space is shared by all tasks, thereby avoids the unnecessary repetition of system service routine, and helps shared data and Interrupt Process.In addition, no matter program is with which kind of mode operation, but the equal structure of access as storehouse.Application code should be accessed to rudimentary general-purpose register and the special register that master routine is using.And this kind application program should can read the system file that has stored.
Therefore, if can provide a method, merge each independently built-in application program with easy method, and need not redesign code, then very desirable.
One safer mechanism if can be provided so that independently each group program in microprocessor system, do not disturb execution each other mutually, then more excellent.
This system should provide a dual-mode processor with safe and non-safe handling pattern.
This system should implement at the user terminal in the TV network.
The invention provides a system with above-mentioned and other advantage.
Summary of the invention
A kind of multi-mode treatment circuit as dual-mode processor, can run on first and second pattern at least according to a switch.When the pattern of activation, between processor and corresponding memory data transmission takes place.So, can carry out instruction at this processor, and its result can be stored in the respective memory from storer.For example, first and second storer can supply the usefulness of first and second pattern respectively.Data transmission can directly not take place for independently in described storer between storer or via processor.
First pattern can be one and is used for the safe mode that security procedure is operated, as providing access with good conditionsi in set-top box subscriber terminal for TV programme arrangement service.Second pattern can be non-security mode, for example provides other application program in terminal, as program guide, homeshopping service etc.
In one embodiment, data bus is set, for the usefulness of the multiplexed transmission of the sequential of the data between processor and the respective memory (time-multiplexed transfer).In another embodiment, be arranged on the conversion of carrying out between indivedual internal registers and outer member such as address and the data latch.
Processor can be changed between each pattern according to different mechanisms, and mechanism comprises the fixed ratio of clock period, the fixed ratio of performed instruction in processor, and the respective priority of each pattern.
In addition, first and second pattern can have different separately operating system.
The accompanying drawing schematic illustration
Figure l represents the total figure according to double mode treatment circuit of the present invention.
Fig. 2 represents the dual-mode processor that has the bus multiplex electronics according to of the present invention.
Fig. 3 represents the dual-mode processor that has a switch of controlling external module respectively according to of the present invention one.
Fig. 4 represents the switch that is used to select first and second pattern of dual-mode processor according to of the present invention one.
Detailed Description Of The Invention
The present invention relates to a kind of multimode processors, as dual-mode processor.
Fig. 1 represents the total figure according to a dual-mode processor of the present invention.
In one embodiment, dual-mode processor 5 comprises a security system part 10, and a non-security system part 50.Security system part 10 comprises register 12, one random-access memory (ram)s 14, one CPU16, a ROM (read-only memory) (ROM) 18 and a program design control function piece 20.But RAM14 storage safe code and key for example are used to be provided at the visit of having ready conditions that STB terminal carries out.Non-security system 50 comprises register 52 and RAM54.
Processor 5 provides two functions (being safety and non-safety function), definitely isolates between the function.That is there is its RAM14 and 54 separately in system 10,50, thereby any of security system 10 can not arrive RAM54 by (for example leaking), and non-security system 50 any one can be by arriving RAM14.Therefore and since can not be by non-security system 50 direct---or through CPU16---fetch or provide data from security system 10 to security system 10, the data among the RAM14 of security system 10 can keep safety.
Hardware time slicing device (time slicer) 70 is a switching device shifter, it provides for 50% work period by distributing the CPU16 half the time, be used to handle the data from the RAM14 of security system 10, second half time then is used for the data from the RAM54 of non-security system 50.Under 50% work period situation, the processor of a 50MHz can be considered the processor of two 25MHz.Attention can be used alternatingly a converter (commutator).
In addition, can there be different operating system in each system 10 and 50.
Fig. 2 represents the dual-mode processor that has the bus multiplex electronics according to of the present invention.
It is consistent each other in each figure to number identical assembly.
Dual-mode processor 100 comprises an internal data bus 105, one instruction queue 110, one command decoder and machine cycle scrambler 115, and timing and logic control functional block 120, this timing logic control function 120 comprises program design mode data bus, maintenance, interrupts, waits, writes synchronously, controls clock and other control function.
Still have data buffer 125, program schema selector switch 130, interrupt control 135 and pattern timing function piece 140.As shown in the figure, the present invention reuses some content register, makes when two stand-alone mode operations, can use resetting of processor.Program schema selector switch 130 makes and can switch between two modes.
Registers group multiplexer 150 comprises two groups of registers.The registers group that is used for first pattern (pattern ＂ A ＂) of dual-mode processor 100 comprises general-purpose register 160, modifier register 162, stack pointer/return address register 164, programmable counter 166, storage administration register 168, director cache register 170 and interrupt control register 172.
In like manner, (the pattern ＂ B ＂) registers group that is used for second pattern of dual-mode processor 100 comprises general-purpose register 180, modifier register 182, stack pointer/return address register 184, programmable counter 186, storage administration register 188, director cache register 190, and interrupt control register 192.
Still have an address buffer 194 and a memory set multiplexer 195, wherein memory set A197 is used for first pattern, and memory set B198 is used for second pattern.
In the multiplexed embodiment of this bus, during each pattern, data are carried out the sequential multipath transmission on bus 105.
Fig. 3 represents the dual-mode processor according to control external module of the present invention.This figure shows and utilizes Mode A/B and from the example of the inside and outside IC of switching to, this IC for example is a dual-mode processor setting special IC (ASIC) thereon.Utilize Mode A/B address space can be cut apart.Here, each internal register all is switched, and in the embodiment shown in Figure 2, has then used the bus multiplex electronics.
Circuit shown in 300, comprises dual-mode processor 305 and some external modules usually, comprises address latch A (350), B (352) and data latches A (354) and B (356).Processor mode A have instance port 1 (358) ... .., port N (362), processor mode B have instance port 1 (360) ... .., port N (364).Also have storer A (197) and storer B (198).
Dual-mode processor 305 comprises instruction decode and machine cycle scrambler 115, Mode A/B timing converter 310 (see the conversion among Fig. 4 describe in detail), address generator 315 and 317, instruction pipelining 320 and 322, data register 325 and 327, buffer 160 and 180, Cache 170 and 190 and memory management unit (MMU) 168 and 188.Memory management unit (MMU) 168 and 188 provides virtual address to the conversion between the physical address.
The data of storer and operation part can be limited.In addition, can have control register, it makes superuser be permitted the different memory set of moving with user model of application program access selectively.
Path 380 is carried one Mode A/B and is selected signal, and it is to be provided by Mode A/310 of B timing converters (timer switcher), in order to indicate at present with which kind of mode operation.
Address generator 315,317 provides storage address to each address latch 350,352, and it latchs the address that is used for storer 197,198 read/write operations respectively.
325,327 pairs of data latchs 354,365 of data buffer and port 358,360 ... .., port 362,364 send data and receive data from it.
The present invention allows to move independently two groups or many groups program by single microprocessor, independent fully and 100% isolation between each group program.For ease of discussing, we define independently package ＂ A ＂ and ＂ B ＂ respectively, but this notion should be easy to extend to other independently package.The program of a package can't be visited the program of another package, also can't influence the program implementation of another package.Can think that each group program has its oneself operating system, moves each different application program simultaneously.The operating system of a package and application program can't be disturbed another package.
In addition, even write, also can't make the operating system of a package or application program read other program of moving in another package, or understand the details of other program of moving in another package by malice.
By making package A and B sharing functionality hardware, as command decoder and machine cycle coding circuit 115, and regularly and control logic circuit 120, promptly more effectively having utilized the zone of IC chip, this IC chip for example is VLSI (very large scale integrated circuit) (VLSI) chip.Particularly, merged and from system, subdued a whole microprocessor, can reduce the number of all components, thereby realize the remarkable reduction of cost by operation with A group and B group program.
Independent two groups of (or many groups) programs in the processor operation were worked on single processor together before the present invention can make, and changed or do not have a change in two groups of original set programs any one is all very few.This causes the significantly saving on code development time and cost.In addition, even with two groups of program combinations, form have combination function than large program, and this program can be carried out by the processor of same type, what this was new still needs to check and debugging than large program comprehensively.The present invention by make two than small routine as existing in the past, and avoided this problem.
In a possible embodiment, batch processing can be thought to carry out the ＂ security code ＂ of encryption routine, this routine is finished accessing control function in set-top box.This group program can not disturbed by the program of carrying out in the non-safe ＂ package of another ＂.In set-top box, this just makes and each master microprocessor can be incorporated in the device.
＂ access control ＂ means the algorithm of carrying out in ＂ safety ＂ processor, processor is in order to determine the whether authorized specific program of watching of a code translator.This program may need to order or need the user to be bought and distribute.
Fig. 4 represents to be used to select the Mode A of dual-mode processor or the switch of B according to the present invention.
Switch 400 is that a marginal edge triggers D flip-flop.Trigger 405 via line 410 receive master clock signal, and output mode A selects signal on circuit 420, or output mode B selects signal on circuit 430.Master clock signal can be via circuit 440 as other purpose.
Processor needs a switchgear, is switched so that organize at the operation of batch processing and another between operation of program.Can be with timing as the means of between set of applications, switching.Below be several selections:
1. the fixed ratio of clock period.As set 50～50%, then can be used for organizing A (Mode A), and whenever can be used for organizing B (Mode B) program every one-period in addition every a clock cycle.As be set at 80～20%, then organize A and will carry out for four clock period, and group B carries out one-period.
2. the fixed number in continuous clock cycle.As be set at 50～50%, then organize A and can use ten continuous clock cycles, and group B uses ten continuous clock cycles.As be made as 80～20%, then organize A and can use continuous 16 clock period, and the B group is used four continuous clock cycles.
3. be performed the fixed ratio of instruction.As setting 50～50%, group A and group B carry out every an instruction.As set 80～20%, and group A carries out four instructions, and group B carries out an instruction.
4. the fixed number of continual command.As set 50～50%, then organize A and can carry out continuous ten instructions, and group B carries out ten continual commands.As set 80～20%, then organize A and can carry out continuous 16 instructions, and group B carries out continuous four instructions.
5. guaranteeing also may to implement dynamic clock or command assignment under minimum clock or the condition execution instruction.For the process of an execution low priority routine, may abandon the clock or the instruction cycle of some and give other process.When calling a high priority process as an interruption, (pre-empted) process of then trying to be the first can be returned its clock of abandoning or instruction cycle.
Following selectivity embodiment also can be considered:
1. group A and group B circuit can be triggered by clock simultaneously.The clock and instruction cycle has been guaranteed the access for any shared resource.In above-mentioned situation, shared resource is; Command decoder and machine cycle scrambler 115, and timing and control circuit 120.They all observe a strict clock and command assignment mechanism.
2. storage space can separate with organizing between the B program fully at group A.
3. can require CPU, make minimum timing be damaged never.This may must have extra repetition hardware.Or by with the priority of next instruction to another group program, also can finish a tediously long instruction simply.
Result of the present invention is, must duplicate any data that relate to the context of content that microprocessor just carrying out and position or claim state in storer, for use in each package independently of carrying out in this microprocessor system.
Processor of the present invention has following structure, and it provides storer and context (context) is provided therefrom system: storehouse and stack pointer 164 and 184 or at least one contain register, general- purpose register 160 and 180, programmable counter 166 and 186, CPU status register, MMU control register 166 and 168, high-speed cache control register 170 and 190, various I/O register, and the interruptable controller of return address.In addition, the inside of system and external RAM and ROM are all changeable.This to the switchable memory group conceptive similar.If the highest significant position of address is the function of the in the past performed pattern (A or B) of package, be high then when it, upper (upper) memory set 197 can supply the usefulness of package A, and when it was low level, the next (lower) memory set 198 can be for the usefulness of package B.
Have internal cache as microprocessor system, whether then it needs or does not need this structure of repetition, can directly be decided by CPU reads on this storer.Any high-speed cache control register all needs repetition.Because each package can realize its more efficient use by repeating cache structure all in different storage space operations.Owing to will carry out two groups of independently programs, can realize higher cache hit rate by the cache memory that repeats.
Each package has its oneself boot.But this program setup parameter, this parameter are for example discerned and how to be organized code is that low priority reaches how to organize code be high priority, and it may need whole distribution numberings of clock period.
For making TV set-top box terminal (for example, code translator) exempt the demand of handling access control and encryption with separate processor, the present invention is very useful.Usually the processor in order to the operation code translator can move this function equally, and utilizes this dual-mode nature.
Select on the purposes of the present invention, it is possible testing some unknown code.For example, the Internet makes and can download the many little Java application routine or ＂ applet (applet) ＂ in unknown character and source from various web websites.Two-processor system of the present invention (for example being implemented in the set-top box of a WWW compatibility) can provide protection when this code of operation.This can be to make to avoid a method interfering with each other between the application program.
In another was selected, available the present invention realized one type fire wall, for example handled the space in order to isolated data.
Also have one to select, available the present invention realizes fault-tolerant computer, for example the personal computer of unlikely inefficacy when primary processor collapses.
This shows, the invention provides double mode or other multimode processors.This processor executes instruction by distributing its time, and has realized timesharing (time-share) between each process.In a specific embodiments, this processor comprises safe and non-security system, and it arrives independently each storer with data storage, and from these memory search data.This processor can be in order to provide the visit of having ready conditions to TV programme arrangement service.
Although in conjunction with various specific embodiments the present invention has been described, in addition, skilled person in the art will appreciate that and still can carry out many modifications and change, and unlikelyly run counter to the spirit and scope that claims of the present invention propose it.
For example, the present invention is suitable for the in fact network of any kind, comprises wired or satellite television broadcasting communication network, Local Area Network, city net (MAN), wide area network (WAN), the Internet, corporate intranet and combination thereof.
In addition, can use known computer hardware, firmware and/or software engineering to implement the present invention.

Claims (17)

1. multi-mode treatment circuit comprises:
At least with the processor of first and second mode operation;
Be used for the timing device that switches between first and second pattern at least described;
When described processor is in this first pattern, provides data to this processor and receive the first memory of data from this processor;
With the second memory that described first memory is isolated, when described processor was in second pattern, this second memory provided data to this processor and receives data from this processor;
Respond the device of described timing device, be used to manage between described processor and this first memory and the data transmission between described processor and this second memory.
2. circuit as claimed in claim 1, wherein:
Described first pattern is a safe mode, be used for safe processing operation, and described second pattern is a non-security mode, is used for non-safe processing operation; And
Described management devices can prevent that data from transferring to this first memory from described second memory, and data transfer to this second memory from described first memory.
3. circuit as claimed in claim 2, wherein:
Described safe handling operation comprises for TV programme arrangement service provides access with good conditionsi.
4. TV set-top box terminal (top-setterminal) that comprises as circuit as described in the claim 3.
5. circuit as claimed in claim 1, wherein:
Described management devices comprises a data bus, and this data bus is used between described processor and this first memory and the multiplexed transmission of sequential (time-multiplexed transfer) of carrying out data between described processor and this second memory.
6. circuit as claimed in claim 5, wherein:
Described processor and this data bus are arranged in the integrated circuit (IC).
7. circuit as claimed in claim 1, wherein:
Described management devices comprises first and second register, and it is activated to respond between described processor and this first memory and the conversion of the described data transmission between described processor and this second memory.
8. circuit as claimed in claim 7, wherein:
Described processor and described first and second registers are arranged in the integrated circuit (IC).
9. circuit as claimed in claim 8, wherein:
Described first and second memory bit is in the outside of described IC; And
Described management devices comprises first and second latch, and it is in the outside of described IC, and it is activated to respond the conversion of the described data transmission between the described processor and second memory between described processor and this first memory.
10. circuit as claimed in claim 1, wherein:
Described timing device is according to the fixed ratio of clock period, and switches described processor at least between first and second pattern described.
11. circuit as claimed in claim, wherein:
Described timing device is according to the fixed ratio in the performed instruction of described processor, and switches described processor at least between first and second pattern described.
12. circuit as claimed in claim 1, wherein:
Described timing device is according to described first and second pattern at least priority separately, and switches described processor at least between first and second pattern described.
13. circuit as claimed in claim 1, wherein:
Described first and second pattern has different separately operating system.
14. circuit as claimed in claim 1, wherein:
First and second application program responds described first and second storer respectively, to carry out described first and second pattern respectively.
15. circuit as claimed in claim 14, wherein:
Described first and second application program is (disparate) that separates.
16. multi-mode treatment circuit as claimed in claim 1, wherein:
Described first and second group program is independently of one another, and responds described first and second storer respectively, to carry out described first and second pattern respectively.
17. multi-mode treatment circuit as claimed in claim 1, wherein:
Described management method can prevent that data from transmitting between described first and second storer.
CN00818611A 1999-12-23 2000-12-19 Dual-mode processor Pending CN1425157A (en)

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