CN1414625A - Manufacturing method of flash storage having separated floating grid and its structure - Google Patents
Manufacturing method of flash storage having separated floating grid and its structure Download PDFInfo
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- CN1414625A CN1414625A CN 01136793 CN01136793A CN1414625A CN 1414625 A CN1414625 A CN 1414625A CN 01136793 CN01136793 CN 01136793 CN 01136793 A CN01136793 A CN 01136793A CN 1414625 A CN1414625 A CN 1414625A
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Abstract
A preparing method of flash storage with separation floating grid provides substrate and an oxide layer and a sacrifice layer of patternization are formed on the substrate in sequence, and then to carry out the ion planting in step by using patternization sacrifice layer as a mask for forming shallow doping source/source of drain electrode/drain electrode in the substrate at two sides of the sacrifice layer. Two conductors gap walls are formed at the side wall of patternization sacrifice layer after the partial patternization sacrifice layer is removed by isotropic radiation etching, and then the remained gap walls of conductor are two floating grids after the oxide layer except that at conductor gap wall, and the patternization sacrifice layer is removed out, subsequently the media layer and the control grid are formed on the substrate in sequence.
Description
Technical field
The invention relates to a kind of manufacture method and structure thereof of internal memory, and particularly relevant for a kind of flash memory making method and structure thereof with separated floating grid (splitfloating gate).
Background technology
Read-only memory has can preserve data characteristic, thereby be subjected to using widely, read-only memory comprises mask ROM (Mask ROM), programmable read only memory (Programmable ROM, PROM), Erasable Programmable Read Only Memory EPROM (ErasableProgrammable ROM, EPROM), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, EEPROM) and flash ROM (Flash ROM).
In read-only memory, that Erasable Programmable Read Only Memory EPROM has is able to programme, still can preserve the advantage of data after can wiping and cut off the power supply, can preserve data and can be for needs with the equipment of the Data Update of being preserved, for example be basic input output system (the Basic Input Output System in personal computer and the electronic equipment, BIOS), be a kind of memory devices of extensive employing.And flash memory especially wherein, have that volume is little, power consumption is low, can be in circuit (in-circuit) carry out the advantage that electricity programming and electricity are wiped, and the mode that adopts piece (Block by Block) to wipe during because of its data erase (Erasing), having more the fast advantage of service speed, therefore is the main direction of research and development in the future.
Figure 1 shows that the generalized section of memory cell (Memory Cell) structure of known a kind of flash memory.This flash memory has a storehouse grid structure (Stacked Gate Structure) as shown in Figure 1, this storehouse grid structure is arranged on the substrate 100, is formed by tunnel oxide (tunneling oxidelayer) 102, floating boom (Floating Gate) 104, dielectric layer (Dielectric Layer) 106 and 108 storehouses of control gate (Control Gate) in regular turn.And, in the substrate 100 of storehouse grid structure both sides, be provided with source electrode 110 and drain 112.
The mode of above-mentioned flash memory stores data adopts the storing mode of one of a memory cell (1 Cell, 1 Bit), just in a memory cell structure, with one data storing in the floating boom of memory cell structure.Yet along with increasing gradually of memory devices integrated level and dwindling gradually of size, the storing mode that known this kind memory cell is will be subjected to the restriction of design rule, makes the integrated level of memory devices be difficult for the raising of continuation.
Summary of the invention
Therefore, the invention provides a kind of flash memory making method and structure thereof with separated floating grid, in a memory cell, form a pair of floating boom disconnected from each other, can be with the mode storage data of two of memory cell (1 cell, 2 bit), thus the storage volume of memory devices and the integrated level that improves device can be increased.
The invention provides a kind of flash memory making method with separated floating grid, this manufacture method provides a substrate, forms oxide layer and patterned sacrificial layers again on substrate in regular turn; Then, be that mask carries out the ion implantation step with the patterned sacrificial layers, in the substrate of sacrifice layer both sides, to form source/drain electrode with shallow doped source/drain electrode; Then, isotropic etching forms two conductor clearance walls in the sacrificial patterned sidewall after removing partially patterned sacrifice layer again; Fully remove sacrificial patterned and conductor clearance wall in addition oxide layer, so that the conductor clearance wall that stay as two floating booms thereafter; Afterwards, on substrate, form dielectric layer and control gate in regular turn.
The invention provides a kind of structure with flash memory of separated floating grid, this structure comprises substrate, source electrode, drain electrode, tunnel oxide, a pair of first floating boom disconnected from each other and second floating boom, dielectric layer and control gate at least.Wherein source electrode is arranged in the substrate respectively with drain electrode.And first floating boom be arranged on the part source electrode with the part substrate on, second floating boom is arranged in part this drain electrode and on the part substrate.Tunnel oxide then is arranged at this between floating boom and source electrode and the drain electrode.Dielectric layer is arranged on first floating boom, second floating boom and the substrate, and control gate is arranged on the dielectric layer.
The programming of a kind of flash memory with separated floating grid of the present invention and the method that removes, exploitable channel hot electron injection method (channel hot electron injection, CHEI) programme, and (negative gate channel erase NGCE) wipes to utilize negative-grid channel erase method.
In sum, advantage of the present invention is to form pair of separated formula floating boom in a memory cell, can carry out the programming of two bit data in a memory cell and wipes.Therefore, the storage volume of memory devices can be increased, and the integrated level of memory devices can be improved.
Description of drawings
Fig. 1 illustrate is the generalized section of the memory cell structure of known a kind of flash memory;
Fig. 2 A to Fig. 2 G illustrate is the generalized section of the manufacturing process of the flash memory that has separated floating grid according to a preferred embodiment of the present invention a kind of;
Fig. 3 A is depicted as the generalized section that the flash memory with separated floating grid of the present invention uses the channel hot electron injection method to programme;
The schematic diagram that Fig. 3 B illustrate uses negative-grid channel erase method to wipe for the flash memory with separated floating grid of the present invention.Label declaration:
100,200: substrate 102,202a, 202b: tunnel oxide
104: floating boom 106,216: dielectric layer
108,218: control gate 110,206: source electrode
112,208: drain electrode 202: oxide layer
204,204a: sacrifice layer 210: shallow doped source
212: shallow doped-drain 214: conductor layer
214a, 214b: conductor clearance wall (floating boom)
Embodiment
The flash memory making method with separated floating grid of preferred embodiment of the present invention is shown in Fig. 2 A to Fig. 2 G.
At first, please refer to Fig. 2 A, a substrate 200 is provided, form oxide layer 202 on substrate 200, wherein the material of oxide layer 202 for example is a silica, and the method that forms oxide layer 202 for example is to use thermal oxidation method.Then, on oxide layer, form one deck patterned sacrificial layers 204, wherein the material of sacrifice layer 204 for example is a silicon nitride, and the method that forms sacrifice layer 204 for example is to form layer of material layer (not indicating) on oxide layer 202, and the method through lithography forms patterned sacrificial layers 204 again.
Then, please refer to Fig. 2 B, in substrate 200, form source electrode 206 and drain 208, wherein form source electrode 206 and 208 the method for draining for example is to be mask with sacrifice layer 204, carry out the deep ion implantation step, in the substrate 200 of sacrifice layer 204 both sides, to form source electrode 206 and to drain 208.Then, in substrate 200, form distinctly by the source electrode 206 and 208 shallow doped source 210 and the shallow doped-drain 212 that extend to sacrifice layer 204 down either side that drain.Wherein form the method for shallow doped source 210 and shallow doped-drain 212, for example be to be mask distinctly with sacrifice layer 204, distinctly carry out inclination angle shallow ion implantation step, with formation out of the ordinary and source electrode 206 and drain and 208 be connected, and distinctly extend to the shallow doped source 210 and the shallow doped-drain 212 of sacrifice layer 204 down either side.
Then, please refer to Fig. 2 C, iso removal partial sacrifice layer 204 is to form undersized sacrifice layer 204a.The method of wherein removing partial sacrifice layer 204 for example is to use the wet etching with hot phosphoric acid etch.In this step, remove the purpose of partial sacrifice layer 204, in the source/drain electrode and shallow doped source/drain electrode partly that is to make the formed floating boom of subsequent step can distinctly be positioned at part.
Then, please refer to Fig. 2 D, on substrate 200, form the conformal conductor layer 214 of one deck.Wherein the material of conductor layer 214 for example is a polysilicon, and the method for its formation for example is a chemical vapour deposition technique.
Then, please refer to Fig. 2 E, form conductor clearance wall 214a and conductor clearance wall 214b in sacrifice layer 204a both sides, wherein conductor clearance wall 214a is positioned at the top of part source electrode 206 and shallow doped source 210, and conductor clearance wall 214b is positioned at the top of part drain electrode 208 and shallow doped-drain 212.The method that forms conductor clearance wall 214a and conductor clearance wall 214b for example is to eat-back conductor layer 214 with the anisotropic etching method.
Then, please refer to Fig. 2 F, remove sacrifice layer 204a fully, wherein remove sacrifice layer 214 methods and for example be to use wet etching with hot phosphoric acid etch.Then, the oxide layer 202 outside removal conductor clearance wall 214a and the conductor clearance wall 214b.The method of wherein removing partial oxidation layer 202 for example is to use hydrofluoric acid (HF)/buffer oxide etch liquid (Buffer Oxide Etchant, wet etching BOE).After removing sacrifice layer 204a fully and removing partial oxidation layer 202, conductor clearance wall 214a that be left behind and conductor clearance wall 214b then become floating boom 214a and floating boom 214b, and residual oxide layer then distinctly becomes tunnel oxide 202a and the tunnel oxide 202b of floating boom 214a and floating boom 214b.
Because in the step of Fig. 2 C, carried out waiting the tropism to remove the step of partial sacrifice layer 204, formed floating boom 214a can be positioned on part source electrode 206 and the shallow doped source 210 of part, and floating boom 214b can be positioned on part drain electrode 208 and the shallow doped-drain 212 of part, just floating boom 214a, 214b can distinctly link to each other with shallow doped source 210 and shallow doped source 212, therefore when operation, can control channel is opened, and be carried out the programming of memory devices and wipe.
Then, please refer to Fig. 2 G, on substrate 200, form the conformal dielectric layer 216 of one deck, wherein the material of dielectric layer 216 for example is a silica, the method that forms dielectric layer 216 for example is a chemical vapour deposition technique, and be covered in this dielectric layer 216, can cover the leading edge of shallow doped source 210 and shallow doped-drain 212 opposite sides floating boom 214a, 214b opposing sidewalls.Then, form control gate 218 on dielectric layer 216, wherein the material of control gate 218 for example is a polysilicon, and the method for formation for example is a chemical vapour deposition technique.
The structure that the present invention has the flash memory of separated floating grid please refer to Fig. 2 G.
Shown in Fig. 2 G, this structure with flash memory of separated floating grid comprises substrate 200, source electrode 206, drain electrode 208, tunnel oxide 202a, tunnel oxide 202b, a pair of floating boom 214a disconnected from each other and floating boom 214b, dielectric layer 216 and control gate 218 at least.
The programming and the mode that removes that the present invention has the flash memory of separated floating grid please refer to Fig. 3 A and Fig. 3 B.
Fig. 3 A illustrate has the generalized section that the flash memory of separated floating grid uses the hot electron injection method to programme for the present invention.On control gate 218, apply positive voltage so that channel is opened, and the drain electrode 208 apply a voltage with source electrode 206 with the drain electrode 208 formation bias voltages, when source electrode 206 and 208 bias voltage of drain electrode are quite big, on channel, just can produce too much hot electron, and the hot electron of part can pass through tunnel oxide 202b, enter floating boom 214b and be stored in wherein by its edge, and finish the operation of programming.And,, also can rely on the hot electron injection method programme to floating boom 214a by to source electrode 206 and drain and 208 oppositely apply voltage.
The generalized section that Fig. 3 B illustrate uses negative-grid channel erase method to wipe for the flash memory with separated floating grid of the present invention.Store at floating boom 214b under the situation of electronics, apply positive voltage, and on control gate 218, apply enough big negative pressure, make the voltage difference between grid and the source electrode be enough to produce the F-N tunneling effect at source electrode 206.At this moment, electronics can comprehensively pass tunnel oxide 202b by floating boom 214b and enter in the channel, and finishes the operation of wiping.Same, by to the source electrode 206 and 208 counter-rotatings that apply voltage that drain, also can use negative-grid channel erase method that floating boom 214a is wiped.
In sum, advantage of the present invention forms pair of separated formula floating boom in a memory, can be with the mode storage data of two of memory cell, and just in a memory cell, can carry out the programming of two bit data and wipe.Therefore, the memory devices that the known memory cell of comparing is, memory devices of the present invention can improve the storage volume of data, and can improve the integrated level of device.
Though the present invention with a preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, in not breaking away from content of the present invention and scope; when can doing to change and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim book.
Claims (13)
1. flash memory making method with separated floating grid, it is characterized in that: this manufacture method comprises the following steps:
One substrate is provided;
Form an oxide layer and a patterned sacrificial layers in regular turn at this substrate;
With this patterned sacrificial layers is mask, carries out the ion implantation step, to form the source/drain electrode with a shallow doped source/drain electrode in this substrate of these sacrifice layer both sides;
This patterned sacrificial layers of part is removed in etching;
Form two conductor clearance walls at this patterned sacrificial layers sidewall;
Remove this patterned sacrificial layers and this two conductors clearance wall this oxide layer in addition, make this two conductors clearance wall that stays as two floating booms;
On this substrate, form a dielectric layer and a control gate in regular turn.
2. the flash memory making method with separated floating grid as claimed in claim 1 is characterized in that: the method that wherein forms this two conductors clearance wall comprises the following steps:
On this substrate, form a conductor layer;
Eat-back this conductor layer, to form those conductor clearance walls in this patterned sacrificial layers sidewall.
3. the flash memory making method with separated floating grid as claimed in claim 1 is characterized in that: wherein the material of this patterned sacrificial layers comprises silicon nitride.
4. the flash memory making method with separated floating grid as claimed in claim 1 is characterized in that: comprise also that wherein the method for implanting with an inclination angle forms this shallow doped-drain.
5. the flash memory making method with separated floating grid as claimed in claim 1 is characterized in that: wherein the step use wet etching of this patterned sacrificial layers of part is removed in etching.
6. the flash memory making method with separated floating grid as claimed in claim 1 is characterized in that: wherein this two floating boom distinctly be formed in part source/drain electrode and this shallow doped-drain of part on.
7. the flash memory making method with separated floating grid as claimed in claim 1 is characterized in that: wherein cover this dielectric layer of this two floating booms opposing sidewalls, cover the leading edge to this shallow doped-drain.
8. the flash memory making method with separated floating grid as claimed in claim 1 is characterized in that: wherein this dielectric layer is conformal being formed on this substrate and this two floating boom.
9. structure with flash memory of separated floating grid, it is characterized in that: this structure comprises:
One substrate;
An one source pole and a drain electrode are arranged at respectively in this substrate;
One first floating boom and one second floating boom, wherein this first floating boom be arranged on this source electrode of part with this substrate of part on, this second floating boom is arranged at that part this drain electrode is gone up and partly on this substrate;
One tunnel oxide is arranged at this between floating boom and this source/drain electrode;
One dielectric layer is arranged at this on floating boom and this substrate;
One control gate is arranged on this dielectric layer.
10. the structure with flash memory of separated floating grid as claimed in claim 9, it is characterized in that: wherein this source electrode also comprises a shallow doped source, this shallow doped source is positioned at this first floating boom below, and extends to this dielectric layer below that covers this first floating boom sidewall between this two floating boom.
11. the structure with flash memory of separated floating grid as claimed in claim 9, it is characterized in that: wherein this drain electrode also comprises a shallow doped-drain, this shallow doped-drain is positioned at this second floating boom below, and extends to this dielectric layer below that covers this second floating boom sidewall between this two floating boom.
12. the structure with flash memory of separated floating grid as claimed in claim 9, it is characterized in that: wherein this source electrode also comprises a shallow doped source, and this drain electrode also comprises shallow doped-drain, wherein this shallow doped source is below this dielectric layer of this first floating boom sidewall of covering between this two floating boom, and this shallow doped-drain is below this dielectric layer of this second floating boom sidewall of covering between this two floating boom.
13. the structure with flash memory of separated floating grid as claimed in claim 9 is characterized in that: wherein this dielectric layer is conformal being formed on this substrate and this two floating boom.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01136793 CN1271707C (en) | 2001-10-25 | 2001-10-25 | Manufacturing method of flash storage having separated floating grid and its structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01136793 CN1271707C (en) | 2001-10-25 | 2001-10-25 | Manufacturing method of flash storage having separated floating grid and its structure |
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| Publication Number | Publication Date |
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| CN1414625A true CN1414625A (en) | 2003-04-30 |
| CN1271707C CN1271707C (en) | 2006-08-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 01136793 Expired - Fee Related CN1271707C (en) | 2001-10-25 | 2001-10-25 | Manufacturing method of flash storage having separated floating grid and its structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866258A (en) * | 2009-04-20 | 2010-10-20 | 鸿富锦精密工业（深圳）有限公司 | Handwriting input device |
| CN102709295A (en) * | 2012-07-11 | 2012-10-03 | 无锡来燕微电子有限公司 | Non-volatile memory compatible with CMOS (complementary metal oxide semiconductor) logic process and preparation method of non-volatile memory |
| CN102709294A (en) * | 2012-07-11 | 2012-10-03 | 无锡来燕微电子有限公司 | Non-volatile memory for improving data storage time and method for producing non-volatile memory |
-
2001
- 2001-10-25 CN CN 01136793 patent/CN1271707C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866258A (en) * | 2009-04-20 | 2010-10-20 | 鸿富锦精密工业（深圳）有限公司 | Handwriting input device |
| CN101866258B (en) * | 2009-04-20 | 2013-07-03 | 鸿富锦精密工业（深圳）有限公司 | Handwriting input device |
| CN102709295A (en) * | 2012-07-11 | 2012-10-03 | 无锡来燕微电子有限公司 | Non-volatile memory compatible with CMOS (complementary metal oxide semiconductor) logic process and preparation method of non-volatile memory |
| CN102709294A (en) * | 2012-07-11 | 2012-10-03 | 无锡来燕微电子有限公司 | Non-volatile memory for improving data storage time and method for producing non-volatile memory |
| CN102709294B (en) * | 2012-07-11 | 2015-06-17 | 无锡来燕微电子有限公司 | Non-volatile memory for improving data storage time and method for producing non-volatile memory |
| CN102709295B (en) * | 2012-07-11 | 2015-06-17 | 无锡来燕微电子有限公司 | Non-volatile memory compatible with CMOS (complementary metal oxide semiconductor) logic process and preparation method of non-volatile memory |
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| Publication number | Publication date |
|---|---|
| CN1271707C (en) | 2006-08-23 |
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