CN1414613A

CN1414613A - Preparation process of deep submicron integrated circuit Cu barrier

Info

Publication number: CN1414613A
Application number: CN 02137193
Authority: CN
Inventors: 徐小诚; 缪炳有
Original assignee: Shanghai Huahong Group Co Ltd
Current assignee: Shanghai Huahong Group Co Ltd; Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority date: 2002-09-27
Filing date: 2002-09-27
Publication date: 2003-04-30

Abstract

A preparing process for Cu blocking layer of integrated circuit in deep submicron uses the IPVD process to deposite TaSiN as a blocking layer to Cu diffusing and to select Ta as an adjacent blocking layer material of Cu metal. In chemical electroplating of Cu, the alternating electric field and electroplating additives are applied. The heat treatment for Cu with annealing in fast heating and the chemicomechanical polishing for Cu is carried out to grind off the unnecessary Cu metal and blocking layer in addition to connection wire and through hole to realize the Cu interconnection wiring technology of Damascus. The process raises the ability of antidiffusing for Cu and F, improves the sticking ability with Cu metal film and insulation media, is suitable to be used in the interconnection technology of Cu metal and low dielectric material.

Description

The preparation technology of deep submicron integrated circuit Cu barrier

Technical field

The invention belongs to the semiconductor integrated circuit manufacturing process technology field, be specifically related to a kind of preparation technology of deep submicron integrated circuit Cu barrier.

Background technology

Along with constantly dwindling of integrated circuit (IC) design rule, the characteristic size live width has narrowed down to 0.10 micron, and keeps the continuous trend that reduces downwards.On the other hand, device density constantly increases in the integrated circuit, and the metal line number of plies is more and more, and the wiring number of plies of logical circuit has reached the 7-8 layer.Because the resistance of metal interconnection line itself and the increase of parasitic capacitance thereof, the interconnected delay of consequent RC has surmounted the grid delay of transistor itself greatly, becomes the restraining factors of integrated circuit speed.

Present stage integrated circuit interconnected mainly be to adopt the Al metal line, metal line itself has series resistance and parasitic capacitance to exist in the process of transmission of electric signals.Along with constantly dwindling of designs rule, live width W constantly diminishes, and simultaneously, the increase of integrated level causes interconnection line length further to extend, thereby causes the rapid rising of interconnection line resistance.On the other hand, the width of metal line constantly dwindles, and makes that the electric capacity between the interconnection line increases day by day.Thereby cause the further increasing of the interconnected delay of RC.Therefore, reduce the RC interconnect delay and become the focus that people pay close attention to.

On the one hand, people attempt adopting dielectric materials to replace traditional insulating material, to reduce between interconnecting metal and line capacitance.On the other hand, actively seek the metal of deelectric transferred ability, replace having used the Al metal of decades with littler resistivity and Geng Gao.Because the Cu metal has the resistivity littler than Al, higher fusing point, lower thermal coefficient of expansion.Thereby the electric conductivity of Cu and deelectric transferred performance all are superior to the Al metal greatly.Since IBM in 1998 takes the lead in introducing Cu Damascus process technology in semiconductor production line, replace the Al multi-layer metal wiring with Cu, thereby reduce the performance impact of interconnection resistance greatly to integrated circuit, reliability level is significantly improved, make Cu become the very potential novel interconnected metal material of following deep-submicron device.

For traditional Al technology, the Cu interconnection technique is a kind of brand-new technology, and great changes have taken place for process equipment and material.Continuing to optimize of Cu Damascus technique, the continuous progress of particularly etching suspension layer (Etch-Stop), medium with low dielectric constant deposit, through hole and Wire connection slot photoetching and etching, Cu barrier layer deposition, Cu seed crystal and plating, Cu chemico-mechanical polishing and back cleaning makes Cu technology can adapt to the processing request of very lagre scale integrated circuit (VLSIC) to minimum characteristic size and very big depth-width ratio figure.

But Cu is a kind of heavy genus, under the situation of high temperature and added electric field, can be in semi-conductor silicon chip and silica dioxide medium rapid diffusion, cause the problem of device reliability aspect.So, between Cu and dielectric, must add the barrier material that prevents the Cu diffusion, the purpose on barrier layer mainly contains two, and the firstth, the diffusion of resistance Cu metal in medium, the secondth, the adhesiveness of raising Cu and medium.

Usually, the requirement on Cu barrier layer is comprised following several respects: 1. barrier layer deposition will have good step coverage, particularly for depth-width ratio (A/R) greater than 6 double-deck damascene structure, it is the comparison difficulty that the step of sidewall and bottom covers; 2. the volume resistance barrier material of barrier material itself must be very low, to reduce contact resistance and Cu wiring series resistance; 3. good with the insulating medium layer adhesiveness, not easily separated and come off; Be the good barrier of Cu, in dielectric, spread, cause between the interconnection line and leak electricity to prevent Cu; 4. can stand the test of road processing technology high temperature behind the Cu, Cu Damascus work flow temperature is at 300 ℃ to 420 ℃ usually; 5. good with the dielectric materials compatibility, do not influence the chemical property of dielectric materials; 6. physical characteristic satisfies follow-up CMP (Chemical Mechanical Polishing) process requirement.

Physical vapor deposition (PVD) is generally adopted on the Cu barrier layer, and main cause has 3 points: 1.PVD depositing technics maturation, and in the semiconductor technology metallization process, be used widely; 2.PVD investment cost is less, processing cost is low; 3. the equipment of replacement PVD barrier layer and technology are also among exploitation.Adopt the PVD barrier layer, make that semiconductor process line can continue to use existing equipment and technology, reduce extra equipment investment of equipment and new process development required time and expense.Particularly the multi-cavity chamber project organization of PVD equipment makes that adding new process chamber is very easy to realize.

For deep submicron integrated circuit technology, require that the Cu barrier layer can (＞4: the continuous barrier layer of deposit thin in the figure 1), this have just proposed harsh more requirement to the PVD deposition technology in very big depth-width ratio.The advantage of long-range physical deposition is that equipment is simple, has only just strengthened the spacing of target to silicon chip, and like this, sputtered atom can gather on the silicon chip effectively.The limitation of long-range physical deposition shows the lack of homogeneity of film, and because the influence of shadow effect, causes the silicon chip sidewall step cladding thickness that keeps to the side in the figure in zone asymmetric.

Exploitation is fit to the Cu barrier layer of deep submicron integrated circuit arts demand, must consider the following step covering that comprises, particle to the blocking capability of Cu, is asked the adhesiveness of dielectric in layer, to a series of key factors such as influence of follow-up Cu chemico-mechanical polishing.

Summary of the invention

The objective of the invention is to propose a kind of manufacturing process of deep submicron integrated circuit Cu barrier, so that to comprise that step covers just, particle, to the blocking capability of Cu, in the adhesiveness of layer insulation medium, the factors such as influence of follow-up Cu chemico-mechanical polishing are improved.

The manufacturing process of the deep submicron integrated circuit Cu barrier that the present invention proposes is to adopt IPVD method deposit TaSiN and TaN as the Cu barrier layer.Wherein, TaSiN and medium are adjacent, and Ta is deposited on the TaSiN, physical deposition Cu inculating crystal layer on TaSiN/Ta, Ta and Cu metal seed crystalline phase neighbour are with chemical plating method deposit Cu film, cooperate rapid thermal annealing (RTP) and Cu chemico-mechanical polishing, realize the metal interconnection technology of Cu.

The present invention selects TaSiN as diffusion impervious layer adjacent with dielectric layer in the interconnected technology of Cu, promptly adds the Si atom and form TaSiN in the TaN lattice, and Si can be linked to each other with the N key is accurate, can significantly improve anti-Cu diffusion and the anti-F diffusivity of TaSiN.TaSiN also has good adhesiveness with Cu metallic film and insulating medium layer, is applicable in the interconnected technology that Cu metal and dielectric materials combine; In addition, also select Ta as the barrier material adjacent with the Cu metal.Ta not only has good adhesiveness with the Cu metal, and the Cu metal of growing on Ta has good crystal orientation orientation consistency and film thickness uniformity.The resistivity of Ta only is 12.45 microhms. centimetre, be good barrier layer material adjacent in the Cu metal interconnection technology with the Cu inculating crystal layer; When electroless plating Cu, adopt to add alternating electric field and electroplating additive, to improve the filling perforation and the thickness evenness of Cu film; Cu heat-treats Cu with rapid thermal annealing after electroplating, to guarantee the crystal grain and the resistance consistency of Cu film; Then carry out chemico-mechanical polishing, grind off line and through hole unnecessary Cu metal and barrier layer in addition, finish the technology of the interconnected wiring in Cu Damascus.

In the technology of the present invention:

Adopt multi-cavity chamber ion physical deposition (IPVD) equipment, under the low vacuum condition, earlier silicon chip is carried out degasification and surface preparation;

Adopt ion physical deposition (IPVD) method, barrier layer TaSiN on silicon chip, thickness are 20nm-40nm;

On TaSiN, use ion physical deposition (IPVD) method depositing metal Ta, thickness 10nm-30nm;

Use ion physical deposition (IPVD) method deposit one deck Cu inculating crystal layer again on TaSiN/Ta, thickness is 100nm-300nm;

On the Cu inculating crystal layer, the Cu film with electroless plating method plating desired thickness adds alternating electric field and additive in the electroplating technology, to improve the filling perforation and the thickness evenness of electroless plating Cu film;

After the electroless plating Cu film, with rapid thermal annealing (RTP) deposit Cu film is heat-treated, to guarantee the crystal grain and the resistance consistency of Cu film, annealing temperature is 200-300 ℃, N ₂Atmosphere, time 15-40 second.

Carry out chemico-mechanical polishing at last, grind off line and through hole unnecessary Cu metal and barrier layer in addition, finish the technology of the interconnected wiring in Cu Damascus.

The present invention selects TaSiN as the Cu diffusion impervious layer, significantly improves anti-Cu diffusion and the anti-F diffusivity of TaSiN.TaSiN also has good adhesiveness with Cu metallic film and insulating medium layer, and crystal orientation orientation consistency and uniformity are all fine.The resistivity of Ta is very low in addition, can reduce the interconnected through hole contact resistance of Cu, selects Ta as the barrier material adjacent with the Cu metal.When electroless plating Cu, adopt to add alternating electric field and electroplating additive, can improve the filling perforation and the thickness evenness of Cu film.Therefore, the present invention covers comprising step, and particle to the blocking capability of Cu, in the adhesiveness of layer insulation medium, has tangible improvement to a series of key factors such as influence of follow-up Cu chemico-mechanical polishing.

Description of drawings

Fig. 1 is that TaSiN and Ta are as the application schematic diagram of barrier layer in the Cu damascene structure.Label declaration: wherein 1 is TaSiN, the 2nd, Ta, the 3rd, Cu.

Embodiment

Further describe the present invention below by specific embodiment:

1, adopt multi-cavity chamber ion physical deposition (IPVD) equipment, under the low vacuum condition, silicon chip is carried out degasification, temperature is 350 ℃, and 180 seconds time is with steam and other impurity of eliminating the surface;

2, use Ar ₂And H ₂Plasma carries out preliminary treatment to silicon chip surface, removes the residue that natural oxidizing layer in the through hole and preceding technology stay.Pretreatment time is 20 seconds;

3, use ion physics (IPVD) method deposit TaSiN barrier layer then, thickness is 30nm;

4, use ion physics (IPVD) method deposit Ta on TaSiN, thickness is 20nmnm;

5, and then use ion physics (IPVD) method deposit one deck Cu inculating crystal layer, thickness is 200nm;

6, finish the silicon chip of ion physics (IPVD) deposit Cu inculating crystal layer, send into Cu electroless plating groove, electroplate the Cu metallic film of 1000nm.Adopt in the plating and add the alternation added electric field, and add other chemical auxiliary reagents, to improve the filling perforation and the thickness evenness of Cu film;

7, after the Cu metal level was electroplated, (RTP) heat-treated Cu with rapid thermal annealing, and to guarantee the crystal grain and the resistance consistency of Cu film, annealing temperature is 200 ℃, 20 seconds time, N ₂Atmosphere.

8, Cu chemico-mechanical polishing grinds off line and through hole unnecessary Cu and barrier layer in addition, finishes the processing technology of the interconnected wiring in Cu Damascus.

9, just finish the through hole and the Wire connection slot processing technology in the interconnected Damascus of Cu like this.See Fig. 1.

Zhi Bei Cu barrier layer thus is to the adhesiveness of the blocking capability of Cu, layer insulation medium, all have clear improvement to follow-up mechanical polishing etc.

Claims

1, a kind of manufacturing process of deep submicron integrated circuit Cu barrier, it is characterized in that, adopt IPVD method deposit TaSiN and TaN, as the Cu barrier layer, wherein TaSiN and medium are adjacent, Ta is deposited on the TaSiN, physical deposition Cu inculating crystal layer on TaSiN/Ta, Ta and Cu metal seed crystalline phase neighbour are with chemical plating method deposit Cu film, cooperate rapid thermal annealing and Cu chemico-mechanical polishing, realize the metal interconnection technology of Cu.

2, manufacturing process according to claim 1 is characterized in that, the thickness of the barrier layer TaSiN of deposit is 20nm-40nm.

3, manufacturing process according to claim 1, the thickness that it is characterized in that metals deposited Ta is 10nm-30nm.

4, manufacturing process according to claim 1 is characterized in that the thickness of one deck Cu inculating crystal layer of deposit is 100nm-300nm.

5, manufacturing process according to claim 1 when it is characterized in that with electroless plating method plating Cu film, adds alternating electric field and additive, to improve the filling perforation and the thickness evenness of electroless plating Cu film.