CN1405781A - Nonvolatile internal storage reliability test method and circuit - Google Patents
Nonvolatile internal storage reliability test method and circuit Download PDFInfo
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- CN1405781A CN1405781A CN 01130670 CN01130670A CN1405781A CN 1405781 A CN1405781 A CN 1405781A CN 01130670 CN01130670 CN 01130670 CN 01130670 A CN01130670 A CN 01130670A CN 1405781 A CN1405781 A CN 1405781A
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Abstract
The method includes the following steps. The relation curve between the grid voltage and the attenuation rate of the reading current is decided. The actual grid voltage and its relevant attenuation rate of the reading current are predicted. The accelerated test grid voltage and the test time relevant to the actual grid voltage are solved from the said relation curve. The test is carried out continuously in the test time number the accelerated test grid voltage in order to measure the reading current related as well as determine whether the memory is in effect or not. Thus, the reliability testing for the non-volatile memory is completed.
Description
Technical field
The present invention relates to a kind of test circuit and method of non-voltile memory, and be particularly related to a kind of reliability testing (qualification test) method and circuit with non-voltile memory of trap layer (trapping).
Background technology
Non-voltile memory (non-volatile memory), flash memory (Flash) for example, the grid structure of general present use has control grid and floating grid, wherein controls the voltage that grid is used for receiving the action of control store unit, and floating grid then is used for store charge.Under this kind framework, because floating grid is as the made conductor of polysilicon, when therefore storage unit being carried out sequencing, the electronics that is injected into floating grid can be uniformly distributed in the floating grid.So having the storage unit of floating grid structure, this kind only can do the storage of a position.Afterwards, the memory cell structure that utilizes insulator to replace floating grid just is suggested.When utilizing insulator to come bound electron, can allow electronics be fettered,, make the service efficiency of storage unit more improve so can reach two storage storage by the part.
Please refer to Fig. 1, is the structural profile synoptic diagram that can store two the non-voltile memory with trap layer.As shown in Figure 1, have as the source electrode 18 of storage unit and the ion doping of drain electrode 16 in substrate.The substrate top then has grid structure, and grid structure can be a kind of oxide 10/ nitride 12/ oxide 14 (oxide/nitride/oxide) structure.Wherein nitride layer 12 is used for the trap layer as trapped electrons.At this, channel hot electron is injected (channel hotelectron injection) and with band band hot hole injection (band-to-band hot hole injection) is used for respectively storage unit is carried out program (program) and erased (erase) program.
Because trap layer 12 is nonconductor (insulation courses), so when electronics is attracted into, just can be limited to the drain side or the source side of storage unit.That is to say that when applying programm voltage in grid and drain electrode, and source electrode is when applying the voltage of 0V, the gate-to-drain side just can produce big electric field, electronics is sucked into the drain side of trap layer and is bound by wherein.Otherwise when applying programm voltage in grid and source electrode, and drain electrode is when applying the voltage of 0V, and the gate-to-source side just can produce big electric field, electronics is sucked into the source side of trap layer and is bound by wherein.Connect this, can accomplish two storing mode, the position 1 just shown in Figure 1 and the position of position 2.
Table one
This storage unit can be by after injecting insulation course 12 with electronics, with the critical voltage that changes storage unit (threshold voltage, Vt).Yet storage unit is after process program/erase period (program/erase cycle, P/E cycle), and the critical voltage of program state (programmed state) can increase along with the increase of retention time (retention time).The increase of critical voltage can cause the increase of leakage current (leakage current), and can make the canned data of storage unit lose efficacy.For example, originally when being lower than certain critical voltage and being the situation of state " 1 ", can be because the increase of critical voltage, and can't tell state " 1 " or state " 0 "; That is to say that what the stored information of storage unit can't be correct reads.
Therefore, in order to guarantee after storage unit is produced, to arriving through the product after the encapsulation in user's the hand, internal memory can be used chronically and can not lose efficacy, so just need to test, guarantee through after the long-term retention time, even critical voltage increases, still in normal operation range, and can not lose efficacy.Yet because the test duration is limited, how performance test method correctly and effectively predicts the serviceable life (life time) of storage unit, just becomes an important job.
Summary of the invention
Utilization of the present invention has the physical characteristics of the non-voltile memory of insulation trap layer, proposes effective method of testing and device, is a kind of accelerated test, makes in the short test duration, can estimate the use serviceable life of following storage unit.
Therefore, the present invention proposes a kind of method for testing reliability and device of non-voltile memory, and it is the test of a kind of acceleration, utilizes in one period test duration, judge memory cell array whether can be in the serviceable life of being scheduled to operate as normal.
The present invention proposes a kind of method for testing reliability of non-voltile memory, comprising: determine a grid voltage for the relation curve that reads the current attenuation rate; Estimate this actual gate voltage with to the current attenuation rate that reads that should grid voltage; Try to achieve an accelerated test grid voltage and a test duration that should actual gate voltage from this relation curve; With this accelerated test grid voltage, in this test duration, test continuously; And measure to should the accelerated test grid voltage one read the current attenuation rate, and judge the electric current that reads of internal memory under this accelerated test grid voltage, whether still effective to judge this internal memory.
The present invention also proposes a kind of reliability testing circuit of non-voltile memory, in order to test a memory cell array, wherein memory cell array has plurality of memory cells, arrange formation with several column and row, wherein respectively these row are couple to a novel word-line driver design for pseudo two-port, and respectively this row is couple to a bit line bias circuit, the reliability testing circuit of this non-voltile memory comprises a character line bias generator, be couple to this novel word-line driver design for pseudo two-port, in order to import the accelerated test that a character voltage carries out the critical voltage skew.
Description of drawings
Fig. 1 is the structural profile synoptic diagram that can store two the non-voltile memory with trap layer;
Fig. 2 is the critical voltage skew and reads current offset and the graph of a relation between the retention time;
Fig. 3 is under the various grid voltage, critical voltage skew and the graph of a relation between the retention time;
Fig. 4 is grid voltage and reads graph of a relation between the current attenuation rate;
Fig. 5 is a schematic flow sheet of the method for testing reliability of non-voltile memory of the present invention;
Fig. 6 is a circuit example schematic implementing the reliability side method for testing of non-voltile memory of the present invention.
Embodiment
Have the non-voltile memory of insulation trap layer the critical voltage skew ((hreshold drift) with read current offset (read current drift) and can increase along with the retention time of storage unit and increase.And the logarithm of this shift phenomenon and retention time is linear relationship haply.The present invention promptly will utilize the physical phenomenon of this skew, comes storage unit is carried out the accelerated test of reliability.
Fig. 2 is the critical voltage skew and reads current offset and the graph of a relation between the retention time.As shown in Figure 2, at first, represent with diamond indicia among the figure at the shift phenomenon of critical voltage.Along with the increase of retention time, the side-play amount of critical voltage also increases with work from scheming as can be seen.For example when the retention time was 100 seconds, critical voltage side-play amount dVt was about 0.01V, and when the retention time arrived 100000 seconds, its corresponding critical voltage side-play amount dVt was about 0.042V.That is along with the increase of retention time, critical voltage side-play amount dVt is increased to 0.042V from 0.01V, and is about linear relationship.In addition, the side-play amount that reads electric current as can be seen from figure also increases along with the increase of retention time.For example when the retention time is 100 seconds, reads current offset amount dIr and be about about 0.2 μ A, and when the retention time arrives 100000 seconds; The current offset amount that the reads dIr of its correspondence is about 1.1 μ A.That is, along with the increase of retention time, read current offset amount dIr and be increased to 1.1 μ A, and be about linear relationship from 0.2 μ A.
In addition, show according to experimental data that the side-play amount of critical voltage is except the increase with the retention time increases, the size of grid voltage Vg that puts on the grid of storage unit also can be influential to the side-play amount of critical voltage.Fig. 3 is under various grid voltage, critical voltage skew and the graph of a relation between the retention time.
As shown in Figure 3, be to be under 0V, 2V and three kinds of situations of 4V at grid voltage Vg, critical voltage skew and the graph of a relation between the retention time.As can be seen from the figure when the retention time is 10 seconds, it is too many that three kinds of pairing critical voltages skews of different grid voltages can not differ from, but along with the increase of retention time, grid voltage Vg is also just remarkable more to the influence of critical voltage side-play amount.For example when the retention time is 1000 seconds, pairing critical voltage side-play amount dVt was about 0.12V when grid voltage Vg was 0V, pairing critical voltage side-play amount dVt was about 0.175V when grid voltage Vg was 2V, and grid voltage Vg when being 4V pairing critical voltage side-play amount dVt be about 0.2V.That is, can find out significantly that grid voltage Vg is big more, it is also big more that critical voltage side-play amount dVt increases the side-play amount that is produced with retention time DE1.
In sum, the present invention is according to above-mentioned DE1 physical phenomenon, in conjunction with grid voltage with read the current offset amount and come foundation as reliability testing of the present invention.
Fig. 4 is grid voltage and the graph of a relation that reads between the current attenuation rate (read current degradation, μ A/dec).Relation between the two is linear relationship haply as seen from Figure 4.In addition, as seen from Figure 4 at the demand of 10 years product, need the acceleration of 1.3 times deviation ratio for 1000 hours product reliability test durations.
As shown in Figure 4, for 10 years product serviceable life, actual characters line voltage was that the pairing current attenuation rate that reads of 2.75V is 1 μ A/dec, was 1.25 μ A/dec and word line voltages is the current attenuation rate that reads of 4V.Therefore, when carrying out reliability testing, as long as apply the grid of the word line voltages of 4V to storage unit, and in 1000 hours the measured current attenuation amount that reads, just can correspond to actual characters line voltage when being 2.75V, its current attenuation amount that reads in 10 years.That is, when satisfying the accelerated test of word line voltages, can conclude that just storage unit can satisfy the serviceable life under the practical operation, and can not lose efficacy.
Fig. 5 is a schematic flow sheet of aforesaid way.At first, step S100 decision grid voltage (word line voltages) and read relation curve between the current attenuation rate.For example, graph of a relation shown in Figure 4.
Storage unit was at the grid voltage of a predetermined lifetime after step S102 estimated.For example, shown in Figure 4, serviceable life, grid voltage Vg was 2.75V when being 10 years.Afterwards, step S104 tries to achieve the accelerated test word line voltages and the test duration of corresponding actual gate voltage from the resulting figure of step S100.For example, Vg=4V, and the test duration be 1000 hours.
Then step S106 tested in 1000 hours test durations continuously with the accelerated test word line voltages of Vg=4V, measured and read electric current.After 1000 hours, just measured read electric current and whether meet its product specification in that step S108 is corresponding.
After through 1000 hours test, the measured current attenuation rate that reads meets product specification, then can obtain in the time spent of doing through actual characters line voltage at step S110, and it reads the judgment criterion that the current attenuation rate can satisfy serviceable life more than 10 years.That is the note storage unit has reliability.Otherwise, after storage unit was through 1000 hours test, the measured electric current that reads does not meet product specification, then can obtain in the time spent of doing through actual characters line voltage at step S112, and it reads the judgment criterion that electric current can't satisfy serviceable life more than 10 years.That is storage unit can lose efficacy under the word line voltages effect of reality.
In sum, utilize aforesaid accelerated test method, can be correctly and estimate serviceable life of product effectively.
Fig. 6 is a circuit example schematic implementing the method for testing reliability of non-voltile memory of the present invention.As shown in Figure 6, be a flash array 20, do representative and wherein only draw a storage unit M.The memory array 20 of should knowing of being familiar with this technology is to be staggered and to form in plural number capable (bit line connects the source electrode with delegation's internal memory) and row (character line connects the grid of same column memory) mode by plurality of memory cells.Novel word-line driver design for pseudo two-port (word line driver) 32 is couple to each bar character line WL, in order to sequencing to be provided, to erase and to read the grid of voltage to storage unit.Column address decoder (row decoder) 30 is couple to novel word-line driver design for pseudo two-port 22, after receiving a column address, after its decoding, is sent to novel word-line driver design for pseudo two-port 32; Drive the storage unit that is connected on the selected column address (character line) by novel word-line driver design for pseudo two-port 32 more afterwards.The bit line bias circuit (b " line bias circuit) 40, be couple to each bit lines BL, in order to sequencing to be provided, to erase and to read to receive the source electrode of voltage to storage unit.Row-address decoder (columndecoder) 42 is couple to bit line bias circuit 40, after receiving a row address, after its decoding, is sent to bit line bias circuit 40; Provide bias voltage to the storage unit that is connected on the selected row address (bit line) by bit line bias circuit 40 more afterwards.
Character line bias generator 50 is coupled to novel word-line driver design for pseudo two-port 32, in order to import the accelerated test that a character voltage carries out the critical voltage skew.For example, be example with above-mentioned example, with the accelerated test word line voltages of Vg=4V, in 1000 hours test durations, tested continuously, measure the current attenuation rate that reads.After through 1000 hours test, measured when reading electric current and meeting product specification, then can obtain through actual characters line voltage do the time spent can satisfy the judgment criterion in the serviceable life more than 10 years; Otherwise, after through 1000 hours test, when the measured current attenuation rate that reads does not meet product specification, then can obtain through actual characters line voltage do the time spent can't satisfy the judgment criterion in serviceable life more than 10 years.
In sum; though the present invention with preferred embodiment openly as above; but it is not in order to limit the present invention; any personnel that are familiar with this technology; various changes and the retouching done without departing from the spirit and scope of the present invention; all belong to protection scope of the present invention, and protection scope of the present invention is with being as the criterion that claims were limited.
Claims (6)
1. the method for testing reliability of a non-voltile memory is characterized in that: comprising:
Determine a grid voltage and a relation curve that reads the current attenuation rate;
Estimate this actual gate voltage with to should grid voltage one read the current attenuation rate;
From this relation curve, try to achieve an accelerated test grid voltage and a test duration to this actual gate voltage;
With this accelerated test grid voltage, in this test duration, test continuously;
Measurement to should the accelerated test grid voltage one read electric current, and judge this accelerated test grid voltage this read electric current and whether satisfy a product specification;
Wherein when satisfying this product specification, then be judged as effectively; When not satisfying this product specification, then be judged as inefficacy.
2. the method for testing reliability of non-voltile memory according to claim 1, it is characterized in that: this grid voltage is roughly linearity to this relation curve that reads the current attenuation rate.
3. the method for testing reliability of a non-voltile memory is characterized in that: comprising:
Determine a grid voltage pair and a relation curve that reads the current attenuation rate;
According to a grid voltage pair with read current attenuation rate relation, estimate an actual gate voltage with to should grid voltage one read the current attenuation rate;
Try to achieve an accelerated test grid voltage and a test duration that should actual gate voltage;
With this accelerated test grid voltage, in this test duration, test continuously, and measure to should the accelerated test grid voltage one read electric current, whether satisfy this actual gate voltage pairing serviceable life to judge this non-voltile memory.
4. the method for testing reliability of non-voltile memory according to claim 3, it is characterized in that: this grid voltage is roughly linearity to reading this green relation curve of current attenuation.
5. the reliability testing circuit of a non-voltile memory, in order to test a memory cell array, it is characterized in that: this memory cell array has plurality of memory cells, arrange formation with several column and row, wherein respectively these row are couple to a novel word-line driver design for pseudo two-port, and respectively this row is couple to a bit line bias circuit, and the reliability testing circuit of this non-voltile memory comprises:
One character line bias generator is couple to this novel word-line driver design for pseudo two-port, in order to import the accelerated test that a character voltage carries out the critical voltage skew.
6. non-voltile memory circuit with reliability testing circuit is characterized in that: comprising:
One memory cell array has plurality of memory cells, arranges with row with several column to constitute;
One character line driving circuit is coupled to each those row, in order to drive each those row;
One bit line bias circuit is coupled to each those row, in order to drive each those row;
One character line bias generator is couple to this novel word-line driver design for pseudo two-port, in order to import the accelerated test that a character voltage carries out the critical voltage skew.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01130670 CN1220986C (en) | 2001-08-17 | 2001-08-17 | Nonvolatile internal storage reliability test method and circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01130670 CN1220986C (en) | 2001-08-17 | 2001-08-17 | Nonvolatile internal storage reliability test method and circuit |
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| CN1405781A true CN1405781A (en) | 2003-03-26 |
| CN1220986C CN1220986C (en) | 2005-09-28 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100403452C (en) * | 2003-11-18 | 2008-07-16 | 海力士半导体有限公司 | Method of measuring threshold voltage for a NAND flash memory device |
| CN103019909A (en) * | 2012-12-14 | 2013-04-03 | 浪潮电子信息产业股份有限公司 | Internal memory reliability test method |
| CN103970631A (en) * | 2014-05-23 | 2014-08-06 | 浪潮电子信息产业股份有限公司 | Method for testing reliability of internal storage based on VID dial switch hardware circuit |
| CN104408252A (en) * | 2014-11-25 | 2015-03-11 | 深圳市国微电子有限公司 | Reliability assessment method and device for circuit device |
| CN103019909B (en) * | 2012-12-14 | 2016-11-30 | 浪潮电子信息产业股份有限公司 | A kind of internal memory reliability test method |
-
2001
- 2001-08-17 CN CN 01130670 patent/CN1220986C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100403452C (en) * | 2003-11-18 | 2008-07-16 | 海力士半导体有限公司 | Method of measuring threshold voltage for a NAND flash memory device |
| CN103019909A (en) * | 2012-12-14 | 2013-04-03 | 浪潮电子信息产业股份有限公司 | Internal memory reliability test method |
| CN103019909B (en) * | 2012-12-14 | 2016-11-30 | 浪潮电子信息产业股份有限公司 | A kind of internal memory reliability test method |
| CN103970631A (en) * | 2014-05-23 | 2014-08-06 | 浪潮电子信息产业股份有限公司 | Method for testing reliability of internal storage based on VID dial switch hardware circuit |
| CN104408252A (en) * | 2014-11-25 | 2015-03-11 | 深圳市国微电子有限公司 | Reliability assessment method and device for circuit device |
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| Publication number | Publication date |
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| CN1220986C (en) | 2005-09-28 |
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