CN1215481C - Method for proving non-volatile internal memory reliability and circuit - Google Patents
Method for proving non-volatile internal memory reliability and circuit Download PDFInfo
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- CN1215481C CN1215481C CN 01130672 CN01130672A CN1215481C CN 1215481 C CN1215481 C CN 1215481C CN 01130672 CN01130672 CN 01130672 CN 01130672 A CN01130672 A CN 01130672A CN 1215481 C CN1215481 C CN 1215481C
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Abstract
The present invention relates to a reliability verification method for a nonvolatile memory. Firstly, a relation curve between program voltage and a memory unit array is determined; subsequently, the program voltage of the memory unit array is predicted; the acceleration test program voltage and the test time which correspond to the preset program voltage are worked out from the relation curve to accelerate the program voltage and make continuous tests within the test time. The programmed state of all memory units in the memory unit array is verified, and whether all of the memory units in the memory unit array remain in the programmed state after the test time or not is judged. When all of the memory units in the memory unit array remain in the programmed state, the memory unit array has the predicted service life. When parts of the memory units in the memory unit array do not remain in the programmed state, the memory unit array does not have the predicted service life.
Description
Technical field
The present invention relates to a kind of proof scheme and method of Nonvolatile memory, and be particularly related to a kind of reliability demonstration (qualification test) method and circuit with Nonvolatile memory of trap layer (trapping).
Background technology
Nonvolatile memory (non-volatile memory), flash memory (Flash) for example, the grid structure of general present use has control grid and floating grid, wherein controls the voltage that grid is used for receiving the action of control store unit, and floating grid then is used for store charge.Under this kind framework, because floating grid is as the made conductor of polysilicon, when therefore storage unit being carried out sequencing, the electronics that is injected into floating grid can be uniformly distributed in the floating grid.So having the storage unit of floating grid structure, this kind only can do the storage of a position.Afterwards, the memory cell structure that utilizes insulator to replace floating grid just is suggested.When utilizing insulator to come bound electron, can allow electronics be fettered,, make the service efficiency of storage unit more improve so can reach two storage storage by the part.
Please refer to Fig. 1, is the structural profile synoptic diagram that can store two the Nonvolatile memory with trap layer.As shown in Figure 1, have as the source electrode 18 of storage unit and the ion doping of drain electrode 16 in substrate.The substrate top then has grid structure, and grid structure can be a kind of oxide 10/ nitride 12/ oxide 14 (oxide/nitride/oxide) structure.Wherein nitride layer 12 is used for the trap layer as trapped electrons.At this, channel hot electron is injected (channel hot electron injection) and with band the band hot hole is injected (band-to-band hot hole injection).Be used for respectively storage unit is carried out program (program) and erased (erase) program.
Because trap layer 12 is nonconductor (insulation courses), so when electronics is attracted into, just can be limited to the drain side or the source side of storage unit.That is to say that when applying programm voltage in grid and drain electrode, and source electrode is when applying the voltage of 0V, the gate-to-drain side just can produce big electric field, electronics is sucked into the drain side of trap layer and is bound by wherein.Otherwise when applying programm voltage in grid and source electrode, and drain electrode is when applying the voltage of 0V, and the gate-to-source side just can produce big electric field, electronics is sucked into the source side of trap layer and is bound by wherein.Connect this, can accomplish two storing mode, the position 1 just shown in Figure 1 and the position of position 2.
Table one
The kind storage unit can be by after injecting insulation course 12 with electronics, with the critical voltage that changes storage unit (threshold voltage, Vt).Yet storage unit is after process program/erase period (program/erase cycle, P/E cycle), and the critical voltage of program state (programmed state) can reduce along with the increase of retention time (retention time).The reduction of critical voltage can cause the increase of leakage current (leakage current), and can make the canned data of storage unit lose efficacy.For example, when being the situation of state " 0 ", understanding reduction, and can't tell state " 1 " or state " 0 " originally because of critical voltage above certain critical voltage; That is to say that what the stored information of storage unit can't be correct reads.
Therefore, in order to guarantee after storage unit is produced, to arriving through the product after the encapsulation in user's the hand, internal memory can be used chronically and can not lose efficacy, so just need to test, guarantee through after the long-term retention time, even critical voltage reduces, still in normal operation range, and can not lose efficacy.Yet because the test duration is limited, how performance test method correctly and effectively predicts the serviceable life (life time) of storage unit, just becomes an important job.
Summary of the invention
Utilization of the present invention has the physical characteristics of the Nonvolatile memory of insulation trap layer, proposes effective verification method and device, is a kind of accelerated test, makes in the short test duration, can estimate the use serviceable life of following storage unit.
Therefore, the present invention proposes a kind of reliability verification method and device of Nonvolatile memory, and it is the test of a kind of acceleration, utilizes in one period test duration, judge memory cell array whether can be in the serviceable life of being scheduled to operate as normal.
The present invention proposes a kind of reliability verification method of Nonvolatile memory.At first, determination procedure voltage pair and the relation curve of memory cell array between serviceable life.Then estimate the programm voltage of this memory cell array at intended life.From this relation curve, try to achieve accelerated test programm voltage and test duration to this programm voltage that should intended life, with accelerated procedure voltage, in the test duration, test continuously.All storage unit in the memory cell array are carried out the checking of procedure stores state, and judge whether all storage unit all maintain this program state through after this test duration in the memory cell array.Wherein when all storage unit in the memory cell array all maintain program state, then be judged as memory cell array and have corresponding serviceable life; When the partial memory cell in the memory cell array does not maintain program state, then be judged as memory cell array and do not have corresponding serviceable life.
The present invention also proposes a kind of reliability demonstration circuit of Nonvolatile memory, in order to test a memory cell array, wherein memory cell array has plurality of memory cells, arrange formation with several column and row, wherein each row is couple to a novel word-line driver design for pseudo two-port, and each row is couple to a bit line bias circuit, and the reliability demonstration circuit of Nonvolatile memory comprises a programm voltage access control unit, be couple to memory cell array, in order to each storage unit is carried out the control and the checking of program state.
By above-mentioned acceleration verification method and circuit, utilize the programm voltage of accelerated test, in the predetermined test duration, all storage unit are tested.Through after the schedule time, verify thereupon whether all storage unit all can be verified the state in sequencing.If, then can learn under the programm voltage of a reality, its storage unit all be identified can be in predetermined serviceable life operate as normal.Whereby, to reach the purpose of reliability demonstration.
Description of drawings
Fig. 1 is the structural profile synoptic diagram that can store two the Nonvolatile memory with trap layer;
Fig. 2 is under various programm voltage (Vtpgm), critical voltage Vt and the relation between the retention time;
Fig. 3 is under different programm voltages, leakage current and the relation between the retention time;
Fig. 4 is that programm voltage and storage unit concern synoptic diagram between serviceable life;
Fig. 5 is a schematic flow sheet of the reliability verification method of Nonvolatile memory of the present invention;
Fig. 6 is a circuit example schematic of the reliability verification method of Nonvolatile memory of the present invention.
Embodiment
At first, please refer to Fig. 2, is under various programm voltage (Vt program) Vtpgm, critical voltage Vt and the relation between the retention time.For example, when Vtpgm was 5.92V, along with the retention time was increased to 900 hours from 8 hours, its critical voltage Vt reduced to about 3.75V from about 4.75V.Can find out easily that from Fig. 2 the variation of critical voltage Vt and the relation of retention time are logarithmic relationship, and are about linearity, and along with the increase of retention time, critical voltage Vt can descend thereupon.
In addition, be example with Fig. 2, the rate of change of critical voltage and programm voltage correlativity are low, are about shown in the following formula:
Therefore, under identical judgment criterion (failure criteria), when for example being criterion with Vt=2.5V, high more programm voltage Vtpgm, its corresponding serviceable life is just long more.Judgment criterion representative can not tell just that stored data ties up to state " 0 ", storage-unit-failure in the storage unit when critical voltage is lower than this value.
As shown in Figure 2, for example when programm voltage Vtpgm was 4.2V, the critical voltage on the figure was reduced to about 2.7V from about 3.5V.Just when the retention time arrived near 1000 hours, its critical voltage Vt was near inefficacy judgment criterion 2.5V.That is to say that when programm voltage Vtpgm was 4.2V, had only 1000 hours its serviceable life approximately.Otherwise when programm voltage Vtpgm was 5.92V, the critical voltage on the figure was reduced to about 3.75V from about 4.75V.This moment is also poor far from the border that critical voltage lost efficacy, and just its serviceable life is much larger than the condition when programm voltage Vtpgm is 4.2V.Fig. 3 is under different programm voltages, leakage current and the relation between the retention time.Fig. 3 is (Vtpgm=2.91～3.7V), the leakage current Ir of detection of stored unit (μ A) under different programm voltages.Be with the judgment criterion of leakage current Ir=0.5 μ A (indicating II among the figure) in Fig. 3 as storage-unit-failure.When leakage current surpassed Ir=0.5 μ A, the storing state that just can not differentiate storage unit was " 0 ".In addition, graticule I represents product (storage unit) serviceable life in 10 years.
As shown in Figure 3, it can find out obviously that programm voltage Vtpgm is big more, and its corresponding retention time is just long more.With programm voltage Vtpgm=2.91V is example, and after the retention time arrived 1 hour, its leakage current just surpassed the standard of 0.5 μ A, and makes storage-unit-failure.With programm voltage Vtpgm=3.29V is example, and after the retention time arrived about 100 hours, its leakage current just surpassed the standard of 0.5 μ A, and makes storage-unit-failure.And programm voltage Vtpgm=3.70V is an example, and after limitting the 10 year serviceable life of retention time arrival curve I, its leakage current surpasses the standard of 0.5 μ A yet.Promptly as programm voltage Vtpgm=3.70V, the serviceable life of its storage unit can be above 10 years.
Fig. 4 is that programm voltage and storage unit concern synoptic diagram between serviceable life.Fig. 4 is the result in conjunction with Fig. 2 and Fig. 3.Be a linear relationship haply between serviceable life of storage unit (retention time) and the programm voltage Vtpgm as can be seen from Figure 4.The present invention will use this figure to carry out the acceleration checking of storage unit.So-called acceleration checking promptly utilizes the programm voltage Vta of an accelerated test, in a test duration of being scheduled to, all storage unit is tested.Through after this schedule time, verify thereupon whether all storage unit all can be verified the state that remains on sequencing.If, then can learn under a higher programm voltage Vtp, its storage unit all be identified can be within predetermined serviceable life operate as normal.
As shown in Figure 4, because be a linear relationship haply between serviceable life of storage unit (retention time) and the programm voltage Vtpgm, so when thinking that the programm voltage Vtp among the use figure comes the storage unit program, and when making it have predetermined serviceable life (graticule I), it can correspond to a lower programm voltage Vta and a test duration (graticule II) respectively.
For example, be example with Fig. 4, when storage unit will be 3.6V when coming program with programm voltage Vtp in future, make it have 10
5The serviceable life of hour (about 10 years), just can utilize the slope of the relation curve of Fig. 4, find an accelerated test programm voltage Vta (3.3V), and this accelerated test programm voltage Vta corresponds to a test duration 10
3Hour.
Therefore, at the reliability demonstration of carrying out storage unit (qualification test), promptly verify when whether storage unit can have the serviceable life of estimating, just can be with sequencing to accelerated test programm voltage Vta (3.3v) storage unit, and through the test duration 10
3Hour.All storage unit are carried out checking work, whether all can be verified in program state to judge all storage unit.If just all storage unit are under the situation of Vta=3.3V, through 10
3After hour, its store status is and can be verified as normally, but not loses efficacy.
In addition, because between serviceable life that is presented among Fig. 4 (retention time) and the programm voltage Vtpgm be a linear relationship haply, therefore just can obtain when storage unit when utilizing programm voltage Vtpgm for 3.6V future, its storage unit can satisfy the standard in 10 years product serviceable life.
Therefore, utilize above-mentioned method, just can estimate storage unit with lower programm voltage and whether can have predetermined product serviceable life at short notice in higher voltage.
Fig. 5 is a schematic flow sheet of aforesaid way.At first, the relation curve between the serviceable life of step S100 determination procedure voltage Vtpgm and storage unit product.For example, graph of a relation shown in Figure 4.
Step S102 estimates the programm voltage of storage unit at an intended life.For example, shown in Figure 4, serviceable life, programm voltage Vtpgm was 3.6V when being 10 years.Afterwards, step S104 is from the resulting curve of step S100, tries to achieve accelerated test programm voltage Vta and the test duration of corresponding programm voltage Vtpgm.For example, Vta=3.3V and test duration are 1000 hours.
Then step S106 tested in 1000 hours test durations continuously with the acceleration measuring program voltage of Vta=3.3V.After 1000 hours, just all storage unit are carried out the checking of the store status of storage unit, and judge whether all storage unit after through 1000 hours test at step S108, whether program state all can be kept.
After all storage unit were through 1000 hours test, when still maintaining program state, then can obtain all storage unit after sequencing at step S110 through programm voltage Vtpgm, can have the serviceable life more than 10 years.Otherwise, after storage unit was through 1000 hours test, when having partial memory cell can't maintain program state, then can obtain all storage unit after sequencing, can't have the serviceable life more than 10 years at step S112 through programm voltage Vtpgm.
In sum, utilize aforesaid acceleration verification method, can be correctly and estimate serviceable life of product effectively.
Fig. 6 is a circuit example schematic implementing the reliability verification method of Nonvolatile memory of the present invention.As shown in Figure 6, be a flash array 20, do representative and wherein only draw a storage unit M.Those skilled in the art should know that memory array 20 is staggered and forms in plural number capable (bit line connects the source electrode with delegation's internal memory) and row (character line connects the grid of same column memory) mode by plurality of memory cells.Novel word-line driver design for pseudo two-port (word linedriver) 32 is couple to each bar character line WL, in order to program to be provided, to erase and to read the grid of voltage to storage unit.Column address decoder (row decoder) 30 is couple to novel word-line driver design for pseudo two-port 32, after receiving a column address, after its decoding, is sent to novel word-line driver design for pseudo two-port 32; Drive the storage unit that is connected on the selected column address (character line) by novel word-line driver design for pseudo two-port 32 more afterwards.Bit line bias circuit (bit line bias circuit) 40 is couple to each bit lines BL, in order to program to be provided, to erase and to read the source electrode of voltage to storage unit.Row address decoder (columndecoder) 42 is couple to bit line bias circuit 40, after receiving a row address, after its decoding, is sent to bit line bias circuit 40; Provide bias voltage to the storage unit that is connected on the selected row address (bit line) by bit line bias circuit 40 more afterwards.
Programm voltage access control unit 50 is coupled to memory array 20, in order to the program state of each storage unit in the checking memory array 20.Foregoing method controls by programm voltage access control unit 50 that the program state of each storage unit is accelerated test programm voltage Vta in the memory array 20.When all storage unit through after the test of test duration, when still maintaining program state, then can obtain all storage unit and can have the long-term serviceable life of estimating.Otherwise, when storage unit through after the test of test duration, when having partial memory cell can't maintain program state, then obtain all storage unit and can't have the long-term serviceable life of estimating.
In sum; though the present invention with preferred embodiment openly as above; but it is not in order to limit the present invention; any personnel that are familiar with this technology; various changes and the retouching done without departing from the spirit and scope of the present invention; all belong to protection scope of the present invention, and protection scope of the present invention should be limited and is as the criterion with claims.
Claims (6)
1. the reliability verification method of a Nonvolatile memory is characterized in that: comprising:
Determine a programm voltage and the memory cell array relation curve between serviceable life;
Estimate the programm voltage of this memory cell array at an intended life;
From this relation curve, try to achieve an accelerated test programm voltage and a test duration to this programm voltage that should intended life;
With this accelerated test voltage, in this test duration, test continuously;
All storage unit in this memory cell array are carried out a checking of procedure stores state, and judge whether that all storage unit are after this test duration of process in this memory cell array, whether all maintain this program state, wherein all maintain this during program state when all storage unit in this memory cell array, then be judged as this memory cell array and have this serviceable life; When the partial memory cell in this memory cell array does not maintain this during program state, then be judged as this memory cell array and do not have this serviceable life.
2. the reliability verification method of Nonvolatile memory according to claim 1 is characterized in that: this programm voltage pair and memory cell array this relation curve between serviceable life are linear.
3. the reliability verification method of a Nonvolatile memory is characterized in that: comprising:
According to the relation of a programm voltage, estimate the programm voltage of this memory cell array at an intended life to the serviceable life of memory cell array;
Try to achieve an accelerated test programm voltage and a test duration to this programm voltage that should intended life;
With this accelerated test programm voltage, in this test duration, test continuously;
All storage unit in this memory cell array are carried out a checking of procedure stores state, and judge whether whether all storage unit all maintain this program state through after this test duration in this memory cell array.
4. the reliability verification method of Nonvolatile memory according to claim 3 is characterized in that: this programm voltage pair is linear with the relation in memory cell array serviceable life.
5. the reliability demonstration circuit of a Nonvolatile memory, in order to test a memory cell array, wherein this memory cell array has plurality of memory cells, arrange formation with several column and row, wherein respectively these row are couple to a novel word-line driver design for pseudo two-port, and respectively this row is couple to a bit line bias circuit, it is characterized in that: the reliability demonstration circuit of this Nonvolatile memory comprises a programm voltage access control unit, be couple to this memory cell array, in order to each those storage unit is carried out the control and the checking of program state.
6. Nonvolatile memory circuit with reliability demonstration circuit is characterized in that: comprising:
One memory cell array has plurality of memory cells, arranges with row with several column to constitute;
One character line driving circuit is coupled to each those row, in order to drive each those row;
One bit line bias circuit is coupled to each those row, in order to drive each those row;
One programm voltage access control unit is couple to this memory cell array, in order to each those storage unit is carried out the control and the checking of program state.
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| CN 01130672 CN1215481C (en) | 2001-08-17 | 2001-08-17 | Method for proving non-volatile internal memory reliability and circuit |
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| CN 01130672 CN1215481C (en) | 2001-08-17 | 2001-08-17 | Method for proving non-volatile internal memory reliability and circuit |
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| CN110232948B (en) * | 2019-05-28 | 2020-10-30 | 华中科技大学 | Method and system for measuring health degree of UFS chip in UFS storage device |
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