CN1404131A - Making process of embedded intraconnection wire structure - Google Patents
Making process of embedded intraconnection wire structure Download PDFInfo
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- CN1404131A CN1404131A CN 01131054 CN01131054A CN1404131A CN 1404131 A CN1404131 A CN 1404131A CN 01131054 CN01131054 CN 01131054 CN 01131054 A CN01131054 A CN 01131054A CN 1404131 A CN1404131 A CN 1404131A
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Abstract
The making process of embedded intraconnection wire structure includes the following successive steps: forming dielectric layer on semiconductor substrate; etching the said dielectric layer to form channel; forming barrier layer the side wall and bottom of the channel; forming metal layer on the barrier layer and filling the said channel; grinding chemical and mechanically to eliminate the barrier layer and metal layer on the dielectric layer; reducing synchronously via introducing silane to eliminate the metal oxide on the surface of the metal layer; and forming conductive sealing layer on the surface of the metal layer to conver the metal layer. The said process has relatively high attachment of the sealing layer to the metal layer.
Description
Technical field
The invention relates to a kind of lead processing procedure of inlaying, particularly relevant for a kind of manufacture method of embedded intraconnection wire structure, in inlaying the lead processing procedure, form the higher conductivity sealant of degree of adhering in layer on surface of metal, to improve the degree of adhering to of sealant and metal level.
Background technology
As everyone knows, inlaying the lead processing procedure is a kind of metal internal connecting line processing procedure.Traditional lead processing procedure of inlaying mainly is after defining the mosaic texture zone that connects intraconnections, form a barrier layer in the dielectric layer surface that isolates intraconnections and the inwall of mosaic texture again, and then with the preferable metal material of conductivity, for example materials such as copper, aluminium tungsten or aluminium copper are inserted above-mentioned mosaic texture.Then, grind with chemical mechanical milling method excess metal material that irrigation canals and ditches are outer and barrier layer again and remove, and in this mosaic texture, form one and connect the lead of inlaying that intraconnections uses.The step that tradition is inlayed the lead processing procedure is as follows:
Fig. 1-Fig. 4 is the processing procedure generalized section of inlaying lead of conventional art.
At first, consult Fig. 1, semiconductor substrate 100 is provided; Secondly, utilize metallization process on the semiconductor-based end 100, to form an intraconnections 110; Then, form a sealant 120 to cover intraconnections 110; Form dielectric layer 130 in sealant 120 surfaces then, wherein, the material of sealant 120 can be silicon nitride (SiN) or carborundum (SiC), its effect is to be used for sealing intraconnections 110, and the metal that prevents intraconnections 110 is difficult to diffuse to other zone and causes line short, and dielectric layer 130 can be simple layer or is made of the heterozygosis low-resistance matter dielectric material of multilayer, and it can optionally be adjusted;
Consult Fig. 2,, form the dual-damascene structure 140 that runs through dielectric layer 130 and sealant 120 and connection intraconnections 110 again with damascene process definition dielectric layer 130;
Consult Fig. 3, form barrier layer 150 with physics or chemical vapour deposition technique in dielectric layer 130 and dual-damascene structure 140 inwalls earlier; Then, form the preferable metal level 160 of conductivity in barrier layer 150 surfaces with chemical vapour deposition technique or physical vaporous deposition, and dual-damascene structure 140 filled up, wherein, the material of metal level 160 can be the preferable copper of conductivity, aluminium, tungsten, aluminium copper etc.;
Consult Fig. 4, after metal level 160 forms, utilize chemical mechanical milling method (CMP) to carry out planarization, excess metal layer 160 beyond the dual-damascene structure 140 and barrier layer 150 are removed; At last, cover a sealant 170 in layer on surface of metal, this sealant 170 is identical with the material of above-mentioned sealant 120.Its major defect is:
1, above-mentioned sealant 120 and 170 and can't provide and metal level 110 and 160 between good degree of adhering to.The sealant of commonly using with tradition, it generally is employing silicon nitride or carborundum material as sealant, the sealant of above-mentioned material also can't adhere to copper metal layer, causes electromigration (electro-migration) effect to take place, and makes copper diffuse to other unnecessary position.
2, behind the cmp processing procedure, can produce metal oxide at layer on surface of metal usually, if it is not removed, will improve the impedance of plain conductor, and influence the electron mobility effect of plain conductor.
3, because the generation of metal oxide will cause the surface elevation of plain conductor, make the formed sealant of successive process can't be effectively and metal level adhere to, more reduced the degree of adhering to of metal level and sealant, and then influenced the manufacturing and the productive rate of subsequent components.
Summary of the invention
Main purpose of the present invention provides a kind of manufacture method of embedded intraconnection wire structure, only form a conductivity sealant in layer on surface of metal, the material of this conductivity sealant is titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) etc., and the scope of its thickness is about between the 20-150 dust, overcome the drawback of prior art, reach and make sealant and metal level have the purpose of preferable degree of adhering to.
The object of the present invention is achieved like this: 1, a kind of manufacture method of embedded intraconnection wire structure is characterized in that: it comprises the following step at least successively:
(1) provides the semiconductor substrate;
(2) form a dielectric layer in described substrate;
(3) the described dielectric layer of etching is to form a groove;
(4) form a barrier layer in the sidewall and the bottom of described dielectric layer and groove;
(5) form a metal level in described barrier layer, and fill up described groove;
(6) carry out the cmp processing procedure, to carry out the planarization of described layer on surface of metal;
(7) form a conductivity sealant to cover the surface of described metal level.
It more comprises the following steps: this method after carrying out the cmp processing procedure, carries out reduction processing procedure synchronously, by feeding reducing gas, to remove the metal oxide of described layer on surface of metal.The material of described sealant is selected from one of them of titanium, titanium nitride, tantalum, tantalum nitride.The material of described metal level is a copper.Described reducing gas is a silane.Described reducing gas is selected from least a of ammonia, hydrogen, silane.The scope of described conductivity sealant thickness is between the 20-150 dust.
The manufacture method of another kind of embedded intraconnection wire structure, it is characterized in that: it comprises the following step at least successively:
(1) provides the semiconductor-based end with intraconnections;
(2) form the first conductivity sealant to cover described intraconnections;
(3) form a dielectric layer to cover the described first conductivity sealant and the semiconductor-based end;
(4) define described dielectric layer with damascene process, form the mosaic texture that runs through described dielectric layer and connect the described first conductivity sealant;
(5) form a barrier layer in the sidewall and the bottom of described dielectric layer and mosaic texture;
(6) form a metal level in described barrier layer, and fill up described mosaic texture;
(7) carry out the cmp processing procedure, to carry out the planarization on described mosaic texture surface;
(8) carry out reduction processing procedure synchronously, feed a reducing gas, to remove the metal oxide of described layer on surface of metal;
(9) form one second conductivity sealant to cover described metal level and dielectric layer.
The material of described first and second conductivity sealant is to be selected from one of them of titanium, titanium nitride, tantalum, tantalum nitride.The material of described metal level is a copper.Described reducing gas is be selected from ammonia, hydrogen, silane at least a.The scope of described first and second conductivity sealant thickness is between the 20-150 dust.
Describe in detail below in conjunction with the preferred embodiment conjunction with figs..
Description of drawings
Fig. 1-Fig. 4 is the generalized section of inlaying the lead processing procedure of conventional art.
Fig. 5-Figure 14 is a generalized section of inlaying the lead processing procedure of the present invention.
Embodiment
Consult shown in Fig. 5-14, the lead section processing procedure of inlaying of the present invention comprises the steps:
Consult shown in Figure 5ly, semiconductor substrate 200 is provided; Then, form an inner metal dielectric layer (interretal dielectric layer) 210 in substrate 200, wherein, inner metal dielectric layer 210 is constituted for simple layer or by the heterozygosis low-resistance matter dielectric material of multilayer, and its composition minute can optionally be adjusted;
Consult shown in Figure 6, utilize little shadow technology (lithography technofogy) etching inner metal dielectric layer 210, to form groove 220A and 220B, this can non-grade to etching (anisotropically etching process) etching inner metal dielectric layer 210, and the degree of depth of groove 220A and 220B is about the 2000-6000 dust.
Consult shown in Figure 7ly, form a barrier layer 230 in sidewall and the bottom of inner metal dielectric layer 210 and groove 220A and 220B; Then, form metal level 240 in barrier layer 230, wherein, metal level 240 materials can be the preferable copper of conductivity, aluminium, tungsten, aluminium copper etc.In the present embodiment, be to be example, and groove 220A and 220B are filled up with the copper metal.
Consult shown in Figure 8ly, carry out the cmp processing procedure, the barrier layer 230 and the metal level 240 that will be positioned at inner metal dielectric layer 210 tops remove.
Yet, in the process of carrying out the cmp processing procedure, be arranged in the remaining metal level of groove 220A and 220B 240 surfaces, may be because the cmp processing procedure, and generation metal oxide (Cu
2O), this metal oxide will cause the surface elevation of metal level 240, make the formed sealant of successive process can't be effectively and metal level 240 adhere to, reduced the degree of adhering to of metal level and sealant, and influenced the reliability of product.
Therefore, carry out reduction processing procedure synchronously, will produce metal oxide (Cu because of the cmp processing procedure
2O) mode that replaces by free radical is reduced into the copper metal, and its mode is to feed reducing gas to chamber, to reduce above-mentioned metal oxide.In the present embodiment, reducing gas can be ammonia (NH
3), hydrogen (H
2), silane (SiH
4), or ammonia (NH
3) and hydrogen (H
2) mist, and silane (SiH
4) and hydrogen (H
2) mist, be with silane (SiH at this
4) be example.And the condition of carrying out synchronous reduction processing procedure is as follows: the reducing gas flow rates is between the 20-400sccm, and the chamber pressure scope is between the 0.01-10.0torr, and operating temperature range is between 180-620 ℃.
After synchronous reduction processing procedure is finished, can eliminate metal level 240 surfaces because the metal oxide (Cu that the cmp processing procedure is produced
2And make the surface of metal level 240 reach the effect of planarization O).
Consult shown in Figure 9, form conductivity sealant 250 respectively at metal level 240 surfaces, that is sealant 250 is only to be covered in metal level 240 surfaces at this moment, the material of above-mentioned conductivity sealant 250 can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) etc., and the scope of its thickness is about between the 20-150 dust.In addition, above-mentioned conductivity sealant 250 technology that is formed at metal level 240 can comprise sputter process, specific chemical reaction, metal silicide reaction etc.
In the present embodiment, form the reliability that conductivity sealant 250 can improve semiconductor subassembly.Its reason is that conductivity sealant 250 will form corresponding compound according to the material of conductivity sealant 250 with the face that connects between the metal level 240, for example, copper-titanium alloy (CuTi), copper titanium nitrogen compound (CuTiN), copper tantalum alloy (CuTa), copper tantalum nitrogen compound (CuTaN) etc., make conductivity sealant 250 and metal level 240 combine closely, significantly improve the degree of adhering to of conductivity sealant 250 and metal level 240.
Consult shown in Figure 10ly, form inner metal dielectric layers 260 in conductivity sealant 250 surface.Wherein, inner metal dielectric layer 260 can be simple layer or is made of the heterozygosis low-resistance matter dielectric material of multilayer, and it can optionally be adjusted.
Consult shown in Figure 11ly,, form one and run through inner metal dielectric layer 260 and the dual-damascene structure 270A that is connected with conductivity sealant 250 and inlay irrigation canals and ditches 270B again with damascene process definition inner metal dielectric layer 260.
Consult Figure 12, form barrier layer 280 with physics or chemical vapour deposition technique in inner metal dielectric layer 260 and dual-damascene structure 270A, 270B inwall earlier; Then, form the preferable metal level 290 of conductivity with chemical vapour deposition technique, and dual-damascene structure 270A, 270B are filled up in barrier layer 280 surfaces.Wherein, the material of metal level 290 can be the preferable copper of conductivity, aluminium, tungsten, aluminium copper etc., in the present embodiment, is the example explanation with the copper metal.
Consult shown in Figure 13ly, carry out the cmp processing procedure, the barrier layer 280 and the metal level 290 that will be positioned at inner metal dielectric layer 260 tops remove.Yet identical in previous situation, metal level 290 surfaces will produce unnecessary metal oxide (Cu because of the cmp processing procedure
2O).
Therefore, carry out reduction processing procedure synchronously, will produce metal oxide (Cu because of the cmp processing procedure
2O), the mode by being replaced by free radical is reduced into the copper metal, and its mode is to feed reducing gas to chamber, to reduce above-mentioned metal oxide.In the present invention, reducing gas can be ammonia (NH
3), hydrogen (H
2), silane (SiH
4), or ammonia (NH
3) and hydrogen (H
2) mist, in the present embodiment, be to adopt silicon-containing gas as reducing gas.And the condition of carrying out synchronous reduction processing procedure is as follows: the reducing gas flow rates is between the 20-400sccm, and the chamber pressure scope is between the 0.01-10.0torr, and operating temperature range is between 180-620 ℃.
Consult shown in Figure 14, form conductivity sealant 300 respectively at metal level 290 surfaces, that is sealant 300 is only to be covered in metal level 290 surfaces at this moment, the material of above-mentioned conductivity sealant 300 can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) etc., and the scope of its thickness is about between the 20-150 dust.In addition, above-mentioned conductivity sealant 300 technology that is formed at metal level 290 can comprise sputter process, specific chemical reaction, metal silicide reaction etc.
Same, in the present embodiment,, improve the reliability of semiconductor subassembly by forming conductivity sealant 300.Its reason is that conductivity sealant 300 will form corresponding compound according to the material of conductivity sealant 300 with the face that connects between the metal level 290, for example, copper-titanium alloy (CuTi), copper titanium nitrogen compound (CuTiN), copper tantalum alloy (CuTa), copper tantalum nitrogen compound (CuTaN) etc., make conductivity sealant 300 and metal level 290 combine closely, significantly improve the degree of adhering to of conductivity sealant 300 and metal level 290.Moreover, after sealant 250 is formed at metal level 240 surfaces, because sealant 250 is the cause of conductivity, when the metal level among the formed dual-damascene structure 270A of subsequent step 290 is desired with metal level 240 electrically connects, sealant 250 need not be removed and can be finished, with this chance that can reduce metal level 240 oxidations, improved elasticity for processing procedure waiting time (queuetime) control.
In sum, according to the lead processing procedure of inlaying of the present invention, when the conductivity sealant that will have an above-mentioned material is formed at metal level, because the characteristic of conductivity sealant material will be attached to metal level closely.Improve the reliability of semiconductor subassembly, and improved the problem of conventional art in tack and electron mobility effect.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting scope of the present invention, anyly has the knack of this skill person, and without departing from the spirit and scope of the present invention, a little change and the retouching done all belongs within protection scope of the present invention.
Claims (13)
1, a kind of manufacture method of embedded intraconnection wire structure is characterized in that: it comprises the following step at least successively:
(1) provides the semiconductor substrate;
(2) form a dielectric layer in described substrate;
(3) the described dielectric layer of etching is to form a groove;
(4) form a barrier layer in the sidewall and the bottom of described dielectric layer and groove;
(5) form a metal level in described barrier layer, and fill up described groove;
(6) carry out the cmp processing procedure, to carry out the planarization of described layer on surface of metal;
(7) form a conductivity sealant to cover the surface of described metal level.
2, the manufacture method of embedded intraconnection wire structure according to claim 1, it is characterized in that: further comprising the following step: after carrying out the cmp processing procedure, carry out reduction processing procedure synchronously, by feeding reducing gas, to remove the metal oxide of described layer on surface of metal.
3, the manufacture method of embedded intraconnection wire structure according to claim 1 and 2 is characterized in that: the material of described sealant is selected from one of them of titanium, titanium nitride, tantalum, tantalum nitride.
4, the manufacture method of embedded intraconnection wire structure according to claim 1 and 2 is characterized in that: the material of described metal level is a copper.
5, the manufacture method of embedded intraconnection wire structure according to claim 1 and 2 is characterized in that: described reducing gas is a silane.
6, the manufacture method of embedded intraconnection wire structure according to claim 1 and 2 is characterized in that: described reducing gas is selected from least a of ammonia, hydrogen, silane.
7, the manufacture method of embedded intraconnection wire structure according to claim 1 and 2 is characterized in that: the scope of described conductivity sealant thickness is between the 20-150 dust.
8, a kind of manufacture method of embedded intraconnection wire structure is characterized in that: it comprises the following step at least successively:
(1) provides the semiconductor-based end with intraconnections;
(2) form the first conductivity sealant to cover described intraconnections;
(3) form a dielectric layer to cover the described first conductivity sealant and the semiconductor-based end;
(4) define described dielectric layer with damascene process, form the mosaic texture that runs through described dielectric layer and connect the described first conductivity sealant;
(5) form a barrier layer in the sidewall and the bottom of described dielectric layer and mosaic texture;
(6) form a metal level in described barrier layer, and fill up described mosaic texture;
(7) carry out the cmp processing procedure, to carry out the planarization on described mosaic texture surface;
(8) carry out reduction processing procedure synchronously, feed a reducing gas, to remove the metal oxide of described layer on surface of metal;
(9) form one second conductivity sealant to cover described metal level and dielectric layer.
9, the manufacture method of embedded intraconnection wire structure according to claim 8 is characterized in that: the material of described first and second conductivity sealant is to be selected from one of them of titanium, titanium nitride, tantalum, tantalum nitride.
10, the manufacture method of embedded intraconnection wire structure according to claim 8 is characterized in that: the material of described metal level is a copper.
11, the manufacture method of embedded intraconnection wire structure according to claim 8 is characterized in that: described reducing gas is a silane.
12, the manufacture method of embedded intraconnection wire structure according to claim 8 is characterized in that: described reducing gas is be selected from ammonia, hydrogen, silane at least a.
13, the manufacture method of embedded intraconnection wire structure according to claim 8 is characterized in that: the scope of described first and second conductivity sealant thickness is between the 20-150 dust.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01131054 CN1404131A (en) | 2001-09-10 | 2001-09-10 | Making process of embedded intraconnection wire structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01131054 CN1404131A (en) | 2001-09-10 | 2001-09-10 | Making process of embedded intraconnection wire structure |
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| CN1404131A true CN1404131A (en) | 2003-03-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237297A (en) * | 2010-04-29 | 2011-11-09 | 武汉新芯集成电路制造有限公司 | Manufacturing method and planarization process of metal interconnection structure |
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2001
- 2001-09-10 CN CN 01131054 patent/CN1404131A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237297A (en) * | 2010-04-29 | 2011-11-09 | 武汉新芯集成电路制造有限公司 | Manufacturing method and planarization process of metal interconnection structure |
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