CN1404127A - Double-embedded structure with capacitor and its making process - Google Patents
Double-embedded structure with capacitor and its making process Download PDFInfo
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- CN1404127A CN1404127A CN 02106992 CN02106992A CN1404127A CN 1404127 A CN1404127 A CN 1404127A CN 02106992 CN02106992 CN 02106992 CN 02106992 A CN02106992 A CN 02106992A CN 1404127 A CN1404127 A CN 1404127A
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Abstract
The present invention is double-embedded structure with capacitor and its making process. Before the metal film capacitor is formed, the lower inner connecting wires are made via copper metal embedding. The first metal layer, the insulating layer and the second metal layer are deposited successively and the second metal layer is etched to define the electrode on the second metal layer. The insulating layer and the first metal layer and then defined via the second etching to form the lower electrode and metal wires. After the capacitor is made, the copper metal embedding is used to produce interconnection wires. The present invention has low production cost and stable electric performance of the formed capacitor.
Description
Technical field
The invention relates to a kind of integrated circuit that includes capacitor, particularly relevant for a kind of double-embedded structure and manufacture method thereof with capacitor.
Background technology
As everyone knows, capacitor can be integrated mutually with various integrated circuit.For example can be as decoupling capacitance device (decoupling capacitors), to be used for improving voltage-regulation (voltage regulation and the interference resistant ability (noise immunity) that distribute power (power distribution) is provided.Can also be applied in analogy/logical circuit, analogy one digital converter, mixed type signal (mixedsignal) or radio frequency (radio frequency) circuit operation or the like.
It is as described below that tradition is made the method for the semiconductor element comprise capacitor 20.
At first consult shown in Figure 1ly, deposition of aluminum metal level on insulating barrier 12 carries out micro image etching procedure subsequently, makes it be patterned to aluminum metal layer 14a and 14b.Wherein insulating barrier 12 comprise some be formed on the silicon base and substrate in element (not illustrating).
Then, as shown in Figure 2, on aluminum metal layer 14a and 14b and insulating barrier 12, form insulating barrier 16, in this insulating barrier 16, form tungsten plug (tungsten plug; W-plug) 18, in order to electrically connect aluminum metal layer 14a.Afterwards, on tungsten plug 18 and insulating barrier 16, utilize deposition and micro image etching procedure, form first conductive plate 21, insulating barrier 22 and second conductive plate 23, to constitute capacitor 20.Wherein first conductive plate 21 (being bottom electrode) is connected with aluminum metal layer 14a via tungsten plug 18.
Continue at capacitor 20 and insulating barrier 16 tops deposit another layer insulating 26, and in the insulating barrier 16 of insulating barrier 26 and its below, form tungsten plug 28a and 28b simultaneously, as shown in Figure 3.
Then, carry out micro image etching procedure subsequently and be patterned into aluminum metal layer 34a and 34b, as shown in Figure 4 in insulating barrier 26 and tungsten plug 28a and 28b top deposition layer of aluminum metal level.Wherein aluminum metal layer 34a is a top electrode via the tungsten plug 28a and second conductive plate 23) electrically connect, and aluminum metal layer 34b electrically connects via tungsten plug 28b and aluminum metal layer 14b.Its major defect is:
In the above-mentioned conventional method that capacitor 20 is integrated into integrated circuit, need extra little shadow step form capacitor 20, thereby increased the cost of whole manufacture of semiconductor.
Yet,, can't satisfy requirement to speed with the lead that aluminum metal was constituted along with the raising of element integration and data transmission speed increase, therefore, as lead, postponing (RC delay) to reduce RC with metallic copper with high conductivity, is to be present trend.
But the copper metal can't come define pattern in the mode of dry ecthing, and its reason is the copper chloride (CuCl that copper metal and the gas reaction of chlorine electricity slurry generate
2) boiling point high (about 1500 ℃), so the making of copper conductor needs to carry out with damascene process (damascene process).
At United States Patent (USP) the 6th, 180, in 976BI number, disclose a kind of film capacitor that combines with damascene process and its manufacture method, wherein the bottom electrode of capacitor also utilizes damascene process to form.Compare with the processing procedure of the capacitor described in Fig. 1 to Fig. 4, though it can reduce little shadow step together, yet, because the formation of its bottom electrode is to need fiting chemical mechanical lapping processing procedure so that unnecessary metal material is worn, when the cmp processing procedure proceeds to a degree, can cause the surface of formed bottom electrode that dishization (dishing) phenomenon is arranged because the metal that is ground is different with the grinding rate between the barrier layer.Because the dish phenomenon makes that the air spots of bottom electrode is smooth, influenced the uniformity and the consistency of the thickness of its formed insulating barrier in top, cause the electrical quality instability of formed capacitor.
Summary of the invention
The purpose of this invention is to provide a kind of double-embedded structure with capacitor, by using copper mosaic process and aluminum manufacturing procedure simultaneously, because the importing of copper mosaic process, the live width that reaches lead is easy to dwindle, and improves the purpose of the transmission rate of intraconnections.
Another object of the present invention provides a kind of manufacture method with dual damascene of capacitor, by using quite few lithography step, forms plain conductor simultaneously, when being integrated into capacitor in the integrated circuit, only needs extra one light shield to form top electrode; The surface of formed bottom electrode has preferable flatness, makes the thickness of its formed insulating barrier in top have preferable uniformity and consistency, reaches the more stable purpose of electrical quality that reduces processing procedure cost and formed capacitor.
The object of the present invention is achieved like this: a kind of double-embedded structure with capacitor is characterized in that: which comprises at least following structure:
First copper conductor and second copper conductor are arranged in first insulating barrier; First sealant is arranged on this first and second copper conductor; Second insulating barrier is arranged on this first sealant; The 3rd insulating barrier is arranged on this second insulating barrier; The first bronze medal connector and the second bronze medal connector are arranged in this first sealant, this second and the 3rd insulating barrier; Bottom electrode is arranged on the 3rd insulating barrier, and this bottom electrode electrically connects via this first bronze medal connector and this first copper conductor; Plain conductor is arranged on the 3rd insulating barrier, and this plain conductor electrically connects via this second bronze medal connector and this second copper conductor; The 4th insulating barrier is arranged on this bottom electrode and this plain conductor; Top electrode is arranged on the 4th insulating barrier, and with this bottom electrode toward each other; The 5th insulating barrier of tool flat surfaces is arranged on this top electrode, the 4th insulating barrier and the 3rd insulating barrier; The first bronze medal mosaic-like structure and the second bronze medal mosaic-like structure are configured in the 5th insulating barrier and the 4th insulating barrier, wherein this first bronze medal mosaic-like structure is made of the 3rd copper conductor and the 3rd bronze medal connector, this second bronze medal mosaic-like structure is made of the 4th copper conductor and the 4th bronze medal connector, wherein this top electrode electrically connects via the 3rd bronze medal connector and the 3rd copper conductor, and this plain conductor electrically connects via the 4th bronze medal connector and the 4th copper conductor; Second sealant is arranged on this third and fourth copper conductor.
The material of this bottom electrode and this plain conductor is to select from aluminium, aluminium copper, silver or golden one of them.The material of the 4th insulating barrier is selected at least a from silicon nitride, silicon oxynitride, carborundum, tantalum oxide, cobalt oxide, hafnium oxide or aluminium oxide.The material of this top electrode is selected from one of them of titanium, titanium nitride, tantalum, tantalum nitride, aluminium or aluminium copper.The scope of this bottom electrode equals the scope of top electrode.The scope of this bottom electrode is greater than the scope of top electrode.The thickness of this top electrode is between 200 dust to 1500 dusts.The thickness of this bottom electrode and this plain conductor is identical, and between 300 dust to 2000 dusts.Comprise that more a hard cover screen is mediate in this pentasyllabic quatrain edge exhibition.The 5th insulating barrier equals the height of this third and fourth copper conductor in the thickness of this curtain layer of hard hood top.The 5th insulating barrier equals the height of this third and fourth bronze medal connector in the thickness of this curtain layer of hard hood below.The material of this curtain layer of hard hood is a silicon nitride.
The present invention also provides a kind of manufacture method with double-embedded structure of capacitor, it is characterized in that: which comprises at least following steps:
First insulating barrier is provided;
In this first insulating barrier, form first copper conductor and second copper conductor;
Form first sealant on this first and second copper conductor to being less than;
On this first sealant, form second insulating barrier;
On this second insulating barrier, form the 3rd insulating barrier, with usefulness as etching stopping layer;
In this first sealant, this second and the 3rd insulating barrier, form the first bronze medal connector and the second bronze medal connector;
On the 3rd insulating barrier and this first and second bronze medal connector, form the first metal layer;
On this first metal layer, form the 4th insulating barrier;
On the 4th insulating barrier, form second metal level;
With this second metal layer patternization, to transfer top electrode to;
With the 4th insulating barrier and this first metal layer patterning, make this first metal layer transfer bottom electrode and plain conductor to, this bottom electrode electrically connects via this first bronze medal connector and this first copper conductor, and this plain conductor electrically connects via this second bronze medal connector and this second copper conductor;
Formation has the 5th insulating barrier of flat surfaces, is covered on this top electrode, the 4th insulating barrier and this etch stop layer;
Form most double-mosaic patterns in the 5th insulating barrier, this double-mosaic pattern comprises most grooves and most interlayer fenestras;
In those grooves, form the 3rd copper conductor and the 4th copper conductor, and in those interlayer fenestras, form the 3rd bronze medal connector and the 4th bronze medal connector, wherein this top electrode electrically connects via the 3rd bronze medal connector and the 3rd copper conductor, and this plain conductor electrically connects via the 4th bronze medal connector and the 4th copper conductor;
Form second sealant on this third and fourth copper conductor to being less than.
The material of this first metal layer is to select from aluminium, aluminium copper, silver or golden one of them.The material of the 4th insulating barrier is one of them of selecting from silicon nitride, silicon oxynitride, carborundum, tantalum oxide, zirconia, hafnium oxide or aluminium oxide.The material of this second metal level be select from titanium, titanium nitride, tantalum, tantalum nitride, aluminium or aluminium copper one of them.The scope of this bottom electrode equals the scope of this top electrode.The scope of this bottom electrode is greater than the scope of top electrode.This second metal layer thickness is between 200 dust to 1500 dusts.The thickness of this first metal layer is between 300 dust to 2000 dusts.Comprise more in the 5th insulating barrier that a hard cover screen is mediate.The 5th insulating barrier equals the height of this third and fourth copper conductor in the thickness of this curtain layer of hard hood top.The 5th insulating barrier equals the height of this third and fourth bronze medal connector in the thickness of this hard shielding layer below.The material of this curtain layer of hard hood is a silicon nitride.
Describe in detail below in conjunction with the preferred embodiment conjunction with figs..
Description of drawings
Fig. 1-Fig. 4 is that tradition is integrated into flow process generalized section in the integrated circuit with capacitor.
Fig. 5-Figure 13 is the structure section schematic diagram of the metal capacitor of the insulating barrier of the formation of the embodiment of the invention 1 with uniform thickness and the method that combines with damascene process.
Figure 14-Figure 16 is the structure section schematic diagram of the metal capacitor of the insulating barrier of the formation of the embodiment of the invention 2 with uniform thickness and the method that combines with another damascene process.
Embodiment
For the metal capacitor that forms insulating barrier and can combine, to reach the transmission rate that improves lead and the electrical quality of metal capacitor simultaneously with copper mosaic process with uniform thickness.Therefore, before forming metallized film capacitor, utilize copper damascene processing procedure to make intraconnections under it, form the first metal layer, insulating barrier and second metal level by deposition manufacture process, and utilize etching to define second metal level earlier with after forming top electrode, carry out the etching second time again and define insulating barrier and the first metal layer, to form bottom electrode and plain conductor simultaneously.After finishing capacitor, continue to utilize copper damascene processing procedure to make intraconnections on it.
Therefore, the invention provides a kind of double-embedded structure with capacitor, it is constructed as shown in figure 13.The first copper conductor 104a and the second copper conductor 104b are arranged among the first insulating barrier I06.The first sealant I08 is arranged on the above-mentioned first and second copper conductor 104a and 104b.First insulating barrier 116 is arranged on first sealant 108.One the 3rd insulating barrier 118 is arranged on second insulating barrier 116.One first bronze medal connector 124a and one first bronze medal connector 124b are arranged in first sealant 108, the 2nd t city edge layer 116 and the 3rd insulating barrier 118.One bottom electrode 126a is arranged on the 3rd insulating barrier 118, and bottom electrode 126a electrically connects via the first bronze medal connector 124a and the first copper conductor 104a.One plain conductor 126b is arranged on the 3rd insulating barrier 118, and this plain conductor 126b electrically connects via the second bronze medal connector 124b and the second copper conductor I04b.One insulating barrier 128a and 128b is arranged on the bottom electrode 126a metal lead 126b.One top electrode 130a is arranged on the 4th insulating barrier 128a, and with bottom electrode 126a toward each other.The 5th insulating barrier 138 of one tool flat surfaces is arranged on top electrode 130a, the 4th insulating barrier 128a and 128b and the 3rd insulating barrier 118.One first bronze medal mosaic-like structure and one second bronze medal mosaic-like structure, be configured among the 5th insulating barrier 138 and the 4th insulating barrier 128b, wherein the first bronze medal mosaic-like structure is made of one the 3rd copper conductor 148a and one the 3rd bronze medal connector 146a, the first bronze medal mosaic-like structure is made of one the 4th copper conductor 148b and one the 4th bronze medal connector 1 b that oozes, wherein top electrode 130a electrically connects via the 3rd bronze medal connector 146a and the 3rd copper conductor 148a, and plain conductor 126b electrically connects via the 4th bronze medal connector 146b and the 4th copper conductor 148b.One.Sealant 150 is arranged on the third and fourth copper conductor 148a and the 148b
Below with the manufacture method of the above-mentioned structure of specific embodiment 1 and embodiment 2 explanations
Embodiment 1
Consult Fig. 5-shown in Figure 13, a kind of formation of embodiments of the invention 1 has the metal capacitor of insulating barrier of uniform thickness and the structure of the method that combines with damascene process.
At first consult shown in Figure 5ly, on insulating barrier 102, form another layer insulating I06, and utilize damascene process in this insulating barrier I06, to form copper conductor 104a and the 104b that thickness is about 2000 to 6000 dusts.Wherein may comprise other intraconnections in the insulating barrier 102, and insulating barrier 102 belows comprise be formed in the substrate and substrate in element.Describe content of the present invention in order to know, the circuit element of these bottoms is also not shown in the diagram.The formation method of copper conductor 104a and 104b for instance, is form groove in insulating barrier 106 after, behind the barrier layer 103 of formation one deck compliance, inserts the copper metal, carries out cmp afterwards, with worn unnecessary copper metal and barrier layer 103.Then forming sealant 108 at least on copper conductor 104a and 104b, is to be example to form comprehensive sealant 108 in the drawings, and its thickness is about the 100-400 Izod right side, and its material can be silicon nitride (SiN) or carborundum (SiC).
Then consult shown in Figure 6ly, form a layer insulating 116 and insulating barrier 118 in regular turn on sealant 108, wherein insulating barrier 118 is the usefulness as etching stopping layer, and its material can be silicon nitride, and different with insulating barrier 116, and the material of insulating barrier 116 can be silica.Cover one deck photoresist design layer 120 afterwards on as the insulating barrier 118 of etching stopping layer, it has the pattern of interlayer hole.
Then consult shown in Figure 7ly, the design transfer of this photoresist design layer 120 to insulating barrier 118, insulating barrier 116 and sealant 108, is used to wherein form the interlayer fenestra and exposes and desire to do the electrical zone that contacts with copper conductor 104a and 104b.Remove photoresist design layer 120 afterwards, for example remove with dry-etching or Wet-type etching.Form the barrier layer (not illustrating) and the copper metal layer of compliance in regular turn, utilize the cmp processing procedure to remove unnecessary part again, to form copper connector 124a and 124b.
Then consult shown in Figure 8, depositing metal layers 126, insulating barrier 128 and metal level 130 in regular turn on insulating barrier 118 and copper connector 124a and 124b.Wherein metal level 126 is that its thickness is about the 300-2000 dust with the usefulness in order to formation bottom electrode and lead; Insulating barrier 128 is in order to constituting capacitor, and its thickness is about the 100-1200 dust, yet actual thickness still needs the application of apparent capacity device and required capacitance thereof and decides; Metal level 130 is with in order to form top electrode, and its thickness is about the 200-1500 dust.The material of above-mentioned metal level 130 can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminium, aluminium copper (AlCu) etc.The material of insulating barrier 116 can be silicon nitride, silicon oxynitride, carborundum (SiC), tantalum oxide (TaO
2), cobalt oxide (ZrO
2), hafnium oxide (HfO
2), aluminium oxide (Al
2O
3) etc.The material of metal level 126 can be aluminium, aluminium copper, silver or golden.
Then consult shown in Figure 9, the definition metal level 130, its method is for carrying out a micro image etching procedure, so that metal level 130 patterns are dissolved top electrode 130a.
Then consult shown in Figure 10, another road micro image etching procedure then carries out, cooperation with insulating barrier 118 as etching stopping layer, control the opportunity of finishing etching step, in order to definition insulating barrier 128 and metal level 126, to define lead 126b and bottom electrode 126a simultaneously, insulating barrier 128 then transfers insulating barrier 128b that is positioned at lead 126b top and the insulating barrier 128a that depends on bottom electrode 126a top to.The zone of wherein formed bottom electrode 126a and insulating barrier 128a is regional corresponding with top electrode 130a roughly, and the zone of bottom electrode 126a and insulating barrier 128a needs the zone more than or equal to top electrode 130a.
Then consult shown in Figure 11, fill out ability good insulation performance layer 134 in insulating barrier 118, edge layer 128a and 128b and top electrode 130a top covering one deck ditch, it can be and utilizes the high-density electric slurry sedimentation to come cvd silicon oxide, or utilizes rubbing method to be coated with spin-on glasses (spin-on glass; SOG), spin-coating macromolecule (spin-on polymer; SOP) etc.Form one deck code-pattern expendable insulating layer 136 afterwards in insulating barrier 134 tops, its material can be silica, follow the processing procedure that this expendable insulating layer 136 is carried out planarization, make the surface of insulating barrier 136 not be subjected to the influence of the hypsography that its below caused by lead 126b and capacitor 132, be beneficial to the carrying out of successive process.This planarization processing procedure can be the cmp processing procedure.For convenience of description, insulating barrier 134 and insulating barrier are referred to as insulating barrier 138 below 136.
Then carry out double-insert process, consult shown in Figure 12, form the pattern of dual damascene in insulating barrier 138 and insulating barrier 128b, this pattern is made of groove 142 and interlayer fenestra 140, and interlayer fenestra 140 can expose the zone of the lead 126b and the top electrode 130a that desire to do electrical contact.
Then consult shown in Figure 13ly, form one deck barrier layer 144, and insert the copper metal, carry out cmp afterwards,, and in double-mosaic pattern, form copper conductor 148a and 148b and copper connector 146a and 146b with worn unnecessary copper metal.In copper conductor 148a and 148b and insulating barrier 138 tops covering one deck sealants (sealing layer) 150, its material can be silicon nitride or carborundum afterwards.So top electrode 130a electrically connects via copper connector 146a and copper conductor 148a, lead 126b then electrically connects via copper connector 146b and copper conductor 148b.
Follow-up copper wiring is still proceeded, till the manufacturing of finishing whole intraconnections.
Above-mentioned insulating barrier 102,106,116 and 136 material can be the insulation material (for example mix or unadulterated silica) of low-k, the spin-coating macromolecule of low-k (FLARE for example
, SiLK
TM, PAE-II
Deng) and chemical gas sedimentation type low-k material (breakdiamond for example
TM(BD
TM), Coral
TM, Greendot
TM, Aurora
TMDeng).
Embodiment 2
Consulting Figure 14-shown in Figure 16, is the structure of the metal capacitor of insulating barrier with uniform thickness of a kind of formation of the embodiment of the invention 2 and the method that combines with another damascene process.
Form the capacitor of the insulating barrier 128a with flat surfaces and the step of lead I26b simultaneously,, seldom do explanation at this as Fig. 5 of embodiment 1-shown in Figure 9.
After forming capacitor 132, the intraconnections of its top is to be undertaken by another kind of copper metal double-insert processing procedure in this embodiment.
Consult shown in Figure 14, fill out ability good insulation performance layer 134 in insulating barrier 118, insulating barrier 128a and 128b and top electrode I30a top covering one deck ditch, it can be and utilizes the high-density electric slurry sedimentation to come cvd silicon oxide, or utilizes rubbing method to be coated with spin-on glasses (SOG), spin-coating macromolecule (SOP) etc.Form one deck code-pattern expendable insulating layer 136 afterwards in insulating barrier 134 tops, its material can be silica, follow the processing procedure that this expendable insulating layer 136 is carried out planarization, make the surface of insulating barrier 136 not be subjected to the influence of the hypsography that its below caused by lead 126b and capacitor 132, be beneficial to the carrying out of successive process.This planarization processing procedure can be the cmp processing procedure.For convenience of description, insulating barrier 134 and insulating barrier are referred to as insulating barrier 138 below 136.
Be noted that: the gross thickness of insulating barrier 138 approximates the height of the interlayer hole that will form substantially.
Then form the insulating barrier 156 of skim on insulating barrier 138, this insulating barrier 156 has the pattern of interlayer hole, in order to the usefulness as hard cover screen.The material that is used to form insulating barrier 156 can be silicon nitride.Form the thicker insulating barrier of a layer thickness 158 in insulating barrier 156 tops as hard cover screen afterwards, its thickness approximates the height of the lead that will form substantially.
Then carry out double-insert process, consult shown in Figure 15ly, in insulating barrier 158 and insulating barrier 138, form groove 162 and interlayer fenestra 160 respectively, constitute the pattern of dual damascene.Wherein, interlayer fenestra 160 can expose the zone of the lead 126b and the top electrode 130a that desire to do electrical contact.
Then consult shown in Figure 16, on insulating barrier 158 and 138 and groove wherein 162 and interlayer fenestra 160 surfaces form the barrier layers 144 of one deck compliances, and insert the copper metal, carry out cmp afterwards, with worn unnecessary copper metal, and in double-mosaic pattern, form copper conductor 148a and 148b and copper connector 146a and 146b.Form one deck sealant 170 to the surface that is less than copper conductor 148a and 148b afterwards, be to be example in this figure to form the comprehensive sealant 170 of one deck, that is this sealant also is covered in insulating barrier 158 tops, and the material of sealant 170 can be silicon nitride or carborundum.
Above-mentioned insulating barrier 102,106,116,134,136 and 158 material can be the insulation material (for example mix or unadulterated silica) of low-k, the spin-coating macromolecule of low-k (for example FLARE, SiLK
TM, PAE-II etc.) and chemical gas sedimentation type low-k material (breakdiamond for example
TM(BD
TM), Coral
TM, Greendot
TM, Aurora
TMDeng).
Feature of the present invention and effect, in sum, the present invention has following advantage at least:
1, compare with the described conventional art of Fig. 1-Fig. 4, the present invention can use copper mosaic process and aluminum manufacturing procedure simultaneously.Because the importing of copper mosaic process, so the live width of lead is easy to dwindle, and can improve the transmission rate of intraconnections.
2, capacitor of the present invention is to utilize two stage lithography step to finish.And when the mode of utilizing lithography forms the bottom electrode of capacitor of the present invention, also form plain conductor simultaneously.Therefore, when being integrated into capacitor in the integrated circuit, only need extra one light shield to form top electrode, can reduce the processing procedure cost.
3, with United States Patent (USP) the 6th, 180, the technology that discloses in 976BI number is compared, and bottom electrode of the present invention does not pass through the cmp processing procedure, does not therefore have the dish phenomenon.So the surface of formed bottom electrode has preferable flatness, make the thickness of its formed insulating barrier in top have preferable uniformity and consistency, the electrical quality of formed capacitor is more stable.
Though the present invention discloses as above with preferred embodiment, so it is not in order to restriction the present invention, anyly has the knack of this skill person, and without departing from the spirit and scope of the present invention, institute does and changes and retouching, all belongs within protection scope of the present invention.
Claims (24)
1, a kind of double-embedded structure with capacitor is characterized in that: which comprises at least following structure:
First copper conductor and second copper conductor are arranged in first insulating barrier; First sealant is arranged on this first and second copper conductor; Second insulating barrier is arranged on this first sealant; The 3rd insulating barrier is arranged on this second insulating barrier; The first bronze medal connector and the second bronze medal connector are arranged in this first sealant, this second and the 3rd insulating barrier; Bottom electrode is arranged on the 3rd insulating barrier, and this bottom electrode electrically connects via this first bronze medal connector and this first copper conductor; Plain conductor is arranged on the 3rd insulating barrier, and this plain conductor electrically connects via this second bronze medal connector and this second copper conductor; The 4th insulating barrier is arranged on this bottom electrode and this plain conductor; Top electrode is arranged on the 4th insulating barrier, and with this bottom electrode toward each other; The 5th insulating barrier of tool flat surfaces is arranged on this top electrode, the 4th insulating barrier and the 3rd insulating barrier; The first bronze medal mosaic-like structure and the second bronze medal mosaic-like structure are configured in the 5th insulating barrier and the 4th insulating barrier, wherein this first bronze medal mosaic-like structure is made of the 3rd copper conductor and the 3rd bronze medal connector, this second bronze medal mosaic-like structure is made of the 4th copper conductor and the 4th bronze medal connector, wherein this top electrode electrically connects via the 3rd bronze medal connector and the 3rd copper conductor, and this plain conductor electrically connects via the 4th bronze medal connector and the 4th copper conductor; Second sealant is arranged on this third and fourth copper conductor.
2, the double-embedded structure with capacitor according to claim 1 is characterized in that: the material of this bottom electrode and this plain conductor is to select from aluminium, aluminium copper, silver or golden one of them.
3, the double-embedded structure with capacitor according to claim 1 is characterized in that: the material of the 4th insulating barrier is selected at least a from silicon nitride, silicon oxynitride, carborundum, tantalum oxide, cobalt oxide, hafnium oxide or aluminium oxide.
4, the double-embedded structure with capacitor according to claim 1, it is characterized in that: the material of this top electrode is selected from one of them of titanium, titanium nitride, tantalum, tantalum nitride, aluminium or aluminium copper.
5, the double-embedded structure with capacitor according to claim 1 is characterized in that: the scope of this bottom electrode equals the scope of top electrode.
6, the double-embedded structure with capacitor according to claim 1, it is characterized in that: the scope of this bottom electrode is greater than the scope of top electrode.
7, the double-embedded structure with capacitor according to claim 1 is characterized in that: the thickness of this top electrode is between 200 dust to 1500 dusts.
8, the double-embedded structure with capacitor according to claim 1 is characterized in that: the thickness of this bottom electrode and this plain conductor is identical, and between 300 dust to 2000 dusts.
9, the double-embedded structure with capacitor according to claim 1 is characterized in that: comprise that more a hard cover screen is mediate in this pentasyllabic quatrain edge exhibition.
10, the double-embedded structure with capacitor according to claim 9 is characterized in that: the 5th insulating barrier equals the height of this third and fourth copper conductor in the thickness of this curtain layer of hard hood top.
11, the double-embedded structure with capacitor according to claim 9 is characterized in that: the 5th insulating barrier equals the height of this third and fourth bronze medal connector in the thickness of this curtain layer of hard hood below.
12, the double-embedded structure with capacitor according to claim 9 is characterized in that: the material of this curtain layer of hard hood is a silicon nitride.
13, one of them described manufacture method with double-embedded structure of capacitor of a kind of claim 1-12 is characterized in that: which comprises at least following steps:
First insulating barrier is provided;
In this first insulating barrier, form first copper conductor and second copper conductor;
Form first sealant on this first and second copper conductor to being less than;
On this first sealant, form second insulating barrier;
On this second insulating barrier, form the 3rd insulating barrier, with usefulness as etching stopping layer;
In this first sealant, this second and the 3rd insulating barrier, form the first bronze medal connector and the second bronze medal connector;
On the 3rd insulating barrier and this first and second bronze medal connector, form the first metal layer;
On this first metal layer, form the 4th insulating barrier;
On the 4th insulating barrier, form second metal level;
With this second metal layer patternization, to transfer top electrode to;
With the 4th insulating barrier and this first metal layer patterning, make this first metal layer transfer bottom electrode and plain conductor to, this bottom electrode electrically connects via this first bronze medal connector and this first copper conductor, and this plain conductor electrically connects via this second bronze medal connector and this second copper conductor;
Formation has the 5th insulating barrier of flat surfaces, is covered on this top electrode, the 4th insulating barrier and this etch stop layer;
Form most double-mosaic patterns in the 5th insulating barrier, this double-mosaic pattern comprises most grooves and most interlayer fenestras;
In those grooves, form the 3rd copper conductor and the 4th copper conductor, and in those interlayer fenestras, form the 3rd bronze medal connector and the 4th bronze medal connector, wherein this top electrode electrically connects via the 3rd bronze medal connector and the 3rd copper conductor, and this plain conductor electrically connects via the 4th bronze medal connector and the 4th copper conductor;
Form second sealant on this third and fourth copper conductor to being less than.
14, the manufacture method with double-embedded structure of capacitor according to claim 13 is characterized in that: the material of this first metal layer is to select from aluminium, aluminium copper, silver or golden one of them.
15, the manufacture method with double-embedded structure of capacitor according to claim 13 is characterized in that: the material of the 4th insulating barrier is one of them of selecting from silicon nitride, silicon oxynitride, carborundum, tantalum oxide, zirconia, hafnium oxide or aluminium oxide.
16, the manufacture method with double-embedded structure of capacitor according to claim 13 is characterized in that: the material of this second metal level be select from titanium, titanium nitride, tantalum, tantalum nitride, aluminium or aluminium copper one of them.
17, the manufacture method with double-embedded structure of capacitor according to claim 13 is characterized in that: the scope of this bottom electrode equals the scope of this top electrode.
18, the manufacture method with double-embedded structure of capacitor according to claim 13, it is characterized in that: the scope of this bottom electrode is greater than the scope of top electrode.
19, the manufacture method with double-embedded structure of capacitor according to claim 13 is characterized in that: this second metal layer thickness is between 200 dust to 1500 dusts.
20, the manufacture method with double-embedded structure of capacitor according to claim 13 is characterized in that: the thickness of this first metal layer is between 300 dust to 2000 dusts.
21, the manufacture method with double-embedded structure of capacitor according to claim 13 is characterized in that: comprise more in the 5th insulating barrier that a hard cover screen is mediate.
22, the manufacture method with double-embedded structure of capacitor according to claim 21 is characterized in that: the 5th insulating barrier equals the height of this third and fourth copper conductor in the thickness of this curtain layer of hard hood top.
23, the manufacture method with double-embedded structure of capacitor according to claim 21 is characterized in that: the 5th insulating barrier equals the height of this third and fourth bronze medal connector in the thickness of this hard shielding layer below.
24, the manufacture method with double-embedded structure of capacitor according to claim 21 is characterized in that: the material of this curtain layer of hard hood is a silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02106992 CN1404127A (en) | 2001-08-22 | 2002-03-12 | Double-embedded structure with capacitor and its making process |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN01130732.3 | 2001-08-22 | ||
| CN01130732 | 2001-08-22 | ||
| CN 02106992 CN1404127A (en) | 2001-08-22 | 2002-03-12 | Double-embedded structure with capacitor and its making process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1404127A true CN1404127A (en) | 2003-03-19 |
Family
ID=25740534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02106992 Pending CN1404127A (en) | 2001-08-22 | 2002-03-12 | Double-embedded structure with capacitor and its making process |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100353487C (en) * | 2004-05-12 | 2007-12-05 | 联华电子股份有限公司 | Method for preparing capacitance |
| CN1612348B (en) * | 2003-08-18 | 2010-06-02 | 三星电子株式会社 | Semiconductor device and manufacturing method |
| CN102456751A (en) * | 2010-11-05 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Low cost metal-insulator-metal capacitors |
-
2002
- 2002-03-12 CN CN 02106992 patent/CN1404127A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1612348B (en) * | 2003-08-18 | 2010-06-02 | 三星电子株式会社 | Semiconductor device and manufacturing method |
| CN100353487C (en) * | 2004-05-12 | 2007-12-05 | 联华电子股份有限公司 | Method for preparing capacitance |
| CN102456751A (en) * | 2010-11-05 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Low cost metal-insulator-metal capacitors |
| US8803286B2 (en) | 2010-11-05 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low cost metal-insulator-metal capacitors |
| CN102456751B (en) * | 2010-11-05 | 2015-04-01 | 台湾积体电路制造股份有限公司 | Low cost metal-insulator-metal capacitors |
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