CN1400642A - Method for making metal oxide semiconductor field effect transistor - Google Patents
Method for making metal oxide semiconductor field effect transistor Download PDFInfo
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- CN1400642A CN1400642A CN 01125078 CN01125078A CN1400642A CN 1400642 A CN1400642 A CN 1400642A CN 01125078 CN01125078 CN 01125078 CN 01125078 A CN01125078 A CN 01125078A CN 1400642 A CN1400642 A CN 1400642A
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Abstract
A method of processing a metal oxide semiconductor field effect transistor contains to provide a ground wafer forming a channel in it, to form a gate at the bottom of the channel, to form a gap wall at both sides of the gate and fill in the channel, implanting ions in the ground at the two sides of the gap wall, to quickly heat for the first time to form a source/drain zone and a source/drain extending zone on the ground, to quickly heat the second time to form a metallic silicide layer on the gate and source/drain zone to remove the metal layer. This invented method puts the gate and gap wall in a channel preformed on the ground to reduce the depth of engagement and prevent potential drop between the source and channel resulted by the drain and through drain current effect.
Description
Technical field
The relevant a kind of method of making mos field effect transistor of the present invention is particularly relevant for a kind of method that gate and clearance wall is produced on the mos field effect transistor in the trench.
Background technology
The manufacturing technology of semiconductor integrated circuit (semiconductor integrated circuit) is updated, and when the size of individual elements had been dwindled significantly, the number of elements that is installed on the semiconductor wafer increased in large quantities.In fabrication schedule now, the size of semiconductor element has narrowed down to time field of micron (sub-micron).On highdensity wafer like this, in order to obtain excellent electrical property, each element must suitably be dwindled, to reduce the defective that semiconductor element was taken place of reduced volume.
With reference to shown in Figure 1, the formation method of traditional mos field effect transistor is to form a gate 20 earlier on a ground 10, and this gate 20 comprises a gate pole oxidation layer 22 (gate oxidelayer) at least.With reference to shown in Figure 2, next utilize mode that ion implants processing procedure required N type ion or P type ion to be implanted in the ground of gate both sides to form lightly doped drain (lightly doped drain; LDD) 30 zone.With reference to shown in Figure 3, on the sidewall of gate 20, form clearance wall 40, the material major part of this gap wall 40 is generally an insulation material, such as: silicon nitride etc.The defective of leakage currents takes place in clearance wall 40 main functions for minimizing gate 20.With reference to shown in Figure 4, the mode of utilizing ion to implant implants in the ground 10 processing procedure required N type ion or P type ion to form the zone of source/drain 50.The zone of this source/drain 50 is positioned at the both sides in lightly doped drain 30 zones.With reference to shown in Figure 5, utilize the processing procedure of self-aligned metal silicate (salicide) on gate 20 and source/drain 50 zones, to form layer of metal silicide (silicide) 60, finish the processing procedure that utilizes traditional method to make mos field effect transistor immediately.
After semi-conductive volume-diminished, the volume of each position element of semiconductor also will dwindle thereupon.And when the volume of mos field effect transistor need dwindle, the element at each position of mos field effect transistor also will dwindle thereupon, such as: gate, clearance wall or source/drain etc.When the zone of source/drain dwindled, the degree of depth of source/drain also can be along with dwindling.But in the mos field effect transistor of traditional structure, if the depth of engagement of source/drain is too shallow, then after the processing procedure of follow-up formation metal silicide, the defective of pin type leakage current can take place in the metal oxide semitransistor, and the problem of can replace (tradeoff).If the depth of engagement of source/drain is too dark, then cause drain voltage to cause source electrode and interchannel electrical potential energy to descend and the defective that runs through leakage current easily.Therefore, under the more and more littler trend of the volume of semiconductor element,, then can reduce the quality and the acceptance rate (yield) of semiconductor element, and increase production cost if still use conventional methods the making mos field effect transistor.
Summary of the invention
The purpose of this invention is to provide the little and well behaved mos field effect transistor of a kind of making volume, cause source electrode and interchannel electrical potential energy to descend, run through leakage current, fall into pin type leakage current and transposition to reduce drain voltage, thereby improve the quality and the acceptance rate of semiconductor element.
For achieving the above object, the method for the making mos field effect transistor that provides according to an aspect of the present invention is characterized in, described method comprises at least: a wafer is provided, and described wafer comprises a ground at least; Form a trench in described ground; Form the bottom of a gate in described trench; Form a clearance wall in the both sides of described gate and fill up described trench; Implant an ion in the described ground of described clearance wall both sides; Carry out one first Fast Heating processing procedure in described ground, to form source territory and source elongated area; Form a metal level in described gate, described clearance wall and described regions and source; Carry out one second Fast Heating processing procedure on described gate and described regions and source, to form a metal silicide layer; And remove described metal level.
For achieving the above object, the method for the making mos field effect transistor that provides according to a further aspect of the invention is characterized in, described method comprises at least: a wafer is provided, and described wafer comprises a ground at least; Form a trench in described ground; Form the bottom of a gate in described trench, described gate comprises a gate pole oxidation layer at least; Form a clearance wall in a sidewall of described gate and described gate pole oxidation layer and fill up described trench; Implant an ion in the described ground of described clearance wall both sides; Carry out one first Fast Heating processing procedure in ground, to form source territory and source elongated area; Form a metal level in described gate, described clearance wall and described regions and source; Carry out one second Fast Heating processing procedure on described gate and described regions and source, to form a metal silicide layer; And remove described metal level and carry out the 3rd Fast Heating processing procedure.
Such scheme of the present invention is owing to be to form gate and clearance wall making mos field effect transistor in the trench that utilizes in ground, can avoid mos field effect transistor after the reduced volume to cause drain voltage to cause source electrode and the decline of interchannel electrical potential energy because the depth of engagement of source/drain is too dark or too shallow like this and run through the defective of leakage current, also can avoid the too dark or too shallow defective that causes pin type leakage current and transposition of depth of engagement simultaneously, thereby can improve the quality and the acceptance rate of semiconductor element because of source/drain.
Be clearer understanding purpose of the present invention, characteristics and advantage, below in conjunction with accompanying drawing to of the present invention preferable
Embodiment is elaborated.
Description of drawings
Fig. 1 is the schematic diagram that forms a gate on the wafer ground;
Fig. 2 is the schematic diagram that is formed on lightly doped drain in the ground;
Fig. 3 is the schematic diagram that forms clearance wall on the sidewall of gate;
Fig. 4 is the schematic diagram that forms regions and source in ground;
Fig. 5 is for forming the schematic diagram of a metal silicide layer on gate and regions and source;
Fig. 6 is the schematic diagram that forms a trench in ground;
Fig. 7 is for forming the schematic diagram of a gate in the bottom of trench;
Fig. 8 is the schematic diagram that forms a gap parietal layer and fill up trench on ground and gate;
Fig. 9 is for forming clearance wall and filling up the schematic diagram of trench in the gate side walls;
Figure 10 is the schematic diagram that forms regions and source and source/drain elongated area in ground;
Figure 11 is the schematic diagram that forms a metal level on gate, clearance wall and regions and source; And
Figure 12 is the schematic diagram that forms metal silicide layer on gate and regions and source.
Embodiment
The present invention in the trench that gate and clearance wall is formed at ground with the making mos field effect transistor.With reference to shown in Figure 6, a wafer at first is provided, this wafer comprises a ground 100 at least.Next remove the ground 100 of part, to form a trench 120 on ground 100, the width of this trench 120 and the degree of depth are along with processing procedure is required and different.The mode that removes is most of uses etching method, and ground 100 employed material major parts are a silicon base material.With reference to shown in Figure 7, form a gate 200 in the bottom of trench 120, this gate comprises a gate pole oxidation layer 220 at least.The depth bounds of trench is about 50% to 80% of gate thickness, and the width range of trench is about 0.2 μ m to 0.35 μ m.Along with dwindling of semiconductor element volume, the degree of depth and the width of trench will be more and more littler.The volume of gate 200 dwindles along with dwindling of mos field effect transistor.With reference to shown in Figure 8, next on gate 200 and ground 100, form a gap parietal layer 300, and fill up whole trench 120.Usually adopt the material of megohmite insulant as gap parietal layer 300, such as: silicon nitride etc.
With reference to shown in Figure 9, remove the gap parietal layer 300 of part, form clearance wall 310 in the both sides of gate 200.The function of this gap wall 310 is to prevent that gate 200 from the defective of leakage currents taking place and it is positioned at the both sides of gate 200 and fills up whole trench 120.Usually adopt etched mode to remove the gap parietal layer 300 of part.With reference to shown in Figure 10, next that processing procedure is required N type ion or P type ion are implanted in the ground of clearance wall both sides, to make regions and source 400.The mode of traditional fabrication mos field effect transistor, most of mode of lightly doped drain that adopts is to avoid the defective of mos field effect transistor generation short-channel effect.But after the mos field effect transistor volume-diminished, the lightly doped drain zone also will with dwindle.In the processing procedure of lightly doped drain, though can control the size in lightly doped drain zone, but in follow-up high temperature process, ion in the lightly doped region will be easy to move to other zones by the effect of infiltration and diffusion, and the zone of lightly doped drain is enlarged and the defective of generation short-channel effect.Therefore in the present invention, directly the required ion of implantation process to form regions and source 400.Next impose the processing procedure of one first Fast Heating processing procedure again as tempering (anneal).Temperature via the degree of depth of controlling the ion implantation and processing procedure makes the ion of implanting move to suitable position via the effect of spreading or permeate, with the function in replacement lightly doped drain zone.This zone is commonly referred to the elongated area (source/drain extendedregion) 420 of source/drain.The temperature of this first Fast Heating processing procedure is approximately 950 to 1050 ℃.
With reference to shown in Figure 11, on gate 200, clearance wall 310 and regions and source 400, form a metal level 500.Most of (CVD) method or magnetic control direct current sputter (direct current magnetron sputtering) method deposits this metal level 500 of chemical vapour deposition (CVD) (chemical vapor deposition) of using.Next, wafer sent into carry out the second Fast Heating processing procedure in the reative cell, make the pasc reaction of metal level 500 and contact position, to form metal silicide (silicide) layer 510.The temperature of the second Fast Heating processing procedure is approximately 500 to 700 ℃.The structure of the metal silicide of this moment mainly is the structure of the higher C-49 phase of resistance value.Reference is shown in Figure 12, and the mode of utilizing RCA to clean removes and has neither part nor lot in reaction or reaction back institute metal remained layer 500, and metallic silicon compounds layer 510 is stayed on gate 200 and the regions and source 400.Carry out the 3rd Fast Heating processing procedure at last again, the metal suicide structure of C-49 phase is converted to the structure of the lower C-54 phase of resistance value.The temperature of the 3rd Fast Heating processing procedure is approximately 750 to 850 ℃.The material of this metal level 500 can be titanium, cobalt and platinum etc., uses the titanium material of metal level 500 for this reason usually.
Titanium is the metal material of normal use in the present self-aligned metal silicate processing procedure.Titanium is the good metal material of a kind of oxygen energy-absorbing power (oxygen gettering), under suitable temperature, titanium very easily with the metal oxide semitransistor on drain/source and the silicon on the gate form the very low titanium-silicon compound of a resistivity (titanium silicide) (TiSi because of mutual diffusion
2).
By the made mos field effect transistor of the present invention, can more accurately control the depth of engagement of regions and source, and the error allowed band of the depth of engagement of regions and source is also bigger, therefore can and taking place, drain voltage not cause source electrode and interchannel electrical potential energy to descend and the defective that runs through leakage current owing to the depth of engagement of source/drain is too dark.Adopt method of the present invention can also avoid the conjugation grade of source/drain too shallow and the defective of pin type leakage current and transposition takes place behind follow-up formation self-aligned metal silicate processing procedure.Adopt method of the present invention can dwindle the volume of semiconductor element smoothly, and can not influence its usefulness, therefore can improve the quality and the acceptance rate of semiconductor element.
The above only is preferred embodiment of the present invention, this embodiment only be used for the explanation but not in order to limit claim of the present invention.Still can be changed in the category that does not break away from flesh and blood of the present invention and implemented, these variations should still belong to scope of the present invention.Therefore, scope of the present invention is defined by following claim.
Claims (10)
1. a method of making mos field effect transistor is characterized in that, described method comprises at least:
One wafer is provided, and described wafer comprises a ground at least;
Form a trench in described ground;
Form the bottom of a gate in described trench;
Form a clearance wall in the both sides of described gate and fill up described trench;
Implant an ion in the described ground of described clearance wall both sides;
Carry out one first Fast Heating processing procedure in described ground, to form source territory and source elongated area;
Form a metal level in described gate, described clearance wall and described regions and source;
Carry out one second Fast Heating processing procedure on described gate and described regions and source, to form a metal silicide layer; And
Remove described metal level.
2. the method for claim 1 is characterized in that, the degree of depth of described trench be described gate a thickness 50% to 80%.
3. the method for claim 1 is characterized in that, described ion is a N type ion.
4. the method for claim 1 is characterized in that, the material of described metal level is a titanium.
5. a method of making mos field effect transistor is characterized in that, described method comprises at least:
One wafer is provided, and described wafer comprises a ground at least;
Form a trench in described ground;
Form the bottom of a gate in described trench, described gate comprises a gate pole oxidation layer at least;
Form a clearance wall in a sidewall of described gate and described gate pole oxidation layer and fill up described trench;
Implant an ion in the described ground of described clearance wall both sides;
Carry out one first Fast Heating processing procedure in ground, to form source territory and source elongated area;
Form a metal level in described gate, described clearance wall and described regions and source;
Carry out one second Fast Heating processing procedure on described gate and described regions and source, to form a metal silicide layer; And
Remove described metal level and carry out the 3rd Fast Heating processing procedure.
6. method as claimed in claim 5 is characterized in that, the degree of depth of described trench be described gate thickness 50% to 80%.
7. method as claimed in claim 5 is characterized in that, described ion is a P type ion.
8. method as claimed in claim 5 is characterized in that, the material of described metal level is a cobalt.
9. method as claimed in claim 5 is characterized in that, the material of described metal level is a platinum.
10. method as claimed in claim 9 is characterized in that, the material of described clearance wall is a silicon nitride.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB01125078XA CN1159753C (en) | 2001-08-07 | 2001-08-07 | Method for making metal oxide semiconductor field effect transistor |
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| CNB01125078XA CN1159753C (en) | 2001-08-07 | 2001-08-07 | Method for making metal oxide semiconductor field effect transistor |
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| CN1400642A true CN1400642A (en) | 2003-03-05 |
| CN1159753C CN1159753C (en) | 2004-07-28 |
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| CNB01125078XA Expired - Fee Related CN1159753C (en) | 2001-08-07 | 2001-08-07 | Method for making metal oxide semiconductor field effect transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100452422C (en) * | 2004-04-26 | 2009-01-14 | 台湾积体电路制造股份有限公司 | Reliable semiconductor structure and method for fabricating |
| CN100466199C (en) * | 2006-08-07 | 2009-03-04 | 联华电子股份有限公司 | Method for cleaning residual metal |
-
2001
- 2001-08-07 CN CNB01125078XA patent/CN1159753C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100452422C (en) * | 2004-04-26 | 2009-01-14 | 台湾积体电路制造股份有限公司 | Reliable semiconductor structure and method for fabricating |
| CN100466199C (en) * | 2006-08-07 | 2009-03-04 | 联华电子股份有限公司 | Method for cleaning residual metal |
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| Publication number | Publication date |
|---|---|
| CN1159753C (en) | 2004-07-28 |
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Granted publication date: 20040728 Termination date: 20190807 |