CN1399136A - Clock signal frequency verifying device and method - Google Patents
Clock signal frequency verifying device and method Download PDFInfo
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- CN1399136A CN1399136A CN 02127705 CN02127705A CN1399136A CN 1399136 A CN1399136 A CN 1399136A CN 02127705 CN02127705 CN 02127705 CN 02127705 A CN02127705 A CN 02127705A CN 1399136 A CN1399136 A CN 1399136A
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Abstract
The present invention, clock signal frequency verifying device and method are used in verification process of clock signal source. The device includes one reference clock signal and reset signal producing source, one frequency divider and one comparing detector. The method includes inputting a tested clock signal to the frequency divider; triggering the frequency divider corresponding to a activating reset signal to output a double-level frequency-dividing tested signal; detecting the signal level in a certain time internal; and judging whether the clock signal source is in normal operation state and finding out the period error range of the clock signal to be tested.
Description
Technical field
The present invention relates to a kind of clock signal frequency verifying device and method, finger is applied to clock signal frequency verifying device and the method in the integrated circuit testing procedure especially.
Background technology
In various circuit arrangement now, clock signal be when coordinating each components and parts operation indispensable signal of interest, therefore, in the test and verify program that after a circuit arrangement manufacturing is finished, is carried out, must include the testing authentication action that a clock signal source of clocking is carried out.See also Fig. 1, it carries out the block schematic diagram of the proving installation commonly used of testing authentication action to signal source of clock, it is mainly finished by a frequency divider 11 and a testing circuit 12, because the frequency of signal source of clock 10 (being generally an oscillator or a phase-locked loop) institute's clocking is quite high, therefore essential through frequency divider 11 down conversion process and form one hang down the test signal of switching frequency after, this testing circuit 12 of feed-in just now detects.But whether testing circuit 12 commonly used only has this test signal of detection and has by electronegative potential and switch to noble potential and switch to the potential change of electronegative potential by noble potential, and then judges the whether function of regular event of signal source of clock 10.
Yet, when the operating speed of circuit increases day by day, for the requirement of signal source of clock 10 just no longer just regular event whether, but accuracy that must its frequency of checking.But obviously above-mentioned conventional means also can't verify effectively whether the frequency accuracy of signal source of clock 10 conforms with demand,
Summary of the invention
Fundamental purpose of the present invention is to improve the disappearance of conventional means, so can be simultaneously to signal source of clock whether regular event with and frequency accuracy verify.
The present invention discloses a kind of clock signal frequency verifying method, be applied in the proof procedure of a clock signal source, its method comprises the following steps: the clock signal to be measured that this signal source of clock is exported is inputed to a frequency divider, and this clock signal to be measured has a period 1 T1; The activation of a corresponding reset signal, this frequency divider begin triggering that should clock signal to be measured is moved, and then export measured signal behind the frequency division of a bipotential, behind this frequency division measured signal have one second round T2, and T2/n=T1; To activation that should reset signal, the signal potential of measured signal after a schedule time Ts just detects this frequency division; And measured signal is in one first current potential behind detected this frequency division from the 1st time point to a p-q time point, and when the signal potential of measured signal is in one second current potential behind detected this frequency division on p+1 time point, judge that this signal source of clock is operate as normal and the circular error scope Te that draws this clock signal to be measured.
According to above-mentioned conception, clock signal frequency verifying method of the present invention, p=(T2/ (2Ts)) wherein, q=(T1/Ts), Te=(q+ (1/2)) * Ts/ (n/2).
According to above-mentioned conception, clock signal frequency verifying method of the present invention, wherein also comprise the following steps: when continue to detect 2p-q time point and 2p+1 time point, a 3p-q time point and 3p+1 time point ... and the signal potential of measured signal behind this frequency division on mp-q time point and mp+1 the time point, and this signal source of clock is when all being judged as operate as normal, the circular error scope Te=of this clock signal to be measured (q+ (1/2)) * Ts/ (m*n/2).
According to above-mentioned conception, clock signal frequency verifying method of the present invention, wherein should schedule time Ts be determined by the rising edge of a reference clock signal, and the variation of this reset signal is along aliging with the negative edge of this reference clock signal, as for this circular error scope Te=(q+ (1/2)) * Ts/ (m*n/2).
According to above-mentioned conception, clock signal frequency verifying method of the present invention, non-one first current potential that all is in of measured signal behind detected this frequency division from the 1st time point to a p-q time point wherein, or the signal potential of measured signal is non-behind detected this frequency division on p+1 time point when being in one second current potential, judges that then this signal source of clock is a non-normal working.
The present invention also discloses a kind of clock signal frequency verifying device, be applied to verify the accuracy of a clock signal source, it cooperates a reference clock signal and reset signal generation source to move, reference clock signal and reset signal generation source produce a reference clock signal and a reset signal, and this reference clock signal has a predetermined period Ts; And this demo plant comprises: a frequency divider, be electrically connected on this signal source of clock and this reference clock signal and reset signal and produce the source, it receives the clock signal to be measured that this signal source of clock is exported, and to activation that should reset signal, and begin triggering that should clock signal to be measured and move, and then export measured signal behind the frequency division of a bipotential, wherein this clock signal to be measured has a period 1 T1, behind this frequency division measured signal have one second round T2, and T2/n=T1; An and detecting device relatively, be electrically connected on this frequency divider and this reference clock signal and reset signal and produce the source, it is to the activation that should reset signal and the triggering of this reference clock signal, the signal potential of measured signal after this predetermined period Ts just detects this frequency division, and measured signal is in one first current potential behind detected this frequency division from the 1st time point to a p-q time point, and when the signal potential of measured signal is in one second current potential behind detected this frequency division on p+1 time point, export the circular error scope Te that a signal working properly also can draw this clock signal to be measured.
According to above-mentioned conception, clock signal frequency verifying device of the present invention, p=(T2/ (2Ts)) wherein, q=(T1/Ts), Te=(q+ (1/2)) * Ts/ (n/2).
According to above-mentioned conception, clock signal frequency verifying device of the present invention, wherein when detect 2p-q time point and 2p+1 time point, a 3p-q time point and 3p+1 time point ... and behind this frequency division on mp-q time point and mp+1 the time point during signal potential of measured signal, this represents circular error scope Te=(q+ (1/2)) the * Ts/ (m*n/2) of this clock signal to be measured when relatively detecting device continues output one signal working properly.
According to above-mentioned conception, clock signal frequency verifying device of the present invention, wherein should put rising edge detection time, and the variation of this reset signal is along aliging with the negative edge of this reference clock signal, as for this circular error scope Te=(q+ (1/2)) * Ts/ (m*n/2) into this reference clock signal.
According to above-mentioned conception, clock signal frequency verifying device of the present invention, wherein this frequency divider, this comparison detecting device and this signal source of clock are integrated on the same chip.
According to above-mentioned conception, clock signal frequency verifying device of the present invention, non-one first current potential that all is in of measured signal behind detected this frequency division from the 1st time point to a p-q time point wherein, or the signal potential of measured signal is non-behind detected this frequency division on p+1 time point when being in one second current potential, exports a rub-out signal.
According to above-mentioned conception, clock signal frequency verifying device of the present invention wherein when this rub-out signal of output, represents the circular error scope Te of this clock signal to be measured must be greater than (1/2) * Ts/ (n/2).
Description of drawings
The present invention must be by following accompanying drawing and detailed description, in order to do a more deep understanding:
Fig. 1 is a block schematic diagram of signal source of clock being carried out the proving installation commonly used of testing authentication action.
The preferred embodiment block schematic diagram that Fig. 2 for the present invention develops for clock signal frequency verifying device.
Fig. 3 is for to enumerate the coherent signal waveform synoptic diagram that an example describes to above-mentioned technological means.
Each included in the accompanying drawing of the present invention components and parts are as follows:
12--testing circuit behind the 10--signal source of clock 11--frequency divider
20--signal source of clock 21--frequency divider 22--is detecting device relatively
23--reference clock signal and reset signal produce the source
Embodiment
See also Fig. 2, the present invention is for developing the preferred embodiment block schematic diagram that for clock signal frequency verifying device, it is mainly used in the accuracy of checking signal source of clock 20, this device mainly includes relatively detecting device 22 of a frequency divider 21 and, this frequency divider 21 receives the clock signal to be measured that this signal source of clock 20 is exported, and the activation of a corresponding reset signal, and begin triggering that should clock signal to be measured and move, and then export measured signal behind the frequency division of a bipotential, wherein this clock signal to be measured has a period 1 T1, behind this frequency division measured signal have one second round T2, and T2/n=T1 (n is the multiple of frequency division).As for this relatively 22 of detecting devices to the activation that should reset signal and the triggering of this reference clock signal, the signal potential of measured signal after a predetermined period Ts just detects this frequency division, and measured signal is in one first current potential behind detected this frequency division from the 1st time point to a p-q time point, and export a signal working properly when the signal potential of measured signal is in one second current potential behind detected this frequency division on p+1 time point, if detected current potential is not inconsistent above-mentioned condition, then export a rub-out signal, because measured signal has rising edge and a negative edge can be for judging behind this frequency division in one-period, therefore p can be defined as (T2/ (2Ts)), then is defined as T1/Ts as for q.Can be sent by a reference clock signal and reset signal generation source 23 as for above-mentioned reference clock signal and reset signal.
See also Fig. 3 again, it is for to enumerate the coherent signal waveform synoptic diagram that an example describes to above-mentioned technological means, wherein the predetermined period Ts of reference clock signal (REFCLK) is 20 nanoseconds (ns), and the variation of reset signal (RESET#) is along aliging with a negative edge of this reference clock signal.And because clock signal to be measured (CLK) that this signal source of clock 20 is exported and reference clock signal and asynchronous, therefore in the A time range after reset signal (RESET#) is changed to noble potential, clock signal to be measured (CLK) all might change noble potential into by electronegative potential, (this example was 40 nanoseconds and the length of this A time range is just for the period 1 T1 of this clock signal to be measured (CLK), just become 2 frequencys multiplication relation with 20 nanoseconds of predetermined period, but in fact might not be necessary for 2 frequencys multiplication relation, 1 frequency multiplication relation also can, it is relevant with allowed frequency error).In addition, this activation that relatively 22 pairs of detecting devices should reset signal and the triggering of this reference clock signal rising edge, the signal potential of measured signal after this predetermined period Ts (20 nanosecond) just detects this frequency division, and put count value (STROBE NO) its detection time as shown in the figure.Right this routine frequency divider 21 is one 9 a frequency divider (promptly divided by 512), and T2 second round of measured signal (TESTCLK) just equals 40*512 nanosecond behind the feasible frequency division of being exported.Therefore, under perfect condition, its rising edge first time after reset signal activates should take place in measured signal behind the frequency division (TESTCLK) in the B time range, that is to say, should be electronegative potential all smaller or equal to putting detected signal potential the 510th time detection time, and all should be noble potential more than or equal to putting detected signal potential the 513rd time detection time.As in B time range (40 nanosecond),, do not list consideration in because two current potentials are all possible.In addition, under perfect condition, its negative edge first time after reset signal activates should take place in measured signal behind the frequency division (TESTCLK) in C time range (40 nanosecond), that is to say, should be noble potential all smaller or equal to putting detected signal potential the 1022nd time detection time, and all should be electronegative potential more than or equal to putting detected signal potential the 1025th time detection time.As in C time range (40 nanosecond), because two current potentials are all possible, so also do not list consideration in.
In sum, the frequency of the clock signal of being exported when this signal source of clock 20 in this example to be measured (CLK) is 25Mhz and keep necessarily in the ideal, and above-mentioned test result must be set up and make comparison detecting device 22 continue output one signals working properly.Keep one regularly but the frequency F of the clock signal of being exported when this signal source of clock 20 to be measured (CLK) is slightly larger than 25Mhz, the variation of measured signal behind the frequency division (TESTCLK) is along moving to the left of oscillogram.Consider an extremity, when measured signal behind the frequency division (TESTCLK) moves to Far Left (as D arrow in figure shown in along the position by rightmost in producing m variation edge and its variation, totally 50 nanoseconds), so just, can extrapolate its cycle should be 40-50/ (m*512/2) nanosecond, and frequency F then is its inverse.Thus, as long as the actual frequency of clock signal to be measured (CLK) is slightly larger than above-mentioned frequency F, relatively detecting device 22 in its m variation along the time will inevitably export a rub-out signal.Consider another extremity again, when measured signal behind the frequency division (TESTCLK) moves to Far Left (as E arrow in figure shown in along the position by the left side in producing m variation edge and its variation, totally 10 nanoseconds) time, so just, can extrapolate its cycle should be 40-10/ (m*512/2) nanosecond, and frequency F then is its inverse.Thus, as long as the actual frequency of clock signal to be measured (CLK) is slightly less than above-mentioned frequency F, relatively detecting device 22 in its m change along the time certainty still export a signal working properly.In the same manner, a frequency be slightly less than 25Mhz but still keep certain clock signal to be measured (CLK), its analytic process and above-mentioned there is no too different, only for changing along position moving direction opposite (shown in F arrow and G arrow among the figure).
Conclude according to above-mentioned analysis and to draw following formula:
Absolute incorrect frequency: 1/ (T1 ± (q+ (1/2)) * Ts/ (m*n/2))
Frequency range is absolutely correct: 1/ (T1 ± (1/2) * Ts/ (m*n/2))
And when being example and m=4, its absolute incorrect frequency is 25MHz ± 1222ppm with above-mentioned data (T1=40 nanosecond, Ts=20 nanosecond and q=T1/Ts=2 as for n=512), and its frequency that is absolutely correct is 25MHz ± 244ppm, wherein ppm be 1,000,000/.Meaning promptly, when detecting device 22 relatively through 4 variations of measured signal (TESTCLK) behind the frequency division along after still during the output services normal signal, the frequency F that just can reason out this clock signal to be measured (CLK) is at least in the scope of 25MHz ± 1222ppm.
And in some cases, it is so high that the deviser does not need for the degree of accuracy of clock signal frequency, therefore can ignore more detection time of point, and it is wideer that meaning allows that promptly measured signal (TESTCLK) behind the frequency division changes the position on edge.With above-mentioned is example, if front and back respectively relax one detection time point, then its incorrect frequency can be amplified to 25MHz ± 1706ppm (formula becomes 1/ (T1 ± (1+q+ (1/2)) * Ts/ (m*n/2))) by 25MHz ± 1222ppm.
And, can there be dual mode to realize this comparison detecting device 22 based on the relativeness of reset signal, reference clock signal and clock signal to be measured.First kind of mode, this comparison detecting device 22 described in grammer with buffer-transistor stratum (RTL), and use the logic synthetics to convert side circuit to, the advantage of the method is that this side circuit is embedded in the to-be-measured integrated circuit, makes to-be-measured integrated circuit the oneself to detect mistake.And be the degree of accuracy that can improve measured frequency error, can increase observing the change number on edge of measured signal (TESTCLK) behind this frequency division, m=4 in this example, also can increase into m=5,6 ..8 etc., but in the degree of accuracy that promotes measured frequency error, also increase complexity of hardware relatively, and cost is also increased thereupon.
As for the second way, it directly replaces this comparison detecting device 22 with tester table, this mode needs to prepare in advance the test vector (test vector) of measured signal (TESTCLK) behind the correct frequency division, and vector value is the last ideal value of measured signal (TESTCLK) behind this frequency division of each of some detection time.Thus, only need measured signal (TESTCLK) behind the actual frequency division of frequency divider 21 outputs is delivered to tester table, and with test vector with the reference clock signal be the action benchmark deliver to tester table, come the similarities and differences between measured signal and ideal value behind the actual frequency division of comparison frequency divider 21 output by tester table, and then reach the purpose of frequency verifying.
Therefore, the present invention can verify effectively more whether the frequency accuracy of signal source of clock conforms with demand, and then improve the disappearance of conventional means, and then reach development fundamental purpose of the present invention except measuring signal source of clock whether the regular event.
Claims (10)
1. a clock signal frequency verifying method is applied to it is characterized in that in the proof procedure of a clock signal source that this method comprises the following steps:
The clock signal to be measured that this signal source of clock is exported inputs to a frequency divider, and this clock signal to be measured has a period 1 T1;
The activation of a corresponding reset signal, this frequency divider begin triggering that should clock signal to be measured is moved, and then export measured signal behind the frequency division of a bipotential, behind this frequency division measured signal have one second round T2, and T2/n=T1;
To activation that should reset signal, the signal potential of measured signal after a schedule time Ts detects this frequency division; And
Measured signal is in one first current potential behind detected this frequency division from the 1st time point to a p-q time point, and when the signal potential of measured signal is in one second current potential behind detected this frequency division on p+1 time point, judge that this signal source of clock is operate as normal and the circular error scope Te that draws this clock signal to be measured.
2. clock signal frequency verifying method as claimed in claim 1 is characterized in that, p=(T2/ (2Ts)), q=(T1/Ts), Te=(q+ (1/2)) * Ts/ (n/2).
3. clock signal frequency verifying method as claimed in claim 1 is characterized in that, also comprises the following steps:
The signal potential of measured signal behind this frequency division that continue to detect on 2p-q time point and 2p+1 time point, a 3p-q time point and 3p+1 time point and mp-q time point and mp+1 the time point, and this signal source of clock is when all being judged as operate as normal, the circular error scope Te=of this clock signal to be measured (q+ (1/2)) * Ts/ (m*n/2).
4. clock signal frequency verifying method as claimed in claim 3, it is characterized in that, this schedule time, Ts was determined by the rising edge of a reference clock signal, and the variation of this reset signal is along aliging with the negative edge of this reference clock signal, as for this circular error scope Te=(q+ (1/2)) * Ts/ (m*n/2).
5. clock signal frequency verifying method as claimed in claim 1, it is characterized in that, non-this first current potential that all is in of measured signal behind detected this frequency division from the 1st time point to a p-q time point, or the signal potential of measured signal is non-behind detected this frequency division on p+1 time point when being in this second current potential, judges that then this signal source of clock is a non-normal working.
6. clock signal frequency verifying device, be applied to verify the accuracy of a clock signal source, it cooperates a reference clock signal and reset signal generation source to move, reference clock signal and reset signal generation source produce a reference clock signal and a reset signal, and this reference clock signal has a predetermined period Ts; It is characterized in that this demo plant comprises:
One frequency divider, be electrically connected on this signal source of clock and this reference clock signal and reset signal and produce the source, it receives the clock signal to be measured that this signal source of clock is exported, and to activation that should reset signal, and begin triggering that should clock signal to be measured and move, and then export measured signal behind the frequency division of a bipotential, wherein this clock signal to be measured has a period 1 T1, behind this frequency division measured signal have one second round T2, and T2/n=T1; And
One compares detecting device, be electrically connected on this frequency divider and this reference clock signal and reset signal and produce the source, it is to the activation that should reset signal and the triggering of this reference clock signal, the signal potential of measured signal after this predetermined period Ts just detects this frequency division, and measured signal is in one first current potential behind detected this frequency division from the 1st time point to a p-q time point, and when the signal potential of measured signal is in one second current potential behind detected this frequency division on p+1 time point, export the circular error scope Te that a signal working properly also can draw this clock signal to be measured.
7. clock signal frequency verifying device as claimed in claim 6 is characterized in that, p=(T2/ (2Ts)), q=(T1/Ts), Te=(q+ (1/2)) * Ts/ (n/2).
8. clock signal frequency verifying device as claimed in claim 7, it is characterized in that, when detect 2p-q time point and 2p+1 time point, a 3p-q time point and 3p+1 time point ... and behind this frequency division on mp-q time point and mp+1 the time point during signal potential of measured signal, this represents circular error scope Te=(q+ (1/2)) the * Ts/ (m*n/2) of this clock signal to be measured when relatively detecting device continues output one signal working properly.
9. clock signal frequency verifying device as claimed in claim 8, it is characterized in that, put this detection time and be the rising edge of this reference clock signal, and the variation of this reset signal is along aliging with the negative edge of this reference clock signal, as for this circular error scope Te=(q+ (1/2)) * Ts/ (m*n/2).
10. clock signal frequency verifying device as claimed in claim 6 is characterized in that, this frequency divider, this comparison detecting device and this signal source of clock are integrated on the same chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021277052A CN1171090C (en) | 2002-08-08 | 2002-08-08 | Clock signal frequency verifying device and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021277052A CN1171090C (en) | 2002-08-08 | 2002-08-08 | Clock signal frequency verifying device and method |
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| CN1399136A true CN1399136A (en) | 2003-02-26 |
| CN1171090C CN1171090C (en) | 2004-10-13 |
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| CNB021277052A Expired - Lifetime CN1171090C (en) | 2002-08-08 | 2002-08-08 | Clock signal frequency verifying device and method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100362353C (en) * | 2003-12-24 | 2008-01-16 | 华为技术有限公司 | Clock signal amplitude detecting method and circuit |
| CN102692563A (en) * | 2012-05-18 | 2012-09-26 | 大唐微电子技术有限公司 | Clock frequency detector |
| CN105182067A (en) * | 2015-09-30 | 2015-12-23 | 上海大学 | SOC frequency testing method |
| CN106160883A (en) * | 2015-03-27 | 2016-11-23 | 江苏艾科半导体有限公司 | A kind of RF transceiver Auto-Test System |
| CN106788420A (en) * | 2016-11-30 | 2017-05-31 | 上海顺久电子科技有限公司 | A kind of signal frequency detection method, device and signal frequency controller |
| CN112448717A (en) * | 2019-08-27 | 2021-03-05 | 西门子(深圳)磁共振有限公司 | Clock generation device and method for magnetic resonance wireless coil and wireless coil |
-
2002
- 2002-08-08 CN CNB021277052A patent/CN1171090C/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100362353C (en) * | 2003-12-24 | 2008-01-16 | 华为技术有限公司 | Clock signal amplitude detecting method and circuit |
| CN102692563A (en) * | 2012-05-18 | 2012-09-26 | 大唐微电子技术有限公司 | Clock frequency detector |
| CN102692563B (en) * | 2012-05-18 | 2015-06-17 | 大唐微电子技术有限公司 | Clock frequency detector |
| CN106160883A (en) * | 2015-03-27 | 2016-11-23 | 江苏艾科半导体有限公司 | A kind of RF transceiver Auto-Test System |
| CN105182067A (en) * | 2015-09-30 | 2015-12-23 | 上海大学 | SOC frequency testing method |
| CN105182067B (en) * | 2015-09-30 | 2018-03-06 | 上海大学 | SOC frequency test method |
| CN106788420A (en) * | 2016-11-30 | 2017-05-31 | 上海顺久电子科技有限公司 | A kind of signal frequency detection method, device and signal frequency controller |
| CN106788420B (en) * | 2016-11-30 | 2020-09-22 | 上海顺久电子科技有限公司 | Signal frequency detection method and device and signal frequency controller |
| CN112448717A (en) * | 2019-08-27 | 2021-03-05 | 西门子(深圳)磁共振有限公司 | Clock generation device and method for magnetic resonance wireless coil and wireless coil |
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| Publication number | Publication date |
|---|---|
| CN1171090C (en) | 2004-10-13 |
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