CN1399136A - Clock signal frequency verification device and method - Google Patents

Abstract

The invention relates to a clock signal frequency verification device and a method, which are used for the verification process of a clock signal source. The method comprises the following steps: inputting a clock signal to be measured to the frequency divider; in response to activation of a reset signal, the frequency divider starts to act in response to the triggering of the clock signal to be detected and outputs a double-potential frequency-divided signal to be detected; the comparison detector detects the signal potential of the frequency-divided signal to be detected every a preset time Ts corresponding to the activation of the reference clock signal and the reset signal sent by the reset signal generating source; and when the detected signal to be detected after frequency division from the 1 st time point to the p-q time points is at a first potential and the detected signal potential of the signal to be detected after frequency division at the p +1 th time point is at a second potential, judging that the clock signal source works normally and obtaining a period error range Te of the clock signal to be detected.

Description

Clock signal frequency verification device and method

technical field

The invention relates to a clock signal frequency verification device and method, in particular to a clock signal frequency verification device and method used in the integrated circuit testing process.

Background technique

In today's various circuit devices, the clock signal is an important signal that is indispensable for coordinating the operation of various components. Therefore, in a test and verification procedure performed after a circuit device is manufactured, it must include the generation of the clock. A test verification action performed by a clock signal source of the signal. Please refer to FIG. 1 , it is a schematic block diagram of a common test device for performing a test verification action on a clock signal source, which is mainly completed by a frequency divider 11 and a detection circuit 12, because the clock signal source 10 (usually an oscillator or The frequency of the clock signal generated by a phase-locked loop) is quite high, so it must be processed by the frequency divider 11 to form a test signal with a low switching frequency before being fed into the detection circuit 12 for detection. However, the commonly used detection circuit 12 only has the function of detecting whether the test signal has a potential change from low potential to high potential and from high potential to low potential, so as to determine whether the clock signal source 10 is operating normally.

However, when the operation speed of the circuit increases day by day, the requirement for the clock signal source 10 is no longer just normal operation or not, but the accuracy of its frequency must be verified. However, it is obvious that the above-mentioned common means cannot effectively verify whether the frequency accuracy of the clock signal source 10 meets the requirements,

Contents of the invention

The main purpose of the present invention is to improve the lack of common means, and to simultaneously verify whether the clock signal source operates normally and its frequency accuracy.

The invention discloses a clock signal frequency verification method, which is applied in the verification process of a clock signal source. The method comprises the following steps: input a clock signal to be tested outputted by the clock signal source into a frequency divider, and the clock signal to be tested The test clock signal has a first period T1; corresponding to the activation of a reset signal, the frequency divider starts to act in response to the trigger of the clock signal to be tested, and then outputs a double-potential frequency-divided signal to be tested. The signal to be tested has a second period T2, and T2/n=T1; corresponding to the activation of the reset signal, the signal potential of the signal to be tested after the frequency division is detected every predetermined time Ts; and when starting from the first From the time point to the p-qth time point, the frequency-divided signal to be measured is at a first potential, and the signal potential of the frequency-divided signal to be measured at the p+1th time point is detected When it is at a second potential, it is judged that the clock signal source is working normally and the period error range Te of the clock signal under test is obtained.

According to above-mentioned design, clock signal frequency verification method of the present invention, wherein p=(T2/(2Ts)), q=(T1/Ts), Te=(q+(1/2))*Ts/(n/2) .

According to the above idea, the clock signal frequency verification method of the present invention also includes the following steps: when continuously detecting the 2p-q time point and the 2p+1 time point, the 3p-q time point and the 3p+1 time point time point, ... and the signal potential of the frequency-divided signal to be measured at the mp-q time point and the mp+1 time point, and when the clock signal source is judged to be working normally, the The periodic error range Te=(q+(1/2))*Ts/(m*n/2) of the clock signal to be tested.

According to the above idea, the clock signal frequency verification method of the present invention, wherein the predetermined time Ts is determined by the rising edge of a reference clock signal, and the change edge of the reset signal is aligned with the falling edge of the reference clock signal, as for the period Error range Te=(q+(1/2))*Ts/(m*n/2).

According to the above idea, in the method for verifying the clock signal frequency of the present invention, when the frequency-divided signals detected from the first time point to the p-q time point are not all at a first potential, or at the first When the signal potential of the frequency-divided signal to be detected at p+1 time points is not at a second potential, it is determined that the clock signal source is not working normally.

The present invention also discloses a clock signal frequency verifying device, which is used to verify the accuracy of a clock signal source. clock signal and a reset signal, and the reference clock signal has a predetermined period Ts; and the verification device includes: a frequency divider, electrically connected to the clock signal source and the reference clock signal and reset signal generation source, which Receive a clock signal to be tested outputted by the clock signal source, and corresponding to the activation of the reset signal, start to act in response to the triggering of the clock signal to be tested, and then output a double-potential frequency-divided signal to be tested, wherein the The clock signal to be tested has a first period T1, the frequency-divided signal to be tested has a second period T2, and T2/n=T1; and a comparison detector, electrically connected to the frequency divider and the reference clock signal and the reset signal generation source, which corresponds to the activation of the reset signal and the triggering of the reference clock signal, detects the signal potential of the signal to be tested after frequency division every predetermined period Ts, and when starting from the first time point The frequency-divided signal to be detected at the p-qth time point is at a first potential, and the signal potential of the frequency-divided signal to be detected at the p+1th time point is at a At the second potential, a normal working signal is output and the cycle error range Te of the clock signal to be tested can be obtained.

According to the above design, the clock signal frequency verification device of the present invention, wherein p=(T2/(2Ts)), q=(T1/Ts), Te=(q+(1/2))*Ts/(n/2) .

According to the above idea, the clock signal frequency verification device of the present invention, when detecting the 2p-q time point and the 2p+1 time point, the 3p-q time point and the 3p+1 time point, .. .And when the signal potential of the frequency-divided signal to be measured at the mp-q time point and the mp+1 time point, when the comparison detector continues to output a normal working signal, it represents the clock signal to be measured Periodic error range Te=(q+(1/2))*Ts/(m*n/2).

According to the above idea, in the clock signal frequency verifying device of the present invention, wherein the detection time point is the rising edge of the reference clock signal, and the change edge of the reset signal is aligned with the falling edge of the reference clock signal, as for the period error range Te=(q+(1/2))*Ts/(m*n/2).

According to the idea above, in the clock signal frequency verification device of the present invention, the frequency divider, the comparison detector and the clock signal source are integrated on the same chip.

According to the above idea, in the clock signal frequency verification device of the present invention, when the frequency-divided signals detected from the first time point to the p-q time point are not all at a first potential, or at the first When the signal potential of the frequency-divided signal to be detected at p+1 time points is not at a second potential, an error signal is output.

According to the above idea, the clock signal frequency verification device of the present invention, when outputting the error signal, means that the cycle error range Te of the clock signal to be tested must be greater than (1/2)*Ts/(n/2).

Description of drawings

The present invention can gain a deeper understanding by the following drawings and detailed description:

FIG. 1 is a schematic block diagram of a common test device for performing test and verification actions on a clock signal source.

FIG. 2 is a schematic block diagram of a preferred embodiment of the clock signal frequency verification device developed by the present invention.

FIG. 3 is a schematic diagram of related signal waveforms illustrating an example of the above-mentioned technical means.

Each component included in the accompanying drawings of the present invention is as follows:

10--Clock signal source 11--After the frequency divider 12--Detection circuit

20--Clock signal source 21--Frequency divider 22--Comparison detector

23--Reference clock signal and reset signal generation source

Detailed ways

Please refer to FIG. 2 , the present invention is a schematic block diagram of a preferred embodiment of a clock signal frequency verification device, which is mainly used to verify the accuracy of a clock signal source 20, and the device mainly includes a frequency divider 21 and a The comparison detector 22, the frequency divider 21 receives a clock signal to be tested outputted by the clock signal source 20, and corresponds to the activation of a reset signal, and starts to act in response to the trigger of the clock signal to be tested, and then outputs a pair of The signal to be measured after the frequency division of the potential, wherein the clock signal to be measured has a first period T1, the signal to be measured after the frequency division has a second period T2, and T2/n=T1 (n is a multiple of frequency division) . As for the comparison detector 22, corresponding to the activation of the reset signal and the triggering of the reference clock signal, every predetermined cycle Ts detects the signal potential of the signal to be tested after frequency division, and when from the first time point to The frequency-divided signal to be detected at the p-qth time point is at a first potential, and the signal potential of the frequency-divided signal to be detected at the p+1th time point is at a first potential Output a normal working signal at two potentials, if the detected potential does not meet the above conditions, then output an error signal, because the signal to be tested after frequency division has a rising edge and a falling edge in a period for judgment, so p It can be defined as (T2/(2Ts)), and q is defined as T1/Ts. As for the reference clock signal and reset signal mentioned above, a reference clock signal and reset signal generation source 23 can be sent out.

Please refer to FIG. 3 again, which is a schematic diagram of relevant signal waveforms illustrating an example of the above-mentioned technical means, wherein the predetermined period Ts of the reference clock signal (REFCLK) is 20 nanoseconds (ns), and the reset signal (RESET# ) is aligned with a falling edge of the reference clock signal. Since the clock signal to be tested (CLK) output by the clock signal source 20 is not synchronized with the reference clock signal, the clock signal to be tested (CLK) is not synchronized within the time range A after the reset signal (RESET#) changes to high ) may change from a low potential to a high potential, and the length of the time range of A is the first period T1 of the clock signal (CLK) to be tested (40 nanoseconds in this example, which is exactly the same as the predetermined period of 20 nanoseconds) 2 times the frequency relationship, but in fact it does not necessarily have to be 2 times the frequency relationship, 1 times the frequency relationship is also possible, which is related to the frequency error that can be tolerated). In addition, corresponding to the activation of the reset signal and the triggering of the rising edge of the reference clock signal, the comparison detector 22 detects the signal potential of the frequency-divided signal to be measured every predetermined period Ts (20 nanoseconds), and its The detection time point count value (STROBE NO) is shown in the figure. However, the frequency divider 21 in this example is a 9-bit frequency divider (that is, divided by 512), so that the second period T2 of the output signal to be tested (TESTCLK) after frequency division is equal to 40*512 nanoseconds. Therefore, in an ideal state, the signal to be tested after frequency division (TESTCLK) should have its first rising edge after the activation of the reset signal within the B time range, that is, at the detection time less than or equal to the 510th time The signal potentials detected at all points should be low potentials, and the signal potentials detected at the detection time point greater than or equal to the 513th time should be high potentials. As for the B time range (40 nanoseconds), since both potentials are possible, they are not taken into consideration. In addition, in an ideal state, the signal to be tested (TESTCLK) after frequency division should have its first falling edge after the activation of the reset signal within the C time range (40 nanoseconds), that is, at less than or equal to the first falling edge The signal potentials detected at the 1022th detection time point should all be high potentials, and the signal potentials detected at the 1025th detection time point or greater should be low potentials. As for the C time range (40 nanoseconds), since both potentials are possible, they are not considered.

To sum up, when the frequency of the clock signal (CLK) to be tested output by the clock signal source 20 in this example is ideally 25Mhz and maintained constant, the above test result must be established and the comparison detector 22 will continue to output a working normal signal. But when the frequency F of the clock signal to be tested (CLK) output by the clock signal source 20 is slightly greater than 25Mhz but still remains constant, the change edge of the signal to be tested (TESTCLK) after frequency division will move to the left of the waveform diagram. Consider an extreme state, when the signal to be tested (TESTCLK) generates m change edges after frequency division and its change edge position moves from the rightmost to the leftmost (as shown by the D arrow in the figure, a total of 50 nanoseconds), so It can be calculated that its period should be 40-50/(m*512/2) nanoseconds, and the frequency F is its reciprocal. In this way, as long as the actual frequency of the clock signal (CLK) to be tested is slightly greater than the above-mentioned frequency F, the comparison detector 22 will inevitably output an error signal at its mth change edge. Consider another extreme state, when the signal to be tested (TESTCLK) after frequency division generates m change edges and its change edge position moves from the left to the leftmost (as shown by the E arrow in the figure, a total of 10 nanoseconds) , so it can be deduced that its period should be 40-10/(m*512/2) nanoseconds, and the frequency F is its reciprocal. In this way, as long as the actual frequency of the clock signal (CLK) to be tested is slightly lower than the above-mentioned frequency F, the comparison detector 22 must still output a normal working signal at its mth change edge. Similarly, for a clock signal to be tested (CLK) whose frequency is slightly less than 25Mhz but still maintains a certain value, the analysis process is not much different from the above, except that the change moves in the opposite direction along the position (the F arrow in the figure and the G arrows).

Based on the above analysis, the following formula can be obtained:

Absolute error frequency: 1/(T1±(q+(1/2))*Ts/(m*n/2))

Absolutely correct frequency range: 1/(T1±(1/2)*Ts/(m*n/2))

And taking the above data (T1=40 nanoseconds, Ts=20 nanoseconds, and q=T1/Ts=2 to n=512) as an example and when m=4, its absolute error frequency is 25MHz±1222ppm, and its absolute The correct frequency is 25MHz±244ppm, where ppm is one millionth. That is, when the comparison detector 22 still outputs a normal working signal after the 4 changing edges of the signal to be tested (TESTCLK) after frequency division, it can be deduced that the frequency F of the clock signal to be tested (CLK) is at least 25MHz In the range of ±1222ppm.

In some cases, the designer does not need the high accuracy of the clock signal frequency, so more detection time points can be ignored, which means that the position of the change edge of the signal to be tested (TESTCLK) after frequency division is allowed to be wider. Taking the above as an example, if one detection time point is relaxed before and after, the error frequency can be amplified from 25MHz±1222ppm to 25MHz±1706ppm (the formula becomes 1/(T1±(1+q+(1/2))*Ts/( m*n/2))).

Based on the relative relationship between the reset signal, the reference clock signal and the clock signal to be tested, there are two ways to implement the comparison detector 22 . In the first way, the comparison detector 22 is described in register-transistor-level (RTL) syntax and converted into an actual circuit using a logic synthesis tool. The advantage of this method is that the actual circuit is embedded in the integrated circuit to be tested , so that the integrated circuit under test can detect errors by itself. And in order to improve the accuracy of the frequency error measured, the number of changing edges of the signal to be tested (TESTCLK) after observing the frequency division can be observed to increase, in this example m=4, also can be increased to m=5, 6, ..8, etc., but while improving the accuracy of the measured frequency error, the complexity of the hardware is relatively increased, and the cost is also increased accordingly.

As for the second method, it directly replaces the comparison detector 22 with a test machine. This method needs to prepare in advance the correct test vector (test vector) of the signal to be tested (TESTCLK) after frequency division, and the vector value is each The ideal value of the signal to be tested (TESTCLK) after the frequency division at the detection time point. In this way, it is only necessary to send the actual frequency-divided signal (TESTCLK) to be tested (TESTCLK) output by the frequency divider 21 to the test machine, and send the test vector to the test machine with the reference clock signal as the action reference, and the test machine The platform compares the similarities and differences between the actual frequency-divided signal to be tested output by the frequency divider 21 and the ideal value, and then achieves the purpose of frequency verification.

Therefore, in addition to detecting whether the clock signal source is operating normally, the present invention can also effectively verify whether the frequency accuracy of the clock signal source meets the requirements, thereby improving the lack of common means, and achieving the main purpose of the present invention.

Claims (10)

1. a clock signal frequency verifying method is applied to it is characterized in that in the proof procedure of a clock signal source that this method comprises the following steps:

The clock signal to be measured that this signal source of clock is exported inputs to a frequency divider, and this clock signal to be measured has a period 1 T1;

The activation of a corresponding reset signal, this frequency divider begin triggering that should clock signal to be measured is moved, and then export measured signal behind the frequency division of a bipotential, behind this frequency division measured signal have one second round T2, and T2/n=T1;

To activation that should reset signal, the signal potential of measured signal after a schedule time Ts detects this frequency division; And

Measured signal is in one first current potential behind detected this frequency division from the 1st time point to a p-q time point, and when the signal potential of measured signal is in one second current potential behind detected this frequency division on p+1 time point, judge that this signal source of clock is operate as normal and the circular error scope Te that draws this clock signal to be measured.

2. clock signal frequency verifying method as claimed in claim 1 is characterized in that, p=(T2/ (2Ts)), q=(T1/Ts), Te=(q+ (1/2)) * Ts/ (n/2).

3. clock signal frequency verifying method as claimed in claim 1 is characterized in that, also comprises the following steps:

The signal potential of measured signal behind this frequency division that continue to detect on 2p-q time point and 2p+1 time point, a 3p-q time point and 3p+1 time point and mp-q time point and mp+1 the time point, and this signal source of clock is when all being judged as operate as normal, the circular error scope Te=of this clock signal to be measured (q+ (1/2)) * Ts/ (m*n/2).

4. clock signal frequency verifying method as claimed in claim 3, it is characterized in that, this schedule time, Ts was determined by the rising edge of a reference clock signal, and the variation of this reset signal is along aliging with the negative edge of this reference clock signal, as for this circular error scope Te=(q+ (1/2)) * Ts/ (m*n/2).

5. clock signal frequency verifying method as claimed in claim 1, it is characterized in that, non-this first current potential that all is in of measured signal behind detected this frequency division from the 1st time point to a p-q time point, or the signal potential of measured signal is non-behind detected this frequency division on p+1 time point when being in this second current potential, judges that then this signal source of clock is a non-normal working.

6. clock signal frequency verifying device, be applied to verify the accuracy of a clock signal source, it cooperates a reference clock signal and reset signal generation source to move, reference clock signal and reset signal generation source produce a reference clock signal and a reset signal, and this reference clock signal has a predetermined period Ts; It is characterized in that this demo plant comprises:

One frequency divider, be electrically connected on this signal source of clock and this reference clock signal and reset signal and produce the source, it receives the clock signal to be measured that this signal source of clock is exported, and to activation that should reset signal, and begin triggering that should clock signal to be measured and move, and then export measured signal behind the frequency division of a bipotential, wherein this clock signal to be measured has a period 1 T1, behind this frequency division measured signal have one second round T2, and T2/n=T1; And

One compares detecting device, be electrically connected on this frequency divider and this reference clock signal and reset signal and produce the source, it is to the activation that should reset signal and the triggering of this reference clock signal, the signal potential of measured signal after this predetermined period Ts just detects this frequency division, and measured signal is in one first current potential behind detected this frequency division from the 1st time point to a p-q time point, and when the signal potential of measured signal is in one second current potential behind detected this frequency division on p+1 time point, export the circular error scope Te that a signal working properly also can draw this clock signal to be measured.

7. clock signal frequency verifying device as claimed in claim 6 is characterized in that, p=(T2/ (2Ts)), q=(T1/Ts), Te=(q+ (1/2)) * Ts/ (n/2).

8. clock signal frequency verifying device as claimed in claim 7, it is characterized in that, when detect 2p-q time point and 2p+1 time point, a 3p-q time point and 3p+1 time point ... and behind this frequency division on mp-q time point and mp+1 the time point during signal potential of measured signal, this represents circular error scope Te=(q+ (1/2)) the * Ts/ (m*n/2) of this clock signal to be measured when relatively detecting device continues output one signal working properly.

9. clock signal frequency verifying device as claimed in claim 8, it is characterized in that, put this detection time and be the rising edge of this reference clock signal, and the variation of this reset signal is along aliging with the negative edge of this reference clock signal, as for this circular error scope Te=(q+ (1/2)) * Ts/ (m*n/2).

10. clock signal frequency verifying device as claimed in claim 6 is characterized in that, this frequency divider, this comparison detecting device and this signal source of clock are integrated on the same chip.

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