CN1394004A - Method and device for choosing and controlling clock source of synchronous digital optical network - Google Patents
Method and device for choosing and controlling clock source of synchronous digital optical network Download PDFInfo
- Publication number
- CN1394004A CN1394004A CN01113206A CN01113206A CN1394004A CN 1394004 A CN1394004 A CN 1394004A CN 01113206 A CN01113206 A CN 01113206A CN 01113206 A CN01113206 A CN 01113206A CN 1394004 A CN1394004 A CN 1394004A
- Authority
- CN
- China
- Prior art keywords
- clock
- node
- network
- network node
- clock source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to the control method and device for selecting the timing source on the phototiming digit transport network. The distributed control method, which prevents the annular timers, for selecting the timing source is mainly adopted. The optimal timing source used for the network synchronization is automatically selected from the overhead byte SI in the STM-N combined signal between the master/slave node. The control program for selecting the networked timing source according to the invented method is resided on the ROM in each node. The CPU scans the timing signal alarming circuit and the timing sources periodically or controlls the timing signal output at the node as the timing hold mode.
Description
The present invention relates to a kind of clock source selection control of synchronous digital transmission system, specifically, is the selection control method and the device thereof in the clock source of a kind of Optical synchronization digital transmission network (SDH net).
In Optical synchronization digital transmission network (SDH net), each network node all comprises microsystem, nodal clock generative circuit, an I/O light mouth of the Control Network node device work of being made up of CPU (CPU) and ROM (read-only memory) and RAM (random asccess memory) and the input port that is used to insert external timing signal, and adjacent node is connected by communication link.At present, the clock of Optical synchronization digital transmission network adopts grade principal and subordinate method for synchronous more, and all clocks can both finally trace into unique reference clock in the network, and respectively the clock quality from node must be high as much as possible.But when forming closed timing loop in the SDH net, clock can deteriorate into uncertain value, causes data to make mistakes, and can't realize that net synchronously.Therefore, in the present SDH network, mostly the clock source selection of each network node is the priority by network management configuration clock source, guarantees that manually network reaches the Shi Buhui that breaks down in normal operation and clock Cheng Huan occurs, and network node is according to available clock source of this priority selection of configuration.The shortcoming of this way is: the clock source priority of human configuration is not necessarily represented clock source quality situation actual in the network, and for artificial the assurance clock Cheng Huan do not occur in the network, configuration can be more loaded down with trivial details.Chinese patent application 96194572.9 " in a kind of SDH network synchronously " discloses a kind of scheme that prevents that closed timing loop from forming, yet, be only applicable to " a kind of comprise a plurality of nodes that connect by two-way link and Synchronous Digital Hierarchy (SDH) network of an external timing signal ", and needs are understood the node of clock signal process.
The objective of the invention is to provides a kind of distributed clock source selection control method and device that can prevent clock Cheng Huan for the SDH transmission system, the device that use is made by the inventive method, it does not need network management center to intervene again, to main and subordinate node in conjunction with expense in the STM-N signal---synchronization status message byte S1 selects optimum clock source to be used for net synchronously automatically, need not understand the node of this clock signal process, both reached and to prevent to produce timing loop effectively, can select optimum clock source to be used for net synchronously again automatically, and application of the present invention have nothing to do with the SDH network topology.
Method of the present invention, its step comprises:
1. earlier the network node that has inserted external timing signal in the SDH system is designated as the net head; To be designated as crossover node with the network node that at least three other SDH nodes link to each other,
2. during the network node electrifying startup, the clock output of inner crystal oscillator for this node is selected in initialization, and will select optimum clock sign mm_AutoFlag to be changed to TRUE automatically,
If network node neither net head neither crossover node, then according to the clock source of the highest normal (with nowhere to turn to the police) clock source of clock quality of ITU-T Standard Selection as this node, redirect 5 execution then; If network node is net head or crossover node, and breaking down in the clock source of current use, then puts mm_AutoFlag and be masked as FALSE, and starts a timer T
0, redirect 4 is carried out then; Otherwise judge the mm_AutoFlag sign, if mm_AutoFlag=FALSE, also redirect 4 is carried out; If mm_AutoFlag=TRUE, then network node scans external clock reference, inner crystal oscillator and light mouth clock source one by one, according to the clock source of the highest normal (with nowhere to turn to the police) clock source of clock quality of ITU-T Standard Selection as this node, redirect 5 is carried out then, according to the following several clock quality grades that are total to regulation among the ITU-T: G.811 clock signal, G.812 transit exchange's clock signal, G.812 local office clock signal, clock quality do not know, should be as synchronously
4. if timer T
0Be timed to, then put mm_AutoFlag and be masked as TRUE, and enter the optimum clock source module of automatic selection, according to the clock source of the highest normal (with nowhere to turn to the police) clock source of clock quality of ITU-T Standard Selection as this node; Otherwise whether the network node search has trouble-free external clock, if having, then select this external clock source, otherwise enter the maintenance pattern,
5. to the processing of network node S1 byte: if the current selected clock of network node source is an external timing signal, then the S1 byte that outwards sends is the clock quality grade of this external timing signal, so that other network node is synchronized with the clock of present networks node; If the current selected clock of network node source is a light mouth clock, then upwards primary network station node (network node that is connected with the light mouth of selected clock) loopback S1 byte is unavailable (S1=" 1111 "), to prevent that the upper level network node from extracting clock by the light mouth from the present networks node, simultaneously sending S1 byte to other light mouth is the credit rating of selected light mouth clock, so that the next stage network node can be synchronized with the clock of present networks node; If the current selected clock of network node source is for keeping mode clock, then the S1 byte that sends to all light mouths is that clock quality is not known (S1=" 0000 ");
6. loop cycle to 3 is carried out.
The clock source selection control device of the Optical synchronization digital transmission network of the present invention that constitutes according to above-mentioned the inventive method, be installed in each online network node of SDH, this each network node contains link-attached I/O light mouth between a microcomputer of being made up of CPU (CPU), ROM (read-only memory) and RAM (random access memory), network node clock forming circuit node and is used to insert the input port of external timing signal, and characteristics are: also have one to select control program by the network clock source of the invention described above method design; And this program residence is in the ROM of this microcomputer, and this microcomputer moves this program, by this network node clock forming circuit of cpu cycle property ground control, selects control to transmit the clock source signals of net.
Above-mentioned network clock source selects the flow process of control program to be described in detail in conjunction with the embodiments.
Good effect of the present invention will be illustrated by the application of embodiment is described.
Accompanying drawing of the present invention is simply described as follows:
Fig. 1 is the program flow diagram of the inventive method.
Fig. 2 is a current SDH network node clock forming circuit schematic diagram.
Fig. 3 is in the SDH of single loop networking network, and when two kinds of external timing signals of net head access, each node is selected the state diagram of clock and treatment S 1.
Fig. 4 is in SDH network shown in Figure 3, and under the situation that the higher external timing signal of clock credit rating breaks down, each node is selected the state diagram of clock and treatment S 1.
Fig. 5 is in SDH network shown in Figure 4, and in the moment of optical fiber appearance connection fault, each node is selected the state diagram of clock and treatment S 1.
Fig. 6 is in SDH network shown in Figure 4, after optical fiber occurs connecting fault, selects the state diagram of clock and treatment S 1 when each node enters stable state.
Fig. 7 is in a kind of SDH network of phase cross ring of complexity, and a net head is respectively arranged in two loops, all inserts an external timing signal, but under the inconsistent situation of clock quality grade, each node is selected the state diagram of clock and treatment S 1 in the network.
Fig. 8 is in SDH network shown in Figure 7, and when the higher external timing signal of clock credit rating had just broken down, each node was selected the state diagram of clock and treatment S 1 in the network.
Fig. 9 is in SDH network shown in Figure 7, after the higher external timing signal of clock credit rating breaks down, selects the state diagram of clock and treatment S 1 when each node enters stable state in the network.
Below, we are according to Fig. 1---and Fig. 9 provides embodiments of the invention, its objective is for feature of the present invention, function are described, enables to understand better the present invention, rather than is used for limiting the scope of the present invention.
The program circuit of the inventive method as shown in Figure 1.Wherein the network node initialization section is not drawn.During the network node electrifying startup, the clock output of inner crystal oscillator for this node is selected in initialization, and will select optimum clock sign mm_AutoFlag to be changed to TRUE automatically.After initialization finishes, carry out by program circuit circulation shown in Figure 1.At first execution in step 101, judge network node net the head or crossover node? if all be not, then execution in step 104 directly enters the optimum clock source module of automatic selection and selects the clock source that clock quality is the highest, can guarantee neither net head and be not that the network node of crossover node can not occur and adjacent network node clock Cheng Huan because handle by the S1 byte of this method; If network node is net head or crossover node, then execution in step 102, check current selected clock source break down (have alarm, clock quality to reduce or S1 byte becomes unavailable)? if there is fault in the present clock source, then execution in step 107, put mm_AutoFlag and be masked as FALSE, and execution in step 108, timer T is set
0, execution in step 109 then, judge whether the present networks node is connected to normal external timing signal, thus execution in step 110 is selected external timing signal or execution in step 111, selects to keep mode clock; If the present clock source does not have fault, then execution in step 103, judge the mm_AutoFlag sign, if mm_AutoFlag is TRUE, enters the optimum clock source module of automatic selection with regard to execution in step 104 and select the clock source that clock quality is the highest; If mm_AutoFlag is FALSE, then execution in step 105 is at first judged timer T
0Regularly arrive? if timer T
0Regularly arrive, then execution in step 106, put mm_AutoFlag and are masked as TRUE, and execution in step 104 then, carry out and select optimum clock source program automatically; If timer T
0Regularly no show, then execution in step 109, judge whether the present networks node is connected to normal external timing signal, thus execution in step 110 is selected external timing signal or execution in step 111, selects to keep mode clock.For net head or crossover node, can not directly enter the optimum clock source module of automatic selection when why breaking down and select the clock source that clock quality is the highest in the present clock source, be because this node might be as the next stage network node of another network node, and another network node is available by the light mouth to the S1 byte that this node sends, and this S1 byte has been got back to self for the S1 byte that is sent before own through a loop.By the back T that breaks down at present clock
0In time, execution in step 110 or step 111, and behind the S1 byte handling procedure below carrying out, can eliminate this situation.Therefore, through T
0After time, but execution in step 106 put mm_AutoFlag and be masked as TRUE and begin execution in step 104, select optimum clock source automatically by S1 byte.
When network node is selected optimum clock source automatically, network node scans external clock reference, inner crystal oscillator and light mouth clock source one by one, selects the clock source of the highest normal (with nowhere to turn to the police) clock source of clock quality as this node according to the S1 byte state in each clock source.For network node,, then preferentially select external timing signal or keep mode clock if light mouth clock source quality grade is identical with external timing signal or the inner crystal oscillator credit rating that this node inserts as the net head; For the network node that is not the net head, if light mouth clock source quality grade is identical with the inner crystal oscillator credit rating of this node, then preferential selective light mouth clock source.Through above-mentioned processing, just can realize netting the clock source of head to other network node output of the whole network oneself, other network node then is synchronized with the net head by the defeated clock source of coming of light oral instructions.
After choosing the clock source, follow execution in step 112, treatment S 1 byte: if the current selected clock of network node source is an external timing signal, then execution in step 113, outwards the S1 byte that sends is the clock quality grade of this external timing signal, so that other network node is synchronized with the clock of present networks node; If the current selected clock of network node source is a light mouth clock, then execution in step 114, look into light mouth connection table, determine to exist several light mouths to be connected between this node and superior node according to the light slogan of locked clock, execution in step 115 then, the S1 byte that sends to the light mouth that is connected with superior node is unavailable (S1=" 1111 "), to prevent that the upper level network node from extracting clock by the light mouth from the present networks node, simultaneously sending S1 byte to other light mouth is the credit rating of selected light mouth clock, so that the next stage network node can be synchronized with the clock of present networks node; If the current selected clock of network node source is for keeping mode clock, then execution in step 116, do not know (S1=" 0000 ") to all light mouth tranmitting data register quality.
Fig. 2 is a hardware block diagram of realizing the SDH network node clock part of the inventive method, and the software of realizing the inventive method just resides on the rom chip in the network node.Cpu cycle ground scan clock signal alarm detection circuit 20 and clock signal S1 byte testing circuit 21, carry out the Automatic Program of the inventive method according to the alarm status in each clock source and clock quality and select the clock source that clock quality is the highest, that controls then that clock reference selects circuit 22 exports phase-locked loop circuit 23 phase-locked back clock signals to.If the external clock signal is all unavailable, CPU can directly control phase-locked loop circuit 23 in 233 outputs of D/A and amplifying circuit, make clock signal be output as the maintenance mode clock.
Fig. 3 is a kind of schematic diagram of SDH network of ring type structure.Wherein, node 1 is the net head, and it has inserted two external timing signals, and wherein external timing signal 1 is clock G.811, and external timing signal 2 is transit exchange's clock G.812.Node 2,3,4 all is not the net head, and is not crossover node, according to the present invention, and resident respectively Optical synchronization digital transmission network clock source selection Control Software of the present invention in above-mentioned node 1,2,3,4.
Therefore, node 1 just enters the optimum clock source module of automatic selection through after the initialization.Because the clock quality of external timing signal 1 is higher than external timing signal 2, so node 1 is selected the clock source of external timing signal 1 as oneself.In order to allow the SDH node of the whole network be synchronized with oneself clock signal, the S1 byte that node 1 is outwards sent out is clock quality grade G.811, and node 2 will be synchronized with the clock that node 1 sends from the light mouth, i.e. light mouth 1 clock.In order to allow next node (node 3) be synchronized with the clock of node 2, the S1 byte that node 2 sends to node 3 is clock quality grade G.811; Simultaneously occur clock signal Cheng Huan (being that node 1 and node 2 extract clock from the other side mutually) between node 1 and the node 2 in order to prevent, node 2 is to node 1 loopback clock quality unavailable (S1=" 1111 ").In like manner, node 3 selective light mouths 1 clock, and the S1 byte that sends to node 4 is clock quality grade G.811.For node 4, because the credit rating in two light mouth clock sources is identical, it will select one of them clock source as oneself at random.Suppose node 4 selective light mouths 1 clock, then it is unavailable to node 3 loopback clock qualities, and the S1 byte that sends to next node (node 1) is clock quality grade G.811.
When the external timing signal 1 of node 1 breaks down, extract light mouth clock in order to prevent node 1 from node 4, node 1 is provided with timer T earlier
0, and because node 1 inserted external timing signal 2, so it is with the clock source of external timing signal 2 as oneself, outside simultaneously transmission S1 byte is transit exchange's clock quality grade G.812.And node 2, node 3 and node 4 are selected to be still locking light mouth 1 clock behind the optimum clock automatically, and the S1 byte that sends to next node changes to G.812 transit exchange's clock quality grade simultaneously.Through T
0After time, the S1 byte (G.811 clock quality grade) that the whole network has been sent when not existed node 1 to select external timing signal 1, therefore, node 1 enters normally and selects optimum clock source according to S1 byte, the S1 byte that this moment, it read from light mouth 1 is transit exchange's clock quality grade G.812, because this clock quality grade is not higher than the clock quality grade of the external timing signal 2 of own current locking, it will keep locking external timing signal 2 constant.Therefore, the whole network clock still is synchronized with the clock source of node 1, as shown in Figure 4.
When the optical fiber between node 1 and the node 2 occurred connecting fault, as shown in Figure 5, node 1 still locked external timing signal 2.Node 2 is because light mouth 1 clock has alarm, and the S1 byte of light mouth 2 clocks is that clock quality is unavailable, so the clock of node 2 will enter the maintenance pattern.For node 3, because the clock quality grade (clock quality is not known) of light mouth 1 is higher than the clock quality grade (unavailable) of light mouth 2, still lock light mouth 1 clock, and the clock quality grade that sends to node 4 is that clock quality is not known.The clock quality grade (G.812 transit exchange) of the very fast discovery light of node 4 mouth 2 is higher than the clock quality grade (clock quality is not known) of light mouth 1, therefore the clock switching takes place in node 4, light mouth 2 clocks have been selected, the S1 byte that sends to node 3 becomes G.812 transit exchange's clock quality grade, therefore, clock also takes place and switches in node 3, has selected light mouth 2 clocks.In like manner, node 3 becomes G.812 transit exchange's clock quality grade to the S1 byte that node 2 sends, and therefore, node 2 has been selected light mouth 2 clocks after oversampling clock switches.After each node of network entered stable state, the state diagram of selection clock and treatment S 1 as shown in Figure 6.
Consider more complicated SDH networking situation, as shown in Figure 7.In this network, node 1,2,3,4,5 connects by two two-way links, and simultaneously, node 3,4,8,7,6 is formed a loop again.Wherein, node 1 inserts a G.811 external timing signal 1 of clock quality grade, and node 7 inserts a G.812 external timing signal 2 of transit exchange's clock quality grade.Same as the previously described embodiments, each network node 1,2,3,4,5,6,7,8, the ROM of equipment on all resident Optical synchronization digital transmission network clock source selection Control Software of the present invention that has as shown in Figure 1.When network normally moved, because G.811 the credit rating of the external timing signal 1 that node 1 inserts is higher than the G.812 transit exchange clock quality grade of the external timing signal 2 of node 7 accesses, so the whole network was unified in locking clock source G.811.
When the external timing signal 1 of node 1 access breaks down, owing to there is not available external timing signal, node 1 will enter the maintenance pattern, and the S1 byte that outwards sends is that clock quality is not known simultaneously.Node 2 still locks light mouth 1 clock, and does not know to node 3 tranmitting data register quality.The clock quality of finding the light mouth 1 clock source of own current locking when node 3 reduces (not knowing by G.811 reducing to clock quality), and it enters the maintenance pattern immediately, and outwards sending S1 byte simultaneously is that clock quality is not known.The clock quality that node 4 also detects the light mouth 1 clock source of own current locking very soon reduces (not knowing by G.811 reducing to clock quality), it also enters the maintenance pattern immediately, in case extract clock from light mouth 5, outwards sending S1 byte simultaneously is that clock quality is not known.It is constant that node 5,6 then still locks light mouth 1 clock.After the clock quality that detects the light mouth 1 clock source of own current locking when node 7 reduced (not knowing by G.811 reducing to clock quality), it switched to external timing signal 2 at once, and outwards sent S1 byte and be transit exchange's clock quality grade G.812.The clock quality grade (G.812 transit exchange) of the very fast discovery light of node 6 mouth 2 is higher than the clock quality grade (clock quality is not known) of light mouth 1, so node 6 generation clocks switchings, has selected light mouth 2 clocks.It is constant that node 8 still locks light mouth 1 clock.The processing of each node selected clock of network and S1 byte at this moment as shown in Figure 8.
Node 3 keeps T
0After time, enter normally and select optimum clock source automatically according to S1 byte, find the highest grade of clock quality (G.812 transit exchange) of light mouth 6, so clock source of selective light mouth 6, S1 byte to 6 loopbacks of light mouth is that clock quality is unavailable, and other light mouth sends S1 byte and is clock quality grade G.812.In like manner, node 4 keeps T
0Light mouth 5 clocks have been selected after time.Automatically select optimum clock source and node 2 and 5 is also very fast according to S1 byte.Soon, node 1 also extracts the clock source from light mouth 1, and this moment, the whole network was unified in the clock source of the G.812 transit exchange credit rating of latch node 7 accesses, as shown in Figure 9.
In sum, the topology of application of the present invention and SDH net is irrelevant.
Advantage of the present invention is, according to SDH clock selecting control method provided by the present invention and device, net Each node distributed earth of network is according to the overhead byte in the SDH frame structure---and S1 byte is selected optimum clock automatically The source has realized that the whole network automatic synchronization in an optimum clock source, need not manual intervention, and can not occur the time The Zhong Chenghuan phenomenon. And the present invention is applicable to randomly topologically structured SDH network.
Claims (3)
1. Optical synchronization digital transmission network clock source selection control method, its step comprises:
A, the network node that has inserted external timing signal in the SDH system is designated as net head, will be designated as crossover node with the network node that at least three other SDH nodes link to each other,
The clock output of inner crystal oscillator for this node is selected in initialization when b, network node electrifying startup, and will select optimum clock sign mm_AutoFlag to be changed to TRUE automatically,
C, if network node neither net head neither crossover node, then according to the clock source of the highest normal clock source of clock quality of ITU-T Standard Selection as this node, then, redirect 5 is carried out; If network node is net head or crossover node, and breaking down in the clock source of current use, then puts mm_AutoFlag and be masked as FALSE, and starts a timer T
0, redirect 4 is carried out then; Otherwise, judge the mm_AutoFlag sign, if mm_AutoFlag=FALSE, also redirect 4 is carried out; If mm_AutoFlag=TRUE, then network node scans external clock reference, inner crystal oscillator and light mouth clock source one by one, and according to the clock source of the highest normal clock source of clock quality of ITU-T Standard Selection as this node, redirect 5 is carried out then,
D, if timer T
0Be timed to, then put mm_AutoFlag and be masked as TRUE, and enter the optimum clock source module of automatic selection, according to the clock source of the highest normal clock source of clock quality of ITU-T Standard Selection as this node; Does otherwise whether the network node search also have another trouble-free external clock? if have, then select this external clock source, otherwise, enter the maintenance pattern,
E, to the processing of network node S1 byte: if the current selected clock of network node source is an external timing signal, then the S1 byte that outwards sends is the clock quality grade of this external timing signal, so that other network node is synchronized with the clock of present networks node; If the current selected clock of network node source is its light mouth clock, then upwards primary network station node loopback S1 byte is unavailable, represent with S1=1111, to prevent that the upper level network node from extracting clock by the light mouth from the present networks node, simultaneously sending S1 byte to other light mouth is the credit rating of selected light mouth clock, so that the next stage network node can be synchronized with the clock of present networks node; If the current selected clock of network node source is for keeping mode clock, then the S1 byte that sends to all light mouths is that clock quality is not known, represent with S1=0000,
F, loop cycle to 3 are carried out.
2. the clock source selection control device of an Optical synchronization digital transmission network of making by the described Optical synchronization digital transmission network clock source selection of claim 1 control method, system is installed in each network node, this each network node includes one by CPU, the microcomputer that read-only memory and random access memory are formed, link-attached I/O light mouth and the input port that is used to insert external timing signal between a network node clock forming circuit node, it is characterized in that, also has a network clock source selection control program by the design of the described Optical synchronization digital transmission network clock source selection of claim 1 control method, and, this program residence is in the read-only memory of this microcomputer, this microcomputer moves this program and controls this network node clock forming circuit periodically, transmits the clock source signals of net to select control.
3. Optical synchronization digital transmission network clock source selection control device according to claim 2 is characterized in that, said network clock source is selected control program, and its flow process and starts the back circulation and carries out as shown in Figure 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB01113206XA CN1281005C (en) | 2001-06-29 | 2001-06-29 | Method and device for choosing and controlling clock source of synchronous digital optical network |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB01113206XA CN1281005C (en) | 2001-06-29 | 2001-06-29 | Method and device for choosing and controlling clock source of synchronous digital optical network |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1394004A true CN1394004A (en) | 2003-01-29 |
| CN1281005C CN1281005C (en) | 2006-10-18 |
Family
ID=4659948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB01113206XA Expired - Fee Related CN1281005C (en) | 2001-06-29 | 2001-06-29 | Method and device for choosing and controlling clock source of synchronous digital optical network |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1281005C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008101394A1 (en) * | 2007-02-13 | 2008-08-28 | Shan Dong University | Real-time synchronous method and synchronous network based on the standard ethernet |
| CN101192913B (en) * | 2007-08-08 | 2010-12-08 | 中兴通讯股份有限公司 | A system and method for clock synchronization and clock switch over optical transmission network |
| CN102077493A (en) * | 2008-04-30 | 2011-05-25 | 惠普开发有限公司 | Intentionally skewed optical clock signal distribution |
| CN102317885A (en) * | 2011-07-26 | 2012-01-11 | 华为技术有限公司 | Computer system and method of configuring clock thereof |
| CN101316149B (en) * | 2008-07-16 | 2012-05-16 | 中兴通讯股份有限公司 | Method and device for expansion leading out clock function in SDH equipment |
| CN102469484A (en) * | 2010-11-15 | 2012-05-23 | 中国移动通信集团公司 | Base station out-of-service method, base station and time server |
| CN104238413A (en) * | 2014-09-05 | 2014-12-24 | 四川和芯微电子股份有限公司 | External crystal oscillator judging circuit of SOC system chip |
| CN104854531A (en) * | 2012-12-13 | 2015-08-19 | 相干逻辑公司 | Reconfiguration of clock generation circuitry |
-
2001
- 2001-06-29 CN CNB01113206XA patent/CN1281005C/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008101394A1 (en) * | 2007-02-13 | 2008-08-28 | Shan Dong University | Real-time synchronous method and synchronous network based on the standard ethernet |
| CN101192913B (en) * | 2007-08-08 | 2010-12-08 | 中兴通讯股份有限公司 | A system and method for clock synchronization and clock switch over optical transmission network |
| CN102077493B (en) * | 2008-04-30 | 2015-01-14 | 惠普开发有限公司 | Intentionally skewed optical clock signal distribution |
| CN102077493A (en) * | 2008-04-30 | 2011-05-25 | 惠普开发有限公司 | Intentionally skewed optical clock signal distribution |
| CN101316149B (en) * | 2008-07-16 | 2012-05-16 | 中兴通讯股份有限公司 | Method and device for expansion leading out clock function in SDH equipment |
| CN102469484A (en) * | 2010-11-15 | 2012-05-23 | 中国移动通信集团公司 | Base station out-of-service method, base station and time server |
| CN102469484B (en) * | 2010-11-15 | 2015-02-04 | 中国移动通信集团公司 | Base station out-of-service method, base station and time server |
| CN102317885A (en) * | 2011-07-26 | 2012-01-11 | 华为技术有限公司 | Computer system and method of configuring clock thereof |
| CN102317885B (en) * | 2011-07-26 | 2014-05-07 | 华为技术有限公司 | Computer system and method of configuring clock thereof |
| WO2012106929A1 (en) * | 2011-07-26 | 2012-08-16 | 华为技术有限公司 | Computer system and clock configuration method thereof |
| US9026835B2 (en) | 2011-07-26 | 2015-05-05 | Huawei Technologies Co., Ltd. | Computer system for configuring a clock |
| CN104854531A (en) * | 2012-12-13 | 2015-08-19 | 相干逻辑公司 | Reconfiguration of clock generation circuitry |
| CN104854531B (en) * | 2012-12-13 | 2018-05-18 | 相干逻辑公司 | Clock generating circuit reconfigures |
| CN104238413A (en) * | 2014-09-05 | 2014-12-24 | 四川和芯微电子股份有限公司 | External crystal oscillator judging circuit of SOC system chip |
| CN104238413B (en) * | 2014-09-05 | 2017-02-01 | 四川和芯微电子股份有限公司 | External crystal oscillator judging circuit of SOC system chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1281005C (en) | 2006-10-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5475717A (en) | Method of ensuring that each node of a private telecommunication network is synchronized to the best available clock at all times | |
| EP0667997B1 (en) | A hierarchical synchronization method and a telecommunications system employing message-based synchronization | |
| US5878095A (en) | Hierarchical synchronization method | |
| CN1281005C (en) | Method and device for choosing and controlling clock source of synchronous digital optical network | |
| JP2000216741A (en) | Synchronizing of network elements in synchronous digital communication network | |
| EP0748547B1 (en) | Hierarchical synchronization method | |
| US5706291A (en) | Method and apparatus for connecting two messaging systems having differing synchronizations one of which is message-based | |
| JP2000209245A (en) | Network synchronizing controller and method for preventing occurrence of timing loop | |
| EP0667996B1 (en) | Network arrangement | |
| US5796793A (en) | Hierarchical synchronization method | |
| US5841779A (en) | Hierarchical synchronization method | |
| CN100407605C (en) | Synchronous method for optical synchronous digital network | |
| AU680879B2 (en) | Method for synchronizing interconnected sdh and pdh telecommunications networks | |
| WO1994011965A1 (en) | A hierarchical synchronization method and a telecommunications system employing message-based synchronization | |
| JP4181867B2 (en) | Synchronous network establishment method and apparatus | |
| WO1994011964A1 (en) | Hierarchical synchronization method | |
| EP0872083B1 (en) | Implementing a fault-tolerant bus in a telecommunications network | |
| WO1994011963A1 (en) | A hierarchical synchronization method and a telecommunications system employing message-based synchronization |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHENZHENG CITY ZTE CO., LTD. Free format text: FORMER OWNER: SHENZHENG CITY ZTE CO., LTD. SHANGHAI SECOND INSTITUTE Effective date: 20030724 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20030724 Applicant after: Zhongxing Communication Co., Ltd., Shenzhen City Applicant before: Shanghai Inst. of No.2, Zhongxing Communication Co., Ltd., Shenzhen City |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20061018 Termination date: 20100629 |